diff --git a/hardware/v2/ddr3/litedram_gen/ecp5_85f_ddr3_mt41k256m16.yml b/hardware/v2/ddr3/litedram_gen/ecp5_85f_ddr3_mt41k256m16.yml new file mode 100644 index 0000000..ae972ca --- /dev/null +++ b/hardware/v2/ddr3/litedram_gen/ecp5_85f_ddr3_mt41k256m16.yml @@ -0,0 +1,15 @@ +device: "LFE5U-85F-8BG381C" +cpu: "None" +memtype: "DDR3" +sdram_phy: "ECP5DDRPHY" +sdram_module: "MT41K256M16" +sdram_module_nb: 2 +sdram_rank_nb: 1 +input_clk_freq: 16e6 +sys_clk_freq: 75e6 +init_clk_freq: 25e6 +cmd_latency: 0 +speedgrade: -8 +user_ports: + native_0: + type: "native" diff --git a/hardware/v2/ddr3/litedram_gen/generated_headers/csr.h b/hardware/v2/ddr3/litedram_gen/generated_headers/csr.h new file mode 100644 index 0000000..f9f1524 --- /dev/null +++ b/hardware/v2/ddr3/litedram_gen/generated_headers/csr.h @@ -0,0 +1,279 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by LiteX (9ad3ecf74) on 2026-09-16 08:16:18 +//-------------------------------------------------------------------------------- + +//-------------------------------------------------------------------------------- +// CSR Includes. +//-------------------------------------------------------------------------------- + +#include +#ifndef __GENERATED_CSR_H +#define __GENERATED_CSR_H +#include +#include +#ifndef CSR_ACCESSORS_DEFINED +#include +#endif /* ! CSR_ACCESSORS_DEFINED */ + +#ifndef CSR_BASE +#define CSR_BASE 0x0L +#endif /* ! CSR_BASE */ + +//-------------------------------------------------------------------------------- +// CSR Registers/Fields Definition. +//-------------------------------------------------------------------------------- + +/* DDRCTRL Registers */ +#define CSR_DDRCTRL_BASE (CSR_BASE + 0x0L) +#define CSR_DDRCTRL_INIT_DONE_ADDR (CSR_BASE + 0x0L) +#define CSR_DDRCTRL_INIT_DONE_SIZE 1 +#define CSR_DDRCTRL_INIT_ERROR_ADDR (CSR_BASE + 0x4L) +#define CSR_DDRCTRL_INIT_ERROR_SIZE 1 + +/* DDRCTRL Fields */ + +/* DDRPHY Registers */ +#define CSR_DDRPHY_BASE (CSR_BASE + 0x800L) +#define CSR_DDRPHY_DLY_SEL_ADDR (CSR_BASE + 0x800L) +#define CSR_DDRPHY_DLY_SEL_SIZE 1 +#define CSR_DDRPHY_RDLY_DQ_RST_ADDR (CSR_BASE + 0x804L) +#define CSR_DDRPHY_RDLY_DQ_RST_SIZE 1 +#define CSR_DDRPHY_RDLY_DQ_INC_ADDR (CSR_BASE + 0x808L) +#define CSR_DDRPHY_RDLY_DQ_INC_SIZE 1 +#define CSR_DDRPHY_RDLY_DQ_BITSLIP_RST_ADDR (CSR_BASE + 0x80cL) +#define CSR_DDRPHY_RDLY_DQ_BITSLIP_RST_SIZE 1 +#define CSR_DDRPHY_RDLY_DQ_BITSLIP_ADDR (CSR_BASE + 0x810L) +#define CSR_DDRPHY_RDLY_DQ_BITSLIP_SIZE 1 +#define CSR_DDRPHY_BURSTDET_CLR_ADDR (CSR_BASE + 0x814L) +#define CSR_DDRPHY_BURSTDET_CLR_SIZE 1 +#define CSR_DDRPHY_BURSTDET_SEEN_ADDR (CSR_BASE + 0x818L) +#define CSR_DDRPHY_BURSTDET_SEEN_SIZE 1 + +/* DDRPHY Fields */ + +/* SDRAM Registers */ +#define CSR_SDRAM_BASE (CSR_BASE + 0x1000L) +#define CSR_SDRAM_DFII_CONTROL_ADDR (CSR_BASE + 0x1000L) +#define CSR_SDRAM_DFII_CONTROL_SIZE 1 +#define CSR_SDRAM_DFII_PI0_COMMAND_ADDR (CSR_BASE + 0x1004L) +#define CSR_SDRAM_DFII_PI0_COMMAND_SIZE 1 +#define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_ADDR (CSR_BASE + 0x1008L) +#define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_SIZE 1 +#define CSR_SDRAM_DFII_PI0_ADDRESS_ADDR (CSR_BASE + 0x100cL) +#define CSR_SDRAM_DFII_PI0_ADDRESS_SIZE 1 +#define CSR_SDRAM_DFII_PI0_BADDRESS_ADDR (CSR_BASE + 0x1010L) +#define CSR_SDRAM_DFII_PI0_BADDRESS_SIZE 1 +#define CSR_SDRAM_DFII_PI0_WRDATA_ADDR (CSR_BASE + 0x1014L) +#define CSR_SDRAM_DFII_PI0_WRDATA_SIZE 2 +#define CSR_SDRAM_DFII_PI0_RDDATA_ADDR (CSR_BASE + 0x101cL) +#define CSR_SDRAM_DFII_PI0_RDDATA_SIZE 2 +#define CSR_SDRAM_DFII_PI1_COMMAND_ADDR (CSR_BASE + 0x1024L) +#define CSR_SDRAM_DFII_PI1_COMMAND_SIZE 1 +#define CSR_SDRAM_DFII_PI1_COMMAND_ISSUE_ADDR (CSR_BASE + 0x1028L) +#define CSR_SDRAM_DFII_PI1_COMMAND_ISSUE_SIZE 1 +#define CSR_SDRAM_DFII_PI1_ADDRESS_ADDR (CSR_BASE + 0x102cL) +#define CSR_SDRAM_DFII_PI1_ADDRESS_SIZE 1 +#define CSR_SDRAM_DFII_PI1_BADDRESS_ADDR (CSR_BASE + 0x1030L) +#define CSR_SDRAM_DFII_PI1_BADDRESS_SIZE 1 +#define CSR_SDRAM_DFII_PI1_WRDATA_ADDR (CSR_BASE + 0x1034L) +#define CSR_SDRAM_DFII_PI1_WRDATA_SIZE 2 +#define CSR_SDRAM_DFII_PI1_RDDATA_ADDR (CSR_BASE + 0x103cL) +#define CSR_SDRAM_DFII_PI1_RDDATA_SIZE 2 + +/* SDRAM Fields */ +#define CSR_SDRAM_DFII_CONTROL_SEL_OFFSET 0 +#define CSR_SDRAM_DFII_CONTROL_SEL_SIZE 1 +#define CSR_SDRAM_DFII_CONTROL_CKE_OFFSET 1 +#define CSR_SDRAM_DFII_CONTROL_CKE_SIZE 1 +#define CSR_SDRAM_DFII_CONTROL_ODT_OFFSET 2 +#define CSR_SDRAM_DFII_CONTROL_ODT_SIZE 1 +#define CSR_SDRAM_DFII_CONTROL_RESET_N_OFFSET 3 +#define CSR_SDRAM_DFII_CONTROL_RESET_N_SIZE 1 +#define CSR_SDRAM_DFII_PI0_COMMAND_CS_OFFSET 0 +#define CSR_SDRAM_DFII_PI0_COMMAND_CS_SIZE 1 +#define CSR_SDRAM_DFII_PI0_COMMAND_WE_OFFSET 1 +#define CSR_SDRAM_DFII_PI0_COMMAND_WE_SIZE 1 +#define CSR_SDRAM_DFII_PI0_COMMAND_CAS_OFFSET 2 +#define CSR_SDRAM_DFII_PI0_COMMAND_CAS_SIZE 1 +#define CSR_SDRAM_DFII_PI0_COMMAND_RAS_OFFSET 3 +#define CSR_SDRAM_DFII_PI0_COMMAND_RAS_SIZE 1 +#define CSR_SDRAM_DFII_PI0_COMMAND_WREN_OFFSET 4 +#define CSR_SDRAM_DFII_PI0_COMMAND_WREN_SIZE 1 +#define CSR_SDRAM_DFII_PI0_COMMAND_RDEN_OFFSET 5 +#define CSR_SDRAM_DFII_PI0_COMMAND_RDEN_SIZE 1 +#define CSR_SDRAM_DFII_PI0_COMMAND_CS_TOP_OFFSET 6 +#define CSR_SDRAM_DFII_PI0_COMMAND_CS_TOP_SIZE 1 +#define CSR_SDRAM_DFII_PI0_COMMAND_CS_BOTTOM_OFFSET 7 +#define CSR_SDRAM_DFII_PI0_COMMAND_CS_BOTTOM_SIZE 1 +#define CSR_SDRAM_DFII_PI1_COMMAND_CS_OFFSET 0 +#define CSR_SDRAM_DFII_PI1_COMMAND_CS_SIZE 1 +#define CSR_SDRAM_DFII_PI1_COMMAND_WE_OFFSET 1 +#define CSR_SDRAM_DFII_PI1_COMMAND_WE_SIZE 1 +#define CSR_SDRAM_DFII_PI1_COMMAND_CAS_OFFSET 2 +#define CSR_SDRAM_DFII_PI1_COMMAND_CAS_SIZE 1 +#define CSR_SDRAM_DFII_PI1_COMMAND_RAS_OFFSET 3 +#define CSR_SDRAM_DFII_PI1_COMMAND_RAS_SIZE 1 +#define CSR_SDRAM_DFII_PI1_COMMAND_WREN_OFFSET 4 +#define CSR_SDRAM_DFII_PI1_COMMAND_WREN_SIZE 1 +#define CSR_SDRAM_DFII_PI1_COMMAND_RDEN_OFFSET 5 +#define CSR_SDRAM_DFII_PI1_COMMAND_RDEN_SIZE 1 +#define CSR_SDRAM_DFII_PI1_COMMAND_CS_TOP_OFFSET 6 +#define CSR_SDRAM_DFII_PI1_COMMAND_CS_TOP_SIZE 1 +#define CSR_SDRAM_DFII_PI1_COMMAND_CS_BOTTOM_OFFSET 7 +#define CSR_SDRAM_DFII_PI1_COMMAND_CS_BOTTOM_SIZE 1 + +//-------------------------------------------------------------------------------- +// CSR Registers Access Functions. +//-------------------------------------------------------------------------------- + +#ifndef LITEX_CSR_ACCESS_FUNCTIONS +#define LITEX_CSR_ACCESS_FUNCTIONS 1 +#endif + +#if LITEX_CSR_ACCESS_FUNCTIONS + +/* DDRCTRL Access Functions */ +static inline uint32_t ddrctrl_init_done_read(void) { + return csr_read_simple((CSR_BASE + 0x0L)); +} +static inline void ddrctrl_init_done_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x0L)); +} +static inline uint32_t ddrctrl_init_error_read(void) { + return csr_read_simple((CSR_BASE + 0x4L)); +} +static inline void ddrctrl_init_error_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x4L)); +} + +/* DDRPHY Access Functions */ +static inline uint32_t ddrphy_dly_sel_read(void) { + return csr_read_simple((CSR_BASE + 0x800L)); +} +static inline void ddrphy_dly_sel_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x800L)); +} +static inline uint32_t ddrphy_rdly_dq_rst_read(void) { + return csr_read_simple((CSR_BASE + 0x804L)); +} +static inline void ddrphy_rdly_dq_rst_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x804L)); +} +static inline uint32_t ddrphy_rdly_dq_inc_read(void) { + return csr_read_simple((CSR_BASE + 0x808L)); +} +static inline void ddrphy_rdly_dq_inc_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x808L)); +} +static inline uint32_t ddrphy_rdly_dq_bitslip_rst_read(void) { + return csr_read_simple((CSR_BASE + 0x80cL)); +} +static inline void ddrphy_rdly_dq_bitslip_rst_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x80cL)); +} +static inline uint32_t ddrphy_rdly_dq_bitslip_read(void) { + return csr_read_simple((CSR_BASE + 0x810L)); +} +static inline void ddrphy_rdly_dq_bitslip_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x810L)); +} +static inline uint32_t ddrphy_burstdet_clr_read(void) { + return csr_read_simple((CSR_BASE + 0x814L)); +} +static inline void ddrphy_burstdet_clr_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x814L)); +} +static inline uint32_t ddrphy_burstdet_seen_read(void) { + return csr_read_simple((CSR_BASE + 0x818L)); +} + +/* SDRAM Access Functions */ +static inline uint32_t sdram_dfii_control_read(void) { + return csr_read_simple((CSR_BASE + 0x1000L)); +} +static inline void sdram_dfii_control_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x1000L)); +} +static inline uint32_t sdram_dfii_pi0_command_read(void) { + return csr_read_simple((CSR_BASE + 0x1004L)); +} +static inline void sdram_dfii_pi0_command_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x1004L)); +} +static inline uint32_t sdram_dfii_pi0_command_issue_read(void) { + return csr_read_simple((CSR_BASE + 0x1008L)); +} +static inline void sdram_dfii_pi0_command_issue_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x1008L)); +} +static inline uint32_t sdram_dfii_pi0_address_read(void) { + return csr_read_simple((CSR_BASE + 0x100cL)); +} +static inline void sdram_dfii_pi0_address_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x100cL)); +} +static inline uint32_t sdram_dfii_pi0_baddress_read(void) { + return csr_read_simple((CSR_BASE + 0x1010L)); +} +static inline void sdram_dfii_pi0_baddress_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x1010L)); +} +static inline uint64_t sdram_dfii_pi0_wrdata_read(void) { + uint64_t r = csr_read_simple((CSR_BASE + 0x1014L)); + r <<= 32; + r |= csr_read_simple((CSR_BASE + 0x1018L)); + return r; +} +static inline void sdram_dfii_pi0_wrdata_write(uint64_t v) { + csr_write_simple(v >> 32, (CSR_BASE + 0x1014L)); + csr_write_simple(v, (CSR_BASE + 0x1018L)); +} +static inline uint64_t sdram_dfii_pi0_rddata_read(void) { + uint64_t r = csr_read_simple((CSR_BASE + 0x101cL)); + r <<= 32; + r |= csr_read_simple((CSR_BASE + 0x1020L)); + return r; +} +static inline uint32_t sdram_dfii_pi1_command_read(void) { + return csr_read_simple((CSR_BASE + 0x1024L)); +} +static inline void sdram_dfii_pi1_command_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x1024L)); +} +static inline uint32_t sdram_dfii_pi1_command_issue_read(void) { + return csr_read_simple((CSR_BASE + 0x1028L)); +} +static inline void sdram_dfii_pi1_command_issue_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x1028L)); +} +static inline uint32_t sdram_dfii_pi1_address_read(void) { + return csr_read_simple((CSR_BASE + 0x102cL)); +} +static inline void sdram_dfii_pi1_address_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x102cL)); +} +static inline uint32_t sdram_dfii_pi1_baddress_read(void) { + return csr_read_simple((CSR_BASE + 0x1030L)); +} +static inline void sdram_dfii_pi1_baddress_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x1030L)); +} +static inline uint64_t sdram_dfii_pi1_wrdata_read(void) { + uint64_t r = csr_read_simple((CSR_BASE + 0x1034L)); + r <<= 32; + r |= csr_read_simple((CSR_BASE + 0x1038L)); + return r; +} +static inline void sdram_dfii_pi1_wrdata_write(uint64_t v) { + csr_write_simple(v >> 32, (CSR_BASE + 0x1034L)); + csr_write_simple(v, (CSR_BASE + 0x1038L)); +} +static inline uint64_t sdram_dfii_pi1_rddata_read(void) { + uint64_t r = csr_read_simple((CSR_BASE + 0x103cL)); + r <<= 32; + r |= csr_read_simple((CSR_BASE + 0x1040L)); + return r; +} +#endif /* LITEX_CSR_ACCESS_FUNCTIONS */ + +#endif /* ! __GENERATED_CSR_H */ diff --git a/hardware/v2/ddr3/litedram_gen/generated_headers/git.h b/hardware/v2/ddr3/litedram_gen/generated_headers/git.h new file mode 100644 index 0000000..5ba3621 --- /dev/null +++ b/hardware/v2/ddr3/litedram_gen/generated_headers/git.h @@ -0,0 +1,8 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by LiteX (9ad3ecf74) on 2026-09-16 08:16:18 +//-------------------------------------------------------------------------------- +#ifndef __GENERATED_GIT_H +#define __GENERATED_GIT_H + +#define LITEX_GIT_SHA1 "9ad3ecf74" +#endif diff --git a/hardware/v2/ddr3/litedram_gen/generated_headers/mem.h b/hardware/v2/ddr3/litedram_gen/generated_headers/mem.h new file mode 100644 index 0000000..cc33ff6 --- /dev/null +++ b/hardware/v2/ddr3/litedram_gen/generated_headers/mem.h @@ -0,0 +1,20 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by LiteX (9ad3ecf74) on 2026-09-16 08:16:18 +//-------------------------------------------------------------------------------- +#ifndef __GENERATED_MEM_H +#define __GENERATED_MEM_H + +#ifndef CSR_BASE +#define CSR_BASE 0x00000000L +#define CSR_BASE_VA 0x00000000L +#define CSR_SIZE 0x00010000 +#endif + +#ifndef MEM_REGIONS +#define MEM_REGIONS "CSR 0x00000000 0x10000 " +#endif + +#ifndef MEM_REGIONS_DETAILS +#define MEM_REGIONS_DETAILS "Region Origin End Size \nCSR 0x00000000 0x0000ffff 0x10000 " +#endif +#endif diff --git a/hardware/v2/ddr3/litedram_gen/generated_headers/sdram_phy.h b/hardware/v2/ddr3/litedram_gen/generated_headers/sdram_phy.h new file mode 100644 index 0000000..3261423 --- /dev/null +++ b/hardware/v2/ddr3/litedram_gen/generated_headers/sdram_phy.h @@ -0,0 +1,115 @@ +#ifndef __GENERATED_SDRAM_PHY_H +#define __GENERATED_SDRAM_PHY_H + +#include +#include + +#define DFII_CONTROL_SEL 0x01 +#define DFII_CONTROL_CKE 0x02 +#define DFII_CONTROL_ODT 0x04 +#define DFII_CONTROL_RESET_N 0x08 + +#define DFII_COMMAND_CS 0x01 +#define DFII_COMMAND_WE 0x02 +#define DFII_COMMAND_CAS 0x04 +#define DFII_COMMAND_RAS 0x08 +#define DFII_COMMAND_WRDATA 0x10 +#define DFII_COMMAND_RDDATA 0x20 + +#define SDRAM_PHY_ECP5DDRPHY +#define SDRAM_PHY_XDR 2 +#define SDRAM_PHY_DATABITS 16 +#define SDRAM_PHY_DFI_DATABITS 64 +#define SDRAM_PHY_PHASES 2 +#define SDRAM_PHY_CL 6 +#define SDRAM_PHY_CWL 5 +#define SDRAM_PHY_RDPHASE 0 +#define SDRAM_PHY_WRPHASE 1 +#define SDRAM_PHY_READ_LEVELING_CAPABLE +#define SDRAM_PHY_DQ_DQS_RATIO 8 +#define SDRAM_PHY_MODULES 2 +#define SDRAM_PHY_DELAYS 8 +#define SDRAM_PHY_BITSLIPS 4 +#define SDRAM_PHY_DDR3 +#define SDRAM_PHY_SUPPORTED_MEMORY 0x0000000020000000ULL + +void cdelay(int i); + +__attribute__((unused)) static inline void command_p0(int cmd) +{ + sdram_dfii_pi0_command_write(cmd); + sdram_dfii_pi0_command_issue_write(1); +} +__attribute__((unused)) static inline void command_p1(int cmd) +{ + sdram_dfii_pi1_command_write(cmd); + sdram_dfii_pi1_command_issue_write(1); +} + +#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE + +static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase) +{ + switch (phase) { + case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR; + case 1: return CSR_SDRAM_DFII_PI1_WRDATA_ADDR; + default: return 0; + } +} +static inline unsigned long sdram_dfii_pix_rddata_addr(int phase) +{ + switch (phase) { + case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR; + case 1: return CSR_SDRAM_DFII_PI1_RDDATA_ADDR; + default: return 0; + } +} + +#define DDRX_MR_WRLVL_ADDRESS 1 +#define DDRX_MR_WRLVL_RESET 6 +#define DDRX_MR_WRLVL_BIT 7 + +static inline void init_sequence(void) +{ + /* Release reset */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(50000); + + /* Bring CKE high */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(10000); + + /* Load Mode Register 2, CWL=5 */ + sdram_dfii_pi0_address_write(0x200); + sdram_dfii_pi0_baddress_write(2); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 3 */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(3); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 1 */ + sdram_dfii_pi0_address_write(0x6); + sdram_dfii_pi0_baddress_write(1); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 0, CL=6, BL=8 */ + sdram_dfii_pi0_address_write(0x320); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + + /* ZQ Calibration */ + sdram_dfii_pi0_address_write(0x400); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + +} + +#endif /* __GENERATED_SDRAM_PHY_H */ diff --git a/hardware/v2/ddr3/litedram_gen/generated_headers/soc.h b/hardware/v2/ddr3/litedram_gen/generated_headers/soc.h new file mode 100644 index 0000000..bcee4b3 --- /dev/null +++ b/hardware/v2/ddr3/litedram_gen/generated_headers/soc.h @@ -0,0 +1,55 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by LiteX (9ad3ecf74) on 2026-09-16 08:16:18 +//-------------------------------------------------------------------------------- +#ifndef __GENERATED_SOC_H +#define __GENERATED_SOC_H +#include +#define CONFIG_PLATFORM_NAME "platform" +#define CONFIG_CLOCK_FREQUENCY 75000000 +#define CONFIG_CPU_TYPE_NONE +#define CONFIG_CPU_VARIANT_STANDARD +#define CONFIG_CPU_FAMILY +#define CONFIG_CPU_NAME "None" +#define CONFIG_CPU_HUMAN_NAME "Unknown" +#define CONFIG_CSR_DATA_WIDTH 32 +#define CONFIG_CSR_ALIGNMENT 32 +#define CONFIG_CSR_ORDERING_BIG +#define CONFIG_BUS_STANDARD "wishbone" +#define CONFIG_BUS_DATA_WIDTH 32 +#define CONFIG_BUS_ADDRESS_WIDTH 32 +#define CONFIG_BUS_BURSTING 0 + +#ifndef __ASSEMBLER__ +static inline const char * config_platform_name_read(void) { + return "platform"; +} +static inline uint32_t config_clock_frequency_read(void) { + return 75000000; +} +static inline const char * config_cpu_name_read(void) { + return "None"; +} +static inline const char * config_cpu_human_name_read(void) { + return "Unknown"; +} +static inline uint32_t config_csr_data_width_read(void) { + return 32; +} +static inline uint32_t config_csr_alignment_read(void) { + return 32; +} +static inline const char * config_bus_standard_read(void) { + return "wishbone"; +} +static inline uint32_t config_bus_data_width_read(void) { + return 32; +} +static inline uint32_t config_bus_address_width_read(void) { + return 32; +} +static inline uint32_t config_bus_bursting_read(void) { + return 0; +} +#endif // !__ASSEMBLER__ + +#endif diff --git a/hardware/v2/ddr3/litedram_gen/litedram_core.lpf b/hardware/v2/ddr3/litedram_gen/litedram_core.lpf new file mode 100644 index 0000000..9776241 --- /dev/null +++ b/hardware/v2/ddr3/litedram_gen/litedram_core.lpf @@ -0,0 +1,470 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +LOCATE COMP "clk" SITE "X"; +LOCATE COMP "rst" SITE "X"; +LOCATE COMP "pll_locked" SITE "X"; +LOCATE COMP "ddram_a[0]" SITE "X"; +LOCATE COMP "ddram_a[1]" SITE "X"; +LOCATE COMP "ddram_a[2]" SITE "X"; +LOCATE COMP "ddram_a[3]" SITE "X"; +LOCATE COMP "ddram_a[4]" SITE "X"; +LOCATE COMP "ddram_a[5]" SITE "X"; +LOCATE COMP "ddram_a[6]" SITE "X"; +LOCATE COMP "ddram_a[7]" SITE "X"; +LOCATE COMP "ddram_a[8]" SITE "X"; +LOCATE COMP "ddram_a[9]" SITE "X"; +LOCATE COMP "ddram_a[10]" SITE "X"; +LOCATE COMP "ddram_a[11]" SITE "X"; +LOCATE COMP "ddram_a[12]" SITE "X"; +LOCATE COMP "ddram_a[13]" SITE "X"; +LOCATE COMP "ddram_a[14]" SITE "X"; +LOCATE COMP "ddram_ba[0]" SITE "X"; +LOCATE COMP "ddram_ba[1]" SITE "X"; +LOCATE COMP "ddram_ba[2]" SITE "X"; +LOCATE COMP "ddram_ras_n" SITE "X"; +LOCATE COMP "ddram_cas_n" SITE "X"; +LOCATE COMP "ddram_we_n" SITE "X"; +LOCATE COMP "ddram_cs_n" SITE "X"; +LOCATE COMP "ddram_dm[0]" SITE "X"; +LOCATE COMP "ddram_dm[1]" SITE "X"; +LOCATE COMP "ddram_dq[0]" SITE "X"; +LOCATE COMP "ddram_dq[1]" SITE "X"; +LOCATE COMP "ddram_dq[2]" SITE "X"; +LOCATE COMP "ddram_dq[3]" SITE "X"; +LOCATE COMP "ddram_dq[4]" SITE "X"; +LOCATE COMP "ddram_dq[5]" SITE "X"; +LOCATE COMP "ddram_dq[6]" SITE "X"; +LOCATE COMP "ddram_dq[7]" SITE "X"; +LOCATE COMP "ddram_dq[8]" SITE "X"; +LOCATE COMP "ddram_dq[9]" SITE "X"; +LOCATE COMP "ddram_dq[10]" SITE "X"; +LOCATE COMP "ddram_dq[11]" SITE "X"; +LOCATE COMP "ddram_dq[12]" SITE "X"; +LOCATE COMP "ddram_dq[13]" SITE "X"; +LOCATE COMP "ddram_dq[14]" SITE "X"; +LOCATE COMP "ddram_dq[15]" SITE "X"; +LOCATE COMP "ddram_dqs_p[0]" SITE "X"; +LOCATE COMP "ddram_dqs_p[1]" SITE "X"; +LOCATE COMP "ddram_dqs_n[0]" SITE "X"; +LOCATE COMP "ddram_dqs_n[1]" SITE "X"; +LOCATE COMP "ddram_clk_p" SITE "X"; +LOCATE COMP "ddram_clk_n" SITE "X"; +LOCATE COMP "ddram_cke" SITE "X"; +LOCATE COMP "ddram_odt" SITE "X"; +LOCATE COMP "ddram_reset_n" SITE "X"; +LOCATE COMP "init_done" SITE "X"; +LOCATE COMP "init_error" SITE "X"; +LOCATE COMP "wb_ctrl_adr[0]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[1]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[2]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[3]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[4]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[5]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[6]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[7]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[8]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[9]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[10]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[11]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[12]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[13]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[14]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[15]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[16]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[17]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[18]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[19]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[20]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[21]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[22]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[23]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[24]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[25]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[26]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[27]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[28]" SITE "X"; +LOCATE COMP "wb_ctrl_adr[29]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[0]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[1]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[2]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[3]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[4]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[5]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[6]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[7]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[8]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[9]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[10]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[11]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[12]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[13]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[14]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[15]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[16]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[17]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[18]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[19]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[20]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[21]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[22]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[23]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[24]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[25]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[26]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[27]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[28]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[29]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[30]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_w[31]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[0]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[1]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[2]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[3]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[4]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[5]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[6]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[7]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[8]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[9]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[10]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[11]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[12]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[13]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[14]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[15]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[16]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[17]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[18]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[19]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[20]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[21]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[22]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[23]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[24]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[25]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[26]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[27]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[28]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[29]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[30]" SITE "X"; +LOCATE COMP "wb_ctrl_dat_r[31]" SITE "X"; +LOCATE COMP "wb_ctrl_sel[0]" SITE "X"; +LOCATE COMP "wb_ctrl_sel[1]" SITE "X"; +LOCATE COMP "wb_ctrl_sel[2]" SITE "X"; +LOCATE COMP "wb_ctrl_sel[3]" SITE "X"; +LOCATE COMP "wb_ctrl_cyc" SITE "X"; +LOCATE COMP "wb_ctrl_stb" SITE "X"; +LOCATE COMP "wb_ctrl_ack" SITE "X"; +LOCATE COMP "wb_ctrl_we" SITE "X"; +LOCATE COMP "wb_ctrl_cti[0]" SITE "X"; +LOCATE COMP "wb_ctrl_cti[1]" SITE "X"; +LOCATE COMP "wb_ctrl_cti[2]" SITE "X"; +LOCATE COMP "wb_ctrl_bte[0]" SITE "X"; +LOCATE COMP "wb_ctrl_bte[1]" SITE "X"; +LOCATE COMP "wb_ctrl_err" SITE "X"; +LOCATE COMP "user_clk" SITE "X"; +LOCATE COMP "user_rst" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_valid" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_ready" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_we" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[0]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[1]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[2]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[3]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[4]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[5]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[6]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[7]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[8]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[9]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[10]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[11]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[12]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[13]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[14]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[15]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[16]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[17]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[18]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[19]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[20]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[21]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[22]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[23]" SITE "X"; +LOCATE COMP "user_port_native_0_cmd_addr[24]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_valid" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_ready" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_we[0]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_we[1]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_we[2]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_we[3]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_we[4]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_we[5]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_we[6]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_we[7]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_we[8]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_we[9]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_we[10]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_we[11]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_we[12]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_we[13]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_we[14]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_we[15]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[0]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[1]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[2]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[3]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[4]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[5]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[6]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[7]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[8]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[9]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[10]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[11]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[12]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[13]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[14]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[15]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[16]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[17]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[18]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[19]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[20]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[21]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[22]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[23]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[24]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[25]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[26]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[27]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[28]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[29]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[30]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[31]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[32]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[33]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[34]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[35]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[36]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[37]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[38]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[39]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[40]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[41]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[42]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[43]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[44]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[45]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[46]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[47]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[48]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[49]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[50]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[51]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[52]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[53]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[54]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[55]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[56]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[57]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[58]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[59]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[60]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[61]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[62]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[63]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[64]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[65]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[66]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[67]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[68]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[69]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[70]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[71]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[72]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[73]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[74]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[75]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[76]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[77]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[78]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[79]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[80]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[81]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[82]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[83]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[84]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[85]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[86]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[87]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[88]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[89]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[90]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[91]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[92]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[93]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[94]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[95]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[96]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[97]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[98]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[99]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[100]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[101]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[102]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[103]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[104]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[105]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[106]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[107]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[108]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[109]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[110]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[111]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[112]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[113]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[114]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[115]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[116]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[117]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[118]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[119]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[120]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[121]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[122]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[123]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[124]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[125]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[126]" SITE "X"; +LOCATE COMP "user_port_native_0_wdata_data[127]" SITE "X"; +LOCATE COMP "user_port_native_0_rdata_valid" SITE "X"; +LOCATE COMP "user_port_native_0_rdata_ready" SITE "X"; +LOCATE COMP "user_port_native_0_rdata_data[0]" SITE "X"; +LOCATE COMP "user_port_native_0_rdata_data[1]" SITE "X"; +LOCATE COMP "user_port_native_0_rdata_data[2]" SITE "X"; +LOCATE COMP "user_port_native_0_rdata_data[3]" SITE "X"; +LOCATE COMP "user_port_native_0_rdata_data[4]" SITE "X"; +LOCATE COMP "user_port_native_0_rdata_data[5]" SITE "X"; +LOCATE COMP "user_port_native_0_rdata_data[6]" SITE "X"; +LOCATE COMP "user_port_native_0_rdata_data[7]" SITE "X"; +LOCATE COMP "user_port_native_0_rdata_data[8]" SITE "X"; +LOCATE COMP "user_port_native_0_rdata_data[9]" SITE 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SITE "X"; +LOCATE COMP "user_port_native_0_rdata_data[127]" SITE "X"; \ No newline at end of file diff --git a/hardware/v2/ddr3/litedram_gen/litedram_core.v b/hardware/v2/ddr3/litedram_gen/litedram_core.v new file mode 100644 index 0000000..4e92ea9 --- /dev/null +++ b/hardware/v2/ddr3/litedram_gen/litedram_core.v @@ -0,0 +1,11400 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : litedram_core.v +// Top : LiteDRAMCore +// Device : LFE5U-85F-8BG381C +// Hierarchy : disabled +// LiteX sha1 : 9ad3ecf74 +// Date : 2026-09-16 08:16:18 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module litedram_core ( + input wire clk, + output wire [14:0] ddram_a, + output wire [2:0] ddram_ba, + output wire ddram_cas_n, + output wire ddram_cke, + input wire ddram_clk_n, + output wire ddram_clk_p, + output wire ddram_cs_n, + output wire [1:0] ddram_dm, + input wire [15:0] ddram_dq, + input wire [1:0] ddram_dqs_n, + input wire [1:0] ddram_dqs_p, + output wire ddram_odt, + output wire ddram_ras_n, + output wire ddram_reset_n, + output wire ddram_we_n, + output wire init_done, + output wire init_error, + output wire pll_locked, + input wire rst, + output wire user_clk, + input wire [24:0] user_port_native_0_cmd_addr, + output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_valid, + input wire user_port_native_0_cmd_we, + output wire [127:0] user_port_native_0_rdata_data, + input wire user_port_native_0_rdata_ready, + output wire user_port_native_0_rdata_valid, + input wire [127:0] user_port_native_0_wdata_data, + output wire user_port_native_0_wdata_ready, + input wire user_port_native_0_wdata_valid, + input wire [15:0] user_port_native_0_wdata_we, + output wire user_rst, + output wire wb_ctrl_ack, + input wire [29:0] wb_ctrl_adr, + input wire [1:0] wb_ctrl_bte, + input wire [2:0] wb_ctrl_cti, + input wire wb_ctrl_cyc, + output wire [31:0] wb_ctrl_dat_r, + input wire [31:0] wb_ctrl_dat_w, + output wire wb_ctrl_err, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_stb, + input wire wb_ctrl_we +); + + +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +LiteDRAMCore +├── bus (SoCBusHandler) +│ └── _interconnect (InterconnectShared) +│ ├── arbiter (Arbiter) +│ │ └── rr (RoundRobin) +│ ├── decoder (Decoder) +│ └── timeout (Timeout) +│ └── waittimer_0 (WaitTimer) [Gen] +├── csr (SoCCSRHandler) +├── irq (SoCIRQHandler) +├── cpu (CPUNone) +├── crg (LiteDRAMECP5DDRPHYCRG) +│ ├── pll (ECP5PLL) +│ │ └── [BB:EHXPLLL] +│ ├── [BB:CLKDIVF] +│ ├── [BB:ECLKBRIDGECS] +│ └── [BB:ECLKSYNCB] +├── ddrphy (ECP5DDRPHY) +│ ├── init (ECP5DDRPHYInit) +│ │ └── [BB:DDRDLLA] +│ ├── bitslip_0 (BitSlip) [Gen] +│ ├── bitslip_1 (BitSlip) [Gen] +│ ├── bitslip_2 (BitSlip) [Gen] +│ ├── bitslip_3 (BitSlip) [Gen] +│ ├── bitslip_4 (BitSlip) [Gen] +│ ├── bitslip_5 (BitSlip) [Gen] +│ ├── bitslip_6 (BitSlip) [Gen] +│ ├── bitslip_7 (BitSlip) [Gen] +│ ├── bitslip_8 (BitSlip) [Gen] +│ ├── bitslip_9 (BitSlip) [Gen] +│ ├── bitslip_10 (BitSlip) [Gen] +│ ├── bitslip_11 (BitSlip) [Gen] +│ ├── bitslip_12 (BitSlip) [Gen] +│ ├── bitslip_13 (BitSlip) [Gen] +│ ├── bitslip_14 (BitSlip) [Gen] +│ ├── bitslip_15 (BitSlip) [Gen] +│ ├── tappeddelayline_0 (TappedDelayLine) [Gen] +│ ├── tappeddelayline_1 (TappedDelayLine) [Gen] +│ ├── [BB:DELAYG] +│ ├── [BB:IDDRX2DQA] +│ ├── [BB:TSHX2DQA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:DELAYG] +│ ├── [BB:IDDRX2DQA] +│ ├── [BB:TSHX2DQA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:DELAYG] +│ ├── [BB:IDDRX2DQA] +│ ├── [BB:TSHX2DQA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:DELAYG] +│ ├── [BB:IDDRX2DQA] +│ ├── [BB:TSHX2DQA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:DELAYG] +│ ├── [BB:IDDRX2DQA] +│ ├── [BB:TSHX2DQA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:DELAYG] +│ ├── [BB:IDDRX2DQA] +│ ├── [BB:TSHX2DQA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:DELAYG] +│ ├── [BB:IDDRX2DQA] +│ ├── [BB:TSHX2DQA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:DELAYG] +│ ├── [BB:IDDRX2DQA] +│ ├── [BB:TSHX2DQA] +│ ├── [BB:DELAYG] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:IDDRX2DQA] +│ ├── [BB:DQSBUFM] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:TSHX2DQSA] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:ODDRX2F] +│ ├── [BB:DELAYG] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ ├── [BB:ODDRX2F] +│ ├── [BB:ODDRX2DQSB] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:IDDRX2DQA] +│ ├── [BB:TSHX2DQA] +│ ├── [BB:DELAYG] +│ ├── [BB:DELAYG] +│ ├── [BB:TSHX2DQA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:DELAYG] +│ ├── [BB:IDDRX2DQA] +│ ├── [BB:TSHX2DQA] +│ ├── [BB:DELAYG] +│ ├── [BB:IDDRX2DQA] +│ ├── [BB:TSHX2DQA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:DELAYG] +│ ├── [BB:IDDRX2DQA] +│ ├── [BB:TSHX2DQA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:DELAYG] +│ ├── [BB:IDDRX2DQA] +│ ├── [BB:TSHX2DQA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:DELAYG] +│ ├── [BB:IDDRX2DQA] +│ ├── [BB:TSHX2DQA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:IDDRX2DQA] +│ ├── [BB:TSHX2DQA] +│ ├── [BB:DQSBUFM] +│ ├── [BB:ODDRX2DQSB] +│ ├── [BB:TSHX2DQSA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:ODDRX2DQA] +│ ├── [BB:DELAYG] +│ ├── [BB:ODDRX2F] +│ └── [BB:DELAYG] +├── sdram (LiteDRAMCore) +│ ├── dfii (DFIInjector) +│ │ ├── pi0 (PhaseInjector) +│ │ └── pi1 (PhaseInjector) +│ ├── controller (LiteDRAMController) +│ │ ├── refresher (Refresher) +│ │ │ ├── timer (RefreshTimer) +│ │ │ ├── postponer (RefreshPostponer) +│ │ │ ├── sequencer (RefreshSequencer) +│ │ │ │ └── refreshexecuter_0 (RefreshExecuter) [Gen] +│ │ │ ├── zqcs_timer (RefreshTimer) +│ │ │ ├── zqs_executer (ZQCSExecuter) +│ │ │ └── fsm (FSM) +│ │ ├── bankmachine_0 (BankMachine) [Gen] +│ │ │ ├── syncfifo_0 (SyncFIFO) [Gen] +│ │ │ │ └── fifo (SyncFIFO) +│ │ │ ├── buffer_0 (Buffer) [Gen] +│ │ │ │ ├── pipe_valid (PipeValid) +│ │ │ │ └── pipeline (Pipeline) +│ │ │ ├── twtpcon (tXXDController) +│ │ │ ├── trccon (tXXDController) +│ │ │ ├── trascon (tXXDController) +│ │ │ └── fsm (FSM) +│ │ ├── bankmachine_1 (BankMachine) [Gen] +│ │ │ ├── syncfifo_0 (SyncFIFO) [Gen] +│ │ │ │ └── fifo (SyncFIFO) +│ │ │ ├── buffer_0 (Buffer) [Gen] +│ │ │ │ ├── pipe_valid (PipeValid) +│ │ │ │ └── pipeline (Pipeline) +│ │ │ ├── twtpcon (tXXDController) +│ │ │ ├── trccon (tXXDController) +│ │ │ ├── trascon (tXXDController) +│ │ │ └── fsm (FSM) +│ │ ├── bankmachine_2 (BankMachine) [Gen] +│ │ │ ├── syncfifo_0 (SyncFIFO) [Gen] +│ │ │ │ └── fifo (SyncFIFO) +│ │ │ ├── buffer_0 (Buffer) [Gen] +│ │ │ │ ├── pipe_valid (PipeValid) +│ │ │ │ └── pipeline (Pipeline) +│ │ │ ├── twtpcon (tXXDController) +│ │ │ ├── trccon (tXXDController) +│ │ │ ├── trascon (tXXDController) +│ │ │ └── fsm (FSM) +│ │ ├── bankmachine_3 (BankMachine) [Gen] +│ │ │ ├── syncfifo_0 (SyncFIFO) [Gen] +│ │ │ │ └── fifo (SyncFIFO) +│ │ │ ├── buffer_0 (Buffer) [Gen] +│ │ │ │ ├── pipe_valid (PipeValid) +│ │ │ │ └── pipeline (Pipeline) +│ │ │ ├── twtpcon (tXXDController) +│ │ │ ├── trccon (tXXDController) +│ │ │ ├── trascon (tXXDController) +│ │ │ └── fsm (FSM) +│ │ ├── bankmachine_4 (BankMachine) [Gen] +│ │ │ ├── syncfifo_0 (SyncFIFO) [Gen] +│ │ │ │ └── fifo (SyncFIFO) +│ │ │ ├── buffer_0 (Buffer) [Gen] +│ │ │ │ ├── pipe_valid (PipeValid) +│ │ │ │ └── pipeline (Pipeline) +│ │ │ ├── twtpcon (tXXDController) +│ │ │ ├── trccon (tXXDController) +│ │ │ ├── trascon (tXXDController) +│ │ │ └── fsm (FSM) +│ │ ├── bankmachine_5 (BankMachine) [Gen] +│ │ │ ├── syncfifo_0 (SyncFIFO) [Gen] +│ │ │ │ └── fifo (SyncFIFO) +│ │ │ ├── buffer_0 (Buffer) [Gen] +│ │ │ │ ├── pipe_valid (PipeValid) +│ │ │ │ └── pipeline (Pipeline) +│ │ │ ├── twtpcon (tXXDController) +│ │ │ ├── trccon (tXXDController) +│ │ │ ├── trascon (tXXDController) +│ │ │ └── fsm (FSM) +│ │ ├── bankmachine_6 (BankMachine) [Gen] +│ │ │ ├── syncfifo_0 (SyncFIFO) [Gen] +│ │ │ │ └── fifo (SyncFIFO) +│ │ │ ├── buffer_0 (Buffer) [Gen] +│ │ │ │ ├── pipe_valid (PipeValid) +│ │ │ │ └── pipeline (Pipeline) +│ │ │ ├── twtpcon (tXXDController) +│ │ │ ├── trccon (tXXDController) +│ │ │ ├── trascon (tXXDController) +│ │ │ └── fsm (FSM) +│ │ ├── bankmachine_7 (BankMachine) [Gen] +│ │ │ ├── syncfifo_0 (SyncFIFO) [Gen] +│ │ │ │ └── fifo (SyncFIFO) +│ │ │ ├── buffer_0 (Buffer) [Gen] +│ │ │ │ ├── pipe_valid (PipeValid) +│ │ │ │ └── pipeline (Pipeline) +│ │ │ ├── twtpcon (tXXDController) +│ │ │ ├── trccon (tXXDController) +│ │ │ ├── trascon (tXXDController) +│ │ │ └── fsm (FSM) +│ │ └── multiplexer (Multiplexer) +│ │ ├── choose_cmd (_CommandChooser) +│ │ │ └── roundrobin_0 (RoundRobin) [Gen] +│ │ ├── choose_req (_CommandChooser) +│ │ │ └── roundrobin_0 (RoundRobin) [Gen] +│ │ ├── _steerer_0 (_Steerer) [Gen] +│ │ ├── trrdcon (tXXDController) +│ │ ├── tfawcon (tFAWController) +│ │ ├── tccdcon (tXXDController) +│ │ ├── twtrcon (tXXDController) +│ │ └── fsm (FSM) +│ └── crossbar (LiteDRAMCrossbar) +│ ├── roundrobin_0 (RoundRobin) [Gen] +│ ├── roundrobin_1 (RoundRobin) [Gen] +│ ├── roundrobin_2 (RoundRobin) [Gen] +│ ├── roundrobin_3 (RoundRobin) [Gen] +│ ├── roundrobin_4 (RoundRobin) [Gen] +│ ├── roundrobin_5 (RoundRobin) [Gen] +│ ├── roundrobin_6 (RoundRobin) [Gen] +│ └── roundrobin_7 (RoundRobin) [Gen] +├── ddrctrl (LiteDRAMCoreControl) +├── csr_bridge (Wishbone2CSR) +│ └── fsm (FSM) +├── csr_bankarray (CSRBankArray) +│ ├── csrbank_0 (CSRBank) [Gen] +│ │ ├── csrstorage_0 (CSRStorage) [Gen] +│ │ └── csrstorage_1 (CSRStorage) [Gen] +│ ├── csrbank_1 (CSRBank) [Gen] +│ │ ├── csrstorage_0 (CSRStorage) [Gen] +│ │ └── csrstatus_0 (CSRStatus) [Gen] +│ └── csrbank_2 (CSRBank) [Gen] +│ ├── csrstorage_0 (CSRStorage) [Gen] +│ ├── csrstorage_1 (CSRStorage) [Gen] +│ ├── csrstorage_2 (CSRStorage) [Gen] +│ ├── csrstorage_3 (CSRStorage) [Gen] +│ ├── csrstorage_4 (CSRStorage) [Gen] +│ ├── csrstatus_0 (CSRStatus) [Gen] +│ ├── csrstorage_5 (CSRStorage) [Gen] +│ ├── csrstorage_6 (CSRStorage) [Gen] +│ ├── csrstorage_7 (CSRStorage) [Gen] +│ ├── csrstorage_8 (CSRStorage) [Gen] +│ └── csrstatus_1 (CSRStatus) [Gen] +├── csr_interconnect (InterconnectShared) +├── [BB:FD1S3BX] +├── [BB:FD1S3BX] +├── [BB:FD1S3BX] +├── [BB:FD1S3BX] +├── [BB:FD1S3BX] +├── [BB:FD1S3BX] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:TRELLIS_IO] +├── [BB:FD1S3BX] +└── [BB:FD1S3BX] +Legend: + [Gen]: Auto-generated instance name. + [BB:NAME]: Blackbox instance (verilog Instance). + +*/ + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire [13:0] adr; +reg [2:0] bankmachine0_next_state = 3'd0; +reg [2:0] bankmachine0_state = 3'd0; +reg [2:0] bankmachine1_next_state = 3'd0; +reg [2:0] bankmachine1_state = 3'd0; +reg [2:0] bankmachine2_next_state = 3'd0; +reg [2:0] bankmachine2_state = 3'd0; +reg [2:0] bankmachine3_next_state = 3'd0; +reg [2:0] bankmachine3_state = 3'd0; +reg [2:0] bankmachine4_next_state = 3'd0; +reg [2:0] bankmachine4_state = 3'd0; +reg [2:0] bankmachine5_next_state = 3'd0; +reg [2:0] bankmachine5_state = 3'd0; +reg [2:0] bankmachine6_next_state = 3'd0; +reg [2:0] bankmachine6_state = 3'd0; +reg [2:0] bankmachine7_next_state = 3'd0; +reg [2:0] bankmachine7_state = 3'd0; +reg [31:0] cases_self = 32'd0; +reg [19:0] count = 20'd1000000; +wire crg_clkin_signal; +wire crg_clkout0; +wire crg_clkout1; +wire crg_locked; +reg [15:0] crg_por_count = 16'hffff; +wire crg_por_done; +wire crg_reset0; +wire crg_reset1; +reg crg_rst = 1'd0; +reg crg_stdby = 1'd0; +wire crg_stop; +wire crg_sys2x_clk_ecsout; +reg csr_data_width = 1'd0; +wire csrbank0_init_done_r; +reg csrbank0_init_done_re = 1'd0; +wire csrbank0_init_done_w; +reg csrbank0_init_done_we = 1'd0; +wire csrbank0_init_error_r; +reg csrbank0_init_error_re = 1'd0; +wire csrbank0_init_error_w; +reg csrbank0_init_error_we = 1'd0; +wire csrbank0_sel; +wire [1:0] csrbank1_burstdet_seen_r; +reg csrbank1_burstdet_seen_re = 1'd0; +wire [1:0] csrbank1_burstdet_seen_w; +reg csrbank1_burstdet_seen_we = 1'd0; +wire [1:0] csrbank1_dly_sel_r; +reg csrbank1_dly_sel_re = 1'd0; +wire [1:0] csrbank1_dly_sel_w; +reg csrbank1_dly_sel_we = 1'd0; +wire csrbank1_sel; +wire [3:0] csrbank2_dfii_control_r; +reg csrbank2_dfii_control_re = 1'd0; +wire [3:0] csrbank2_dfii_control_w; +reg csrbank2_dfii_control_we = 1'd0; +wire [14:0] csrbank2_dfii_pi0_address_r; +reg csrbank2_dfii_pi0_address_re = 1'd0; +wire [14:0] csrbank2_dfii_pi0_address_w; +reg csrbank2_dfii_pi0_address_we = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress_r; +reg csrbank2_dfii_pi0_baddress_re = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress_w; +reg csrbank2_dfii_pi0_baddress_we = 1'd0; +wire [7:0] csrbank2_dfii_pi0_command_r; +reg csrbank2_dfii_pi0_command_re = 1'd0; +wire [7:0] csrbank2_dfii_pi0_command_w; +reg csrbank2_dfii_pi0_command_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata0_r; +reg csrbank2_dfii_pi0_rddata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata0_w; +reg csrbank2_dfii_pi0_rddata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata1_r; +reg csrbank2_dfii_pi0_rddata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata1_w; +reg csrbank2_dfii_pi0_rddata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_r; +reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_w; +reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata1_r; +reg csrbank2_dfii_pi0_wrdata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata1_w; +reg csrbank2_dfii_pi0_wrdata1_we = 1'd0; +wire [14:0] csrbank2_dfii_pi1_address_r; +reg csrbank2_dfii_pi1_address_re = 1'd0; +wire [14:0] csrbank2_dfii_pi1_address_w; +reg csrbank2_dfii_pi1_address_we = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress_r; +reg csrbank2_dfii_pi1_baddress_re = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress_w; +reg csrbank2_dfii_pi1_baddress_we = 1'd0; +wire [7:0] csrbank2_dfii_pi1_command_r; +reg csrbank2_dfii_pi1_command_re = 1'd0; +wire [7:0] csrbank2_dfii_pi1_command_w; +reg csrbank2_dfii_pi1_command_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata0_r; +reg csrbank2_dfii_pi1_rddata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata0_w; +reg csrbank2_dfii_pi1_rddata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata1_r; +reg csrbank2_dfii_pi1_rddata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata1_w; +reg csrbank2_dfii_pi1_rddata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_r; +reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_w; +reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata1_r; +reg csrbank2_dfii_pi1_wrdata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata1_w; +reg csrbank2_dfii_pi1_wrdata1_we = 1'd0; +wire csrbank2_sel; +wire [31:0] dat_r; +wire [31:0] dat_w; +wire [3:0] ddrphy_bitslip0_i; +reg [3:0] ddrphy_bitslip0_o = 4'd0; +reg [7:0] ddrphy_bitslip0_r = 8'd0; +reg [1:0] ddrphy_bitslip0_value = 2'd0; +wire [3:0] ddrphy_bitslip10_i; +reg [3:0] ddrphy_bitslip10_o = 4'd0; +reg [7:0] ddrphy_bitslip10_r = 8'd0; +reg [1:0] ddrphy_bitslip10_value = 2'd0; +wire [3:0] ddrphy_bitslip11_i; +reg [3:0] ddrphy_bitslip11_o = 4'd0; +reg [7:0] ddrphy_bitslip11_r = 8'd0; +reg [1:0] ddrphy_bitslip11_value = 2'd0; +wire [3:0] ddrphy_bitslip12_i; +reg [3:0] ddrphy_bitslip12_o = 4'd0; +reg [7:0] ddrphy_bitslip12_r = 8'd0; +reg [1:0] ddrphy_bitslip12_value = 2'd0; +wire [3:0] ddrphy_bitslip13_i; +reg [3:0] ddrphy_bitslip13_o = 4'd0; +reg [7:0] ddrphy_bitslip13_r = 8'd0; +reg [1:0] ddrphy_bitslip13_value = 2'd0; +wire [3:0] ddrphy_bitslip14_i; +reg [3:0] ddrphy_bitslip14_o = 4'd0; +reg [7:0] ddrphy_bitslip14_r = 8'd0; +reg [1:0] ddrphy_bitslip14_value = 2'd0; +wire [3:0] ddrphy_bitslip15_i; +reg [3:0] ddrphy_bitslip15_o = 4'd0; +reg [7:0] ddrphy_bitslip15_r = 8'd0; +reg [1:0] ddrphy_bitslip15_value = 2'd0; +wire [3:0] ddrphy_bitslip1_i; +reg [3:0] ddrphy_bitslip1_o = 4'd0; +reg [7:0] ddrphy_bitslip1_r = 8'd0; +reg [1:0] ddrphy_bitslip1_value = 2'd0; +wire [3:0] ddrphy_bitslip2_i; +reg [3:0] ddrphy_bitslip2_o = 4'd0; +reg [7:0] ddrphy_bitslip2_r = 8'd0; +reg [1:0] ddrphy_bitslip2_value = 2'd0; +wire [3:0] ddrphy_bitslip3_i; +reg [3:0] ddrphy_bitslip3_o = 4'd0; +reg [7:0] ddrphy_bitslip3_r = 8'd0; +reg [1:0] ddrphy_bitslip3_value = 2'd0; +wire [3:0] ddrphy_bitslip4_i; +reg [3:0] ddrphy_bitslip4_o = 4'd0; +reg [7:0] ddrphy_bitslip4_r = 8'd0; +reg [1:0] ddrphy_bitslip4_value = 2'd0; +wire [3:0] ddrphy_bitslip5_i; +reg [3:0] ddrphy_bitslip5_o = 4'd0; +reg [7:0] ddrphy_bitslip5_r = 8'd0; +reg [1:0] ddrphy_bitslip5_value = 2'd0; +wire [3:0] ddrphy_bitslip6_i; +reg [3:0] ddrphy_bitslip6_o = 4'd0; +reg [7:0] ddrphy_bitslip6_r = 8'd0; +reg [1:0] ddrphy_bitslip6_value = 2'd0; +wire [3:0] ddrphy_bitslip7_i; +reg [3:0] ddrphy_bitslip7_o = 4'd0; +reg [7:0] ddrphy_bitslip7_r = 8'd0; +reg [1:0] ddrphy_bitslip7_value = 2'd0; +wire [3:0] ddrphy_bitslip8_i; +reg [3:0] ddrphy_bitslip8_o = 4'd0; +reg [7:0] ddrphy_bitslip8_r = 8'd0; +reg [1:0] ddrphy_bitslip8_value = 2'd0; +wire [3:0] ddrphy_bitslip9_i; +reg [3:0] ddrphy_bitslip9_o = 4'd0; +reg [7:0] ddrphy_bitslip9_r = 8'd0; +reg [1:0] ddrphy_bitslip9_value = 2'd0; +wire ddrphy_bl8_chunk; +wire ddrphy_burstdet0; +wire ddrphy_burstdet1; +wire ddrphy_burstdet_clr_r; +reg ddrphy_burstdet_clr_re = 1'd0; +reg ddrphy_burstdet_clr_w = 1'd0; +reg ddrphy_burstdet_clr_we = 1'd0; +reg ddrphy_burstdet_d0 = 1'd0; +reg ddrphy_burstdet_d1 = 1'd0; +wire ddrphy_burstdet_seen_rd_stb; +reg [1:0] ddrphy_burstdet_seen_status = 2'd0; +reg ddrphy_burstdet_seen_wr_stb = 1'd0; +wire [1:0] ddrphy_datavalid; +wire ddrphy_delay0; +wire ddrphy_delay1; +wire ddrphy_dfi_p0_act_n; +wire [14:0] ddrphy_dfi_p0_address; +wire [2:0] ddrphy_dfi_p0_bank; +wire ddrphy_dfi_p0_cas_n; +wire ddrphy_dfi_p0_cke; +wire ddrphy_dfi_p0_cs_n; +wire ddrphy_dfi_p0_odt; +wire ddrphy_dfi_p0_ras_n; +reg [63:0] ddrphy_dfi_p0_rddata = 64'd0; +wire ddrphy_dfi_p0_rddata_en; +wire ddrphy_dfi_p0_rddata_valid; +wire ddrphy_dfi_p0_reset_n; +wire ddrphy_dfi_p0_we_n; +wire [63:0] ddrphy_dfi_p0_wrdata; +wire ddrphy_dfi_p0_wrdata_en; +wire [7:0] ddrphy_dfi_p0_wrdata_mask; +wire ddrphy_dfi_p1_act_n; +wire [14:0] ddrphy_dfi_p1_address; +wire [2:0] ddrphy_dfi_p1_bank; +wire ddrphy_dfi_p1_cas_n; +wire ddrphy_dfi_p1_cke; +wire ddrphy_dfi_p1_cs_n; +wire ddrphy_dfi_p1_odt; +wire ddrphy_dfi_p1_ras_n; +reg [63:0] ddrphy_dfi_p1_rddata = 64'd0; +wire ddrphy_dfi_p1_rddata_en; +wire ddrphy_dfi_p1_rddata_valid; +wire ddrphy_dfi_p1_reset_n; +wire ddrphy_dfi_p1_we_n; +wire [63:0] ddrphy_dfi_p1_wrdata; +wire ddrphy_dfi_p1_wrdata_en; +wire [7:0] ddrphy_dfi_p1_wrdata_mask; +reg [1:0] ddrphy_dly_sel_storage = 2'd0; +reg ddrphy_dly_sel_wr_stb = 1'd0; +reg [7:0] ddrphy_dm_o_data0 = 8'd0; +reg [7:0] ddrphy_dm_o_data1 = 8'd0; +reg [7:0] ddrphy_dm_o_data_d0 = 8'd0; +reg [7:0] ddrphy_dm_o_data_d1 = 8'd0; +reg [3:0] ddrphy_dm_o_data_muxed0 = 4'd0; +reg [3:0] ddrphy_dm_o_data_muxed1 = 4'd0; +wire ddrphy_dq_i0; +wire ddrphy_dq_i1; +wire ddrphy_dq_i10; +wire ddrphy_dq_i11; +wire ddrphy_dq_i12; +wire ddrphy_dq_i13; +wire ddrphy_dq_i14; +wire ddrphy_dq_i15; +wire ddrphy_dq_i2; +wire ddrphy_dq_i3; +wire ddrphy_dq_i4; +wire ddrphy_dq_i5; +wire ddrphy_dq_i6; +wire ddrphy_dq_i7; +wire ddrphy_dq_i8; +wire ddrphy_dq_i9; +reg [3:0] ddrphy_dq_i_bitslip_o_d0 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d1 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d10 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d11 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d12 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d13 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d14 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d15 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d2 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d3 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d4 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d5 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d6 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d7 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d8 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d9 = 4'd0; +wire [7:0] ddrphy_dq_i_data0; +wire [7:0] ddrphy_dq_i_data1; +wire [7:0] ddrphy_dq_i_data10; +wire [7:0] ddrphy_dq_i_data11; +wire [7:0] ddrphy_dq_i_data12; +wire [7:0] ddrphy_dq_i_data13; +wire [7:0] ddrphy_dq_i_data14; +wire [7:0] ddrphy_dq_i_data15; +wire [7:0] ddrphy_dq_i_data2; +wire [7:0] ddrphy_dq_i_data3; +wire [7:0] ddrphy_dq_i_data4; +wire [7:0] ddrphy_dq_i_data5; +wire [7:0] ddrphy_dq_i_data6; +wire [7:0] ddrphy_dq_i_data7; +wire [7:0] ddrphy_dq_i_data8; +wire [7:0] ddrphy_dq_i_data9; +wire ddrphy_dq_i_delayed0; +wire ddrphy_dq_i_delayed1; +wire ddrphy_dq_i_delayed10; +wire ddrphy_dq_i_delayed11; +wire ddrphy_dq_i_delayed12; +wire ddrphy_dq_i_delayed13; +wire ddrphy_dq_i_delayed14; +wire ddrphy_dq_i_delayed15; +wire ddrphy_dq_i_delayed2; +wire ddrphy_dq_i_delayed3; +wire ddrphy_dq_i_delayed4; +wire ddrphy_dq_i_delayed5; +wire ddrphy_dq_i_delayed6; +wire ddrphy_dq_i_delayed7; +wire ddrphy_dq_i_delayed8; +wire ddrphy_dq_i_delayed9; +wire ddrphy_dq_o0; +wire ddrphy_dq_o1; +wire ddrphy_dq_o10; +wire ddrphy_dq_o11; +wire ddrphy_dq_o12; +wire ddrphy_dq_o13; +wire ddrphy_dq_o14; +wire ddrphy_dq_o15; +wire ddrphy_dq_o2; +wire ddrphy_dq_o3; +wire ddrphy_dq_o4; +wire ddrphy_dq_o5; +wire ddrphy_dq_o6; +wire ddrphy_dq_o7; +wire ddrphy_dq_o8; +wire ddrphy_dq_o9; +reg [7:0] ddrphy_dq_o_data0 = 8'd0; +reg [7:0] ddrphy_dq_o_data1 = 8'd0; +reg [7:0] ddrphy_dq_o_data10 = 8'd0; +reg [7:0] ddrphy_dq_o_data11 = 8'd0; +reg [7:0] ddrphy_dq_o_data12 = 8'd0; +reg [7:0] ddrphy_dq_o_data13 = 8'd0; +reg [7:0] ddrphy_dq_o_data14 = 8'd0; +reg [7:0] ddrphy_dq_o_data15 = 8'd0; +reg [7:0] ddrphy_dq_o_data2 = 8'd0; +reg [7:0] ddrphy_dq_o_data3 = 8'd0; +reg [7:0] ddrphy_dq_o_data4 = 8'd0; +reg [7:0] ddrphy_dq_o_data5 = 8'd0; +reg [7:0] ddrphy_dq_o_data6 = 8'd0; +reg [7:0] ddrphy_dq_o_data7 = 8'd0; +reg [7:0] ddrphy_dq_o_data8 = 8'd0; +reg [7:0] ddrphy_dq_o_data9 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d0 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d1 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d10 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d11 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d12 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d13 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d14 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d15 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d2 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d3 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d4 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d5 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d6 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d7 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d8 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d9 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed0 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed1 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed10 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed11 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed12 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed13 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed14 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed15 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed2 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed3 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed4 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed5 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed6 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed7 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed8 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed9 = 4'd0; +wire ddrphy_dq_oe; +wire ddrphy_dq_oe_n0; +wire ddrphy_dq_oe_n1; +wire ddrphy_dq_oe_n10; +wire ddrphy_dq_oe_n11; +wire ddrphy_dq_oe_n12; +wire ddrphy_dq_oe_n13; +wire ddrphy_dq_oe_n14; +wire ddrphy_dq_oe_n15; +wire ddrphy_dq_oe_n2; +wire ddrphy_dq_oe_n3; +wire ddrphy_dq_oe_n4; +wire ddrphy_dq_oe_n5; +wire ddrphy_dq_oe_n6; +wire ddrphy_dq_oe_n7; +wire ddrphy_dq_oe_n8; +wire ddrphy_dq_oe_n9; +wire ddrphy_dqs0; +wire ddrphy_dqs1; +wire ddrphy_dqs_i0; +wire ddrphy_dqs_i1; +wire ddrphy_dqs_oe; +wire ddrphy_dqs_oe_n0; +wire ddrphy_dqs_oe_n1; +wire ddrphy_dqs_postamble; +wire ddrphy_dqs_preamble; +wire ddrphy_dqs_re; +wire ddrphy_dqsr900; +wire ddrphy_dqsr901; +wire ddrphy_dqsw0; +wire ddrphy_dqsw1; +wire ddrphy_dqsw2700; +wire ddrphy_dqsw2701; +reg ddrphy_freeze = 1'd0; +wire ddrphy_lock0; +wire ddrphy_lock1; +reg ddrphy_lock_d = 1'd0; +wire ddrphy_new_lock; +wire ddrphy_pad_oddrx2f0; +wire ddrphy_pad_oddrx2f1; +wire ddrphy_pad_oddrx2f10; +wire ddrphy_pad_oddrx2f11; +wire ddrphy_pad_oddrx2f12; +wire ddrphy_pad_oddrx2f13; +wire ddrphy_pad_oddrx2f14; +wire ddrphy_pad_oddrx2f15; +wire ddrphy_pad_oddrx2f16; +wire ddrphy_pad_oddrx2f17; +wire ddrphy_pad_oddrx2f18; +wire ddrphy_pad_oddrx2f19; +wire ddrphy_pad_oddrx2f2; +wire ddrphy_pad_oddrx2f20; +wire ddrphy_pad_oddrx2f21; +wire ddrphy_pad_oddrx2f22; +wire ddrphy_pad_oddrx2f23; +wire ddrphy_pad_oddrx2f24; +wire ddrphy_pad_oddrx2f25; +wire ddrphy_pad_oddrx2f3; +wire ddrphy_pad_oddrx2f4; +wire ddrphy_pad_oddrx2f5; +wire ddrphy_pad_oddrx2f6; +wire ddrphy_pad_oddrx2f7; +wire ddrphy_pad_oddrx2f8; +wire ddrphy_pad_oddrx2f9; +wire ddrphy_pause0; +reg ddrphy_pause1 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline10 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline11 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline12 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline8 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline9 = 1'd0; +reg [2:0] ddrphy_rdly0 = 3'd0; +reg [2:0] ddrphy_rdly1 = 3'd0; +wire ddrphy_rdly_dq_bitslip_r; +reg ddrphy_rdly_dq_bitslip_re = 1'd0; +wire ddrphy_rdly_dq_bitslip_rst_r; +reg ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +reg ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg ddrphy_rdly_dq_bitslip_w = 1'd0; +reg ddrphy_rdly_dq_bitslip_we = 1'd0; +wire ddrphy_rdly_dq_inc_r; +reg ddrphy_rdly_dq_inc_re = 1'd0; +reg ddrphy_rdly_dq_inc_w = 1'd0; +reg ddrphy_rdly_dq_inc_we = 1'd0; +wire ddrphy_rdly_dq_rst_r; +reg ddrphy_rdly_dq_rst_re = 1'd0; +reg ddrphy_rdly_dq_rst_w = 1'd0; +reg ddrphy_rdly_dq_rst_we = 1'd0; +wire [2:0] ddrphy_rdpntr0; +wire [2:0] ddrphy_rdpntr1; +wire ddrphy_reset0; +reg ddrphy_reset1 = 1'd0; +wire ddrphy_stop0; +reg ddrphy_stop1 = 1'd0; +reg [6:0] ddrphy_trigger = 7'd0; +reg ddrphy_update = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline3 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline4 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline5 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline6 = 1'd0; +wire [2:0] ddrphy_wrpntr0; +wire [2:0] ddrphy_wrpntr1; +wire done; +wire ecp5pll; +wire ecp5pll_locked; +reg error = 1'd0; +wire grant; +wire init_clk; +reg init_done_storage = 1'd0; +reg init_done_wr_stb = 1'd0; +reg init_error_storage = 1'd0; +reg init_error_wr_stb = 1'd0; +wire init_rst; +reg interface0_ack = 1'd0; +wire [29:0] interface0_adr; +wire [13:0] interface0_bank_bus_adr; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_re; +wire interface0_bank_bus_we; +wire [1:0] interface0_bte; +wire [2:0] interface0_cti; +wire interface0_cyc; +reg [31:0] interface0_dat_r = 32'd0; +wire [31:0] interface0_dat_w; +reg interface0_err = 1'd0; +wire [3:0] interface0_sel; +wire interface0_stb; +wire interface0_we; +reg [13:0] interface1_adr = 14'd0; +reg [13:0] interface1_adr_next_value2 = 14'd0; +reg interface1_adr_next_value_ce2 = 1'd0; +wire [13:0] interface1_bank_bus_adr; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_re; +wire interface1_bank_bus_we; +wire [31:0] interface1_dat_r; +reg [31:0] interface1_dat_w = 32'd0; +reg [31:0] interface1_dat_w_next_value0 = 32'd0; +reg interface1_dat_w_next_value_ce0 = 1'd0; +reg interface1_re = 1'd0; +reg interface1_re_next_value3 = 1'd0; +reg interface1_re_next_value_ce3 = 1'd0; +reg interface1_we = 1'd0; +reg interface1_we_next_value4 = 1'd0; +reg interface1_we_next_value_ce4 = 1'd0; +wire [13:0] interface2_bank_bus_adr; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_re; +wire interface2_bank_bus_we; +wire latticeecp5asyncresetsynchronizerimpl0_expr; +wire latticeecp5asyncresetsynchronizerimpl0_rst1; +wire latticeecp5asyncresetsynchronizerimpl1_rst1; +wire latticeecp5asyncresetsynchronizerimpl2_rst1; +wire latticeecp5asyncresetsynchronizerimpl3_rst1; +reg litedramcore_bankmachine0_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; +reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine0_cmd_ready = 1'd0; +reg litedramcore_bankmachine0_cmd_valid = 1'd0; +reg [2:0] litedramcore_bankmachine0_consume = 3'd0; +wire litedramcore_bankmachine0_do_read; +wire litedramcore_bankmachine0_fifo_in_first; +wire litedramcore_bankmachine0_fifo_in_last; +wire [21:0] litedramcore_bankmachine0_fifo_in_payload_addr; +wire litedramcore_bankmachine0_fifo_in_payload_we; +wire litedramcore_bankmachine0_fifo_out_first; +wire litedramcore_bankmachine0_fifo_out_last; +wire [21:0] litedramcore_bankmachine0_fifo_out_payload_addr; +wire litedramcore_bankmachine0_fifo_out_payload_we; +reg [3:0] litedramcore_bankmachine0_level = 4'd0; +wire litedramcore_bankmachine0_pipe_valid_sink_first; +wire litedramcore_bankmachine0_pipe_valid_sink_last; +wire [21:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr; +wire litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine0_pipe_valid_sink_ready; +wire litedramcore_bankmachine0_pipe_valid_sink_valid; +reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; +reg [21:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine0_pipe_valid_source_ready; +reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +reg [2:0] litedramcore_bankmachine0_produce = 3'd0; +wire [2:0] litedramcore_bankmachine0_rdport_adr; +wire [24:0] litedramcore_bankmachine0_rdport_dat_r; +reg litedramcore_bankmachine0_refresh_gnt = 1'd0; +wire litedramcore_bankmachine0_refresh_req; +reg litedramcore_bankmachine0_replace = 1'd0; +wire [21:0] litedramcore_bankmachine0_req_addr; +wire litedramcore_bankmachine0_req_lock; +reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine0_req_ready; +wire litedramcore_bankmachine0_req_valid; +reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine0_req_we; +reg [14:0] litedramcore_bankmachine0_row = 15'd0; +reg litedramcore_bankmachine0_row_close = 1'd0; +reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine0_row_hit; +reg litedramcore_bankmachine0_row_open = 1'd0; +reg litedramcore_bankmachine0_row_opened = 1'd0; +reg litedramcore_bankmachine0_sink_first = 1'd0; +reg litedramcore_bankmachine0_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine0_sink_payload_addr; +wire litedramcore_bankmachine0_sink_payload_we; +wire litedramcore_bankmachine0_sink_ready; +wire litedramcore_bankmachine0_sink_sink_first; +wire litedramcore_bankmachine0_sink_sink_last; +wire [21:0] litedramcore_bankmachine0_sink_sink_payload_addr; +wire litedramcore_bankmachine0_sink_sink_payload_we; +wire litedramcore_bankmachine0_sink_sink_ready; +wire litedramcore_bankmachine0_sink_sink_valid; +wire litedramcore_bankmachine0_sink_valid; +wire litedramcore_bankmachine0_source_first; +wire litedramcore_bankmachine0_source_last; +wire [21:0] litedramcore_bankmachine0_source_payload_addr; +wire litedramcore_bankmachine0_source_payload_we; +wire litedramcore_bankmachine0_source_ready; +wire litedramcore_bankmachine0_source_source_first; +wire litedramcore_bankmachine0_source_source_last; +wire [21:0] litedramcore_bankmachine0_source_source_payload_addr; +wire litedramcore_bankmachine0_source_source_payload_we; +wire litedramcore_bankmachine0_source_source_ready; +wire litedramcore_bankmachine0_source_source_valid; +wire litedramcore_bankmachine0_source_valid; +wire [24:0] litedramcore_bankmachine0_syncfifo0_din; +wire [24:0] litedramcore_bankmachine0_syncfifo0_dout; +wire litedramcore_bankmachine0_syncfifo0_re; +wire litedramcore_bankmachine0_syncfifo0_readable; +wire litedramcore_bankmachine0_syncfifo0_we; +wire litedramcore_bankmachine0_syncfifo0_writable; +reg [1:0] litedramcore_bankmachine0_trascon_count = 2'd0; +reg litedramcore_bankmachine0_trascon_ready = 1'd0; +wire litedramcore_bankmachine0_trascon_valid; +reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; +reg litedramcore_bankmachine0_trccon_ready = 1'd0; +wire litedramcore_bankmachine0_trccon_valid; +reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; +reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine0_twtpcon_valid; +reg [2:0] litedramcore_bankmachine0_wrport_adr = 3'd0; +wire [24:0] litedramcore_bankmachine0_wrport_dat_r; +wire [24:0] litedramcore_bankmachine0_wrport_dat_w; +wire litedramcore_bankmachine0_wrport_we; +reg litedramcore_bankmachine1_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; +reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine1_cmd_ready = 1'd0; +reg litedramcore_bankmachine1_cmd_valid = 1'd0; +reg [2:0] litedramcore_bankmachine1_consume = 3'd0; +wire litedramcore_bankmachine1_do_read; +wire litedramcore_bankmachine1_fifo_in_first; +wire litedramcore_bankmachine1_fifo_in_last; +wire [21:0] litedramcore_bankmachine1_fifo_in_payload_addr; +wire litedramcore_bankmachine1_fifo_in_payload_we; +wire litedramcore_bankmachine1_fifo_out_first; +wire litedramcore_bankmachine1_fifo_out_last; +wire [21:0] litedramcore_bankmachine1_fifo_out_payload_addr; +wire litedramcore_bankmachine1_fifo_out_payload_we; +reg [3:0] litedramcore_bankmachine1_level = 4'd0; +wire litedramcore_bankmachine1_pipe_valid_sink_first; +wire litedramcore_bankmachine1_pipe_valid_sink_last; +wire [21:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr; +wire litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine1_pipe_valid_sink_ready; +wire litedramcore_bankmachine1_pipe_valid_sink_valid; +reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; +reg [21:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine1_pipe_valid_source_ready; +reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +reg [2:0] litedramcore_bankmachine1_produce = 3'd0; +wire [2:0] litedramcore_bankmachine1_rdport_adr; +wire [24:0] litedramcore_bankmachine1_rdport_dat_r; +reg litedramcore_bankmachine1_refresh_gnt = 1'd0; +wire litedramcore_bankmachine1_refresh_req; +reg litedramcore_bankmachine1_replace = 1'd0; +wire [21:0] litedramcore_bankmachine1_req_addr; +wire litedramcore_bankmachine1_req_lock; +reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine1_req_ready; +wire litedramcore_bankmachine1_req_valid; +reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine1_req_we; +reg [14:0] litedramcore_bankmachine1_row = 15'd0; +reg litedramcore_bankmachine1_row_close = 1'd0; +reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine1_row_hit; +reg litedramcore_bankmachine1_row_open = 1'd0; +reg litedramcore_bankmachine1_row_opened = 1'd0; +reg litedramcore_bankmachine1_sink_first = 1'd0; +reg litedramcore_bankmachine1_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine1_sink_payload_addr; +wire litedramcore_bankmachine1_sink_payload_we; +wire litedramcore_bankmachine1_sink_ready; +wire litedramcore_bankmachine1_sink_sink_first; +wire litedramcore_bankmachine1_sink_sink_last; +wire [21:0] litedramcore_bankmachine1_sink_sink_payload_addr; +wire litedramcore_bankmachine1_sink_sink_payload_we; +wire litedramcore_bankmachine1_sink_sink_ready; +wire litedramcore_bankmachine1_sink_sink_valid; +wire litedramcore_bankmachine1_sink_valid; +wire litedramcore_bankmachine1_source_first; +wire litedramcore_bankmachine1_source_last; +wire [21:0] litedramcore_bankmachine1_source_payload_addr; +wire litedramcore_bankmachine1_source_payload_we; +wire litedramcore_bankmachine1_source_ready; +wire litedramcore_bankmachine1_source_source_first; +wire litedramcore_bankmachine1_source_source_last; +wire [21:0] litedramcore_bankmachine1_source_source_payload_addr; +wire litedramcore_bankmachine1_source_source_payload_we; +wire litedramcore_bankmachine1_source_source_ready; +wire litedramcore_bankmachine1_source_source_valid; +wire litedramcore_bankmachine1_source_valid; +wire [24:0] litedramcore_bankmachine1_syncfifo1_din; +wire [24:0] litedramcore_bankmachine1_syncfifo1_dout; +wire litedramcore_bankmachine1_syncfifo1_re; +wire litedramcore_bankmachine1_syncfifo1_readable; +wire litedramcore_bankmachine1_syncfifo1_we; +wire litedramcore_bankmachine1_syncfifo1_writable; +reg [1:0] litedramcore_bankmachine1_trascon_count = 2'd0; +reg litedramcore_bankmachine1_trascon_ready = 1'd0; +wire litedramcore_bankmachine1_trascon_valid; +reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; +reg litedramcore_bankmachine1_trccon_ready = 1'd0; +wire litedramcore_bankmachine1_trccon_valid; +reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; +reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine1_twtpcon_valid; +reg [2:0] litedramcore_bankmachine1_wrport_adr = 3'd0; +wire [24:0] litedramcore_bankmachine1_wrport_dat_r; +wire [24:0] litedramcore_bankmachine1_wrport_dat_w; +wire litedramcore_bankmachine1_wrport_we; +reg litedramcore_bankmachine2_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; +reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine2_cmd_ready = 1'd0; +reg litedramcore_bankmachine2_cmd_valid = 1'd0; +reg [2:0] litedramcore_bankmachine2_consume = 3'd0; +wire litedramcore_bankmachine2_do_read; +wire litedramcore_bankmachine2_fifo_in_first; +wire litedramcore_bankmachine2_fifo_in_last; +wire [21:0] litedramcore_bankmachine2_fifo_in_payload_addr; +wire litedramcore_bankmachine2_fifo_in_payload_we; +wire litedramcore_bankmachine2_fifo_out_first; +wire litedramcore_bankmachine2_fifo_out_last; +wire [21:0] litedramcore_bankmachine2_fifo_out_payload_addr; +wire litedramcore_bankmachine2_fifo_out_payload_we; +reg [3:0] litedramcore_bankmachine2_level = 4'd0; +wire litedramcore_bankmachine2_pipe_valid_sink_first; +wire litedramcore_bankmachine2_pipe_valid_sink_last; +wire [21:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr; +wire litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine2_pipe_valid_sink_ready; +wire litedramcore_bankmachine2_pipe_valid_sink_valid; +reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; +reg [21:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine2_pipe_valid_source_ready; +reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +reg [2:0] litedramcore_bankmachine2_produce = 3'd0; +wire [2:0] litedramcore_bankmachine2_rdport_adr; +wire [24:0] litedramcore_bankmachine2_rdport_dat_r; +reg litedramcore_bankmachine2_refresh_gnt = 1'd0; +wire litedramcore_bankmachine2_refresh_req; +reg litedramcore_bankmachine2_replace = 1'd0; +wire [21:0] litedramcore_bankmachine2_req_addr; +wire litedramcore_bankmachine2_req_lock; +reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine2_req_ready; +wire litedramcore_bankmachine2_req_valid; +reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine2_req_we; +reg [14:0] litedramcore_bankmachine2_row = 15'd0; +reg litedramcore_bankmachine2_row_close = 1'd0; +reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine2_row_hit; +reg litedramcore_bankmachine2_row_open = 1'd0; +reg litedramcore_bankmachine2_row_opened = 1'd0; +reg litedramcore_bankmachine2_sink_first = 1'd0; +reg litedramcore_bankmachine2_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine2_sink_payload_addr; +wire litedramcore_bankmachine2_sink_payload_we; +wire litedramcore_bankmachine2_sink_ready; +wire litedramcore_bankmachine2_sink_sink_first; +wire litedramcore_bankmachine2_sink_sink_last; +wire [21:0] litedramcore_bankmachine2_sink_sink_payload_addr; +wire litedramcore_bankmachine2_sink_sink_payload_we; +wire litedramcore_bankmachine2_sink_sink_ready; +wire litedramcore_bankmachine2_sink_sink_valid; +wire litedramcore_bankmachine2_sink_valid; +wire litedramcore_bankmachine2_source_first; +wire litedramcore_bankmachine2_source_last; +wire [21:0] litedramcore_bankmachine2_source_payload_addr; +wire litedramcore_bankmachine2_source_payload_we; +wire litedramcore_bankmachine2_source_ready; +wire litedramcore_bankmachine2_source_source_first; +wire litedramcore_bankmachine2_source_source_last; +wire [21:0] litedramcore_bankmachine2_source_source_payload_addr; +wire litedramcore_bankmachine2_source_source_payload_we; +wire litedramcore_bankmachine2_source_source_ready; +wire litedramcore_bankmachine2_source_source_valid; +wire litedramcore_bankmachine2_source_valid; +wire [24:0] litedramcore_bankmachine2_syncfifo2_din; +wire [24:0] litedramcore_bankmachine2_syncfifo2_dout; +wire litedramcore_bankmachine2_syncfifo2_re; +wire litedramcore_bankmachine2_syncfifo2_readable; +wire litedramcore_bankmachine2_syncfifo2_we; +wire litedramcore_bankmachine2_syncfifo2_writable; +reg [1:0] litedramcore_bankmachine2_trascon_count = 2'd0; +reg litedramcore_bankmachine2_trascon_ready = 1'd0; +wire litedramcore_bankmachine2_trascon_valid; +reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; +reg litedramcore_bankmachine2_trccon_ready = 1'd0; +wire litedramcore_bankmachine2_trccon_valid; +reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; +reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine2_twtpcon_valid; +reg [2:0] litedramcore_bankmachine2_wrport_adr = 3'd0; +wire [24:0] litedramcore_bankmachine2_wrport_dat_r; +wire [24:0] litedramcore_bankmachine2_wrport_dat_w; +wire litedramcore_bankmachine2_wrport_we; +reg litedramcore_bankmachine3_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; +reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine3_cmd_ready = 1'd0; +reg litedramcore_bankmachine3_cmd_valid = 1'd0; +reg [2:0] litedramcore_bankmachine3_consume = 3'd0; +wire litedramcore_bankmachine3_do_read; +wire litedramcore_bankmachine3_fifo_in_first; +wire litedramcore_bankmachine3_fifo_in_last; +wire [21:0] litedramcore_bankmachine3_fifo_in_payload_addr; +wire litedramcore_bankmachine3_fifo_in_payload_we; +wire litedramcore_bankmachine3_fifo_out_first; +wire litedramcore_bankmachine3_fifo_out_last; +wire [21:0] litedramcore_bankmachine3_fifo_out_payload_addr; +wire litedramcore_bankmachine3_fifo_out_payload_we; +reg [3:0] litedramcore_bankmachine3_level = 4'd0; +wire litedramcore_bankmachine3_pipe_valid_sink_first; +wire litedramcore_bankmachine3_pipe_valid_sink_last; +wire [21:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr; +wire litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine3_pipe_valid_sink_ready; +wire litedramcore_bankmachine3_pipe_valid_sink_valid; +reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; +reg [21:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine3_pipe_valid_source_ready; +reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +reg [2:0] litedramcore_bankmachine3_produce = 3'd0; +wire [2:0] litedramcore_bankmachine3_rdport_adr; +wire [24:0] litedramcore_bankmachine3_rdport_dat_r; +reg litedramcore_bankmachine3_refresh_gnt = 1'd0; +wire litedramcore_bankmachine3_refresh_req; +reg litedramcore_bankmachine3_replace = 1'd0; +wire [21:0] litedramcore_bankmachine3_req_addr; +wire litedramcore_bankmachine3_req_lock; +reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine3_req_ready; +wire litedramcore_bankmachine3_req_valid; +reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine3_req_we; +reg [14:0] litedramcore_bankmachine3_row = 15'd0; +reg litedramcore_bankmachine3_row_close = 1'd0; +reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine3_row_hit; +reg litedramcore_bankmachine3_row_open = 1'd0; +reg litedramcore_bankmachine3_row_opened = 1'd0; +reg litedramcore_bankmachine3_sink_first = 1'd0; +reg litedramcore_bankmachine3_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine3_sink_payload_addr; +wire litedramcore_bankmachine3_sink_payload_we; +wire litedramcore_bankmachine3_sink_ready; +wire litedramcore_bankmachine3_sink_sink_first; +wire litedramcore_bankmachine3_sink_sink_last; +wire [21:0] litedramcore_bankmachine3_sink_sink_payload_addr; +wire litedramcore_bankmachine3_sink_sink_payload_we; +wire litedramcore_bankmachine3_sink_sink_ready; +wire litedramcore_bankmachine3_sink_sink_valid; +wire litedramcore_bankmachine3_sink_valid; +wire litedramcore_bankmachine3_source_first; +wire litedramcore_bankmachine3_source_last; +wire [21:0] litedramcore_bankmachine3_source_payload_addr; +wire litedramcore_bankmachine3_source_payload_we; +wire litedramcore_bankmachine3_source_ready; +wire litedramcore_bankmachine3_source_source_first; +wire litedramcore_bankmachine3_source_source_last; +wire [21:0] litedramcore_bankmachine3_source_source_payload_addr; +wire litedramcore_bankmachine3_source_source_payload_we; +wire litedramcore_bankmachine3_source_source_ready; +wire litedramcore_bankmachine3_source_source_valid; +wire litedramcore_bankmachine3_source_valid; +wire [24:0] litedramcore_bankmachine3_syncfifo3_din; +wire [24:0] litedramcore_bankmachine3_syncfifo3_dout; +wire litedramcore_bankmachine3_syncfifo3_re; +wire litedramcore_bankmachine3_syncfifo3_readable; +wire litedramcore_bankmachine3_syncfifo3_we; +wire litedramcore_bankmachine3_syncfifo3_writable; +reg [1:0] litedramcore_bankmachine3_trascon_count = 2'd0; +reg litedramcore_bankmachine3_trascon_ready = 1'd0; +wire litedramcore_bankmachine3_trascon_valid; +reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; +reg litedramcore_bankmachine3_trccon_ready = 1'd0; +wire litedramcore_bankmachine3_trccon_valid; +reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; +reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine3_twtpcon_valid; +reg [2:0] litedramcore_bankmachine3_wrport_adr = 3'd0; +wire [24:0] litedramcore_bankmachine3_wrport_dat_r; +wire [24:0] litedramcore_bankmachine3_wrport_dat_w; +wire litedramcore_bankmachine3_wrport_we; +reg litedramcore_bankmachine4_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; +reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine4_cmd_ready = 1'd0; +reg litedramcore_bankmachine4_cmd_valid = 1'd0; +reg [2:0] litedramcore_bankmachine4_consume = 3'd0; +wire litedramcore_bankmachine4_do_read; +wire litedramcore_bankmachine4_fifo_in_first; +wire litedramcore_bankmachine4_fifo_in_last; +wire [21:0] litedramcore_bankmachine4_fifo_in_payload_addr; +wire litedramcore_bankmachine4_fifo_in_payload_we; +wire litedramcore_bankmachine4_fifo_out_first; +wire litedramcore_bankmachine4_fifo_out_last; +wire [21:0] litedramcore_bankmachine4_fifo_out_payload_addr; +wire litedramcore_bankmachine4_fifo_out_payload_we; +reg [3:0] litedramcore_bankmachine4_level = 4'd0; +wire litedramcore_bankmachine4_pipe_valid_sink_first; +wire litedramcore_bankmachine4_pipe_valid_sink_last; +wire [21:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr; +wire litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine4_pipe_valid_sink_ready; +wire litedramcore_bankmachine4_pipe_valid_sink_valid; +reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; +reg [21:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine4_pipe_valid_source_ready; +reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +reg [2:0] litedramcore_bankmachine4_produce = 3'd0; +wire [2:0] litedramcore_bankmachine4_rdport_adr; +wire [24:0] litedramcore_bankmachine4_rdport_dat_r; +reg litedramcore_bankmachine4_refresh_gnt = 1'd0; +wire litedramcore_bankmachine4_refresh_req; +reg litedramcore_bankmachine4_replace = 1'd0; +wire [21:0] litedramcore_bankmachine4_req_addr; +wire litedramcore_bankmachine4_req_lock; +reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine4_req_ready; +wire litedramcore_bankmachine4_req_valid; +reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine4_req_we; +reg [14:0] litedramcore_bankmachine4_row = 15'd0; +reg litedramcore_bankmachine4_row_close = 1'd0; +reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine4_row_hit; +reg litedramcore_bankmachine4_row_open = 1'd0; +reg litedramcore_bankmachine4_row_opened = 1'd0; +reg litedramcore_bankmachine4_sink_first = 1'd0; +reg litedramcore_bankmachine4_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine4_sink_payload_addr; +wire litedramcore_bankmachine4_sink_payload_we; +wire litedramcore_bankmachine4_sink_ready; +wire litedramcore_bankmachine4_sink_sink_first; +wire litedramcore_bankmachine4_sink_sink_last; +wire [21:0] litedramcore_bankmachine4_sink_sink_payload_addr; +wire litedramcore_bankmachine4_sink_sink_payload_we; +wire litedramcore_bankmachine4_sink_sink_ready; +wire litedramcore_bankmachine4_sink_sink_valid; +wire litedramcore_bankmachine4_sink_valid; +wire litedramcore_bankmachine4_source_first; +wire litedramcore_bankmachine4_source_last; +wire [21:0] litedramcore_bankmachine4_source_payload_addr; +wire litedramcore_bankmachine4_source_payload_we; +wire litedramcore_bankmachine4_source_ready; +wire litedramcore_bankmachine4_source_source_first; +wire litedramcore_bankmachine4_source_source_last; +wire [21:0] litedramcore_bankmachine4_source_source_payload_addr; +wire litedramcore_bankmachine4_source_source_payload_we; +wire litedramcore_bankmachine4_source_source_ready; +wire litedramcore_bankmachine4_source_source_valid; +wire litedramcore_bankmachine4_source_valid; +wire [24:0] litedramcore_bankmachine4_syncfifo4_din; +wire [24:0] litedramcore_bankmachine4_syncfifo4_dout; +wire litedramcore_bankmachine4_syncfifo4_re; +wire litedramcore_bankmachine4_syncfifo4_readable; +wire litedramcore_bankmachine4_syncfifo4_we; +wire litedramcore_bankmachine4_syncfifo4_writable; +reg [1:0] litedramcore_bankmachine4_trascon_count = 2'd0; +reg litedramcore_bankmachine4_trascon_ready = 1'd0; +wire litedramcore_bankmachine4_trascon_valid; +reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; +reg litedramcore_bankmachine4_trccon_ready = 1'd0; +wire litedramcore_bankmachine4_trccon_valid; +reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; +reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine4_twtpcon_valid; +reg [2:0] litedramcore_bankmachine4_wrport_adr = 3'd0; +wire [24:0] litedramcore_bankmachine4_wrport_dat_r; +wire [24:0] litedramcore_bankmachine4_wrport_dat_w; +wire litedramcore_bankmachine4_wrport_we; +reg litedramcore_bankmachine5_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; +reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine5_cmd_ready = 1'd0; +reg litedramcore_bankmachine5_cmd_valid = 1'd0; +reg [2:0] litedramcore_bankmachine5_consume = 3'd0; +wire litedramcore_bankmachine5_do_read; +wire litedramcore_bankmachine5_fifo_in_first; +wire litedramcore_bankmachine5_fifo_in_last; +wire [21:0] litedramcore_bankmachine5_fifo_in_payload_addr; +wire litedramcore_bankmachine5_fifo_in_payload_we; +wire litedramcore_bankmachine5_fifo_out_first; +wire litedramcore_bankmachine5_fifo_out_last; +wire [21:0] litedramcore_bankmachine5_fifo_out_payload_addr; +wire litedramcore_bankmachine5_fifo_out_payload_we; +reg [3:0] litedramcore_bankmachine5_level = 4'd0; +wire litedramcore_bankmachine5_pipe_valid_sink_first; +wire litedramcore_bankmachine5_pipe_valid_sink_last; +wire [21:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr; +wire litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine5_pipe_valid_sink_ready; +wire litedramcore_bankmachine5_pipe_valid_sink_valid; +reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; +reg [21:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine5_pipe_valid_source_ready; +reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +reg [2:0] litedramcore_bankmachine5_produce = 3'd0; +wire [2:0] litedramcore_bankmachine5_rdport_adr; +wire [24:0] litedramcore_bankmachine5_rdport_dat_r; +reg litedramcore_bankmachine5_refresh_gnt = 1'd0; +wire litedramcore_bankmachine5_refresh_req; +reg litedramcore_bankmachine5_replace = 1'd0; +wire [21:0] litedramcore_bankmachine5_req_addr; +wire litedramcore_bankmachine5_req_lock; +reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine5_req_ready; +wire litedramcore_bankmachine5_req_valid; +reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine5_req_we; +reg [14:0] litedramcore_bankmachine5_row = 15'd0; +reg litedramcore_bankmachine5_row_close = 1'd0; +reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine5_row_hit; +reg litedramcore_bankmachine5_row_open = 1'd0; +reg litedramcore_bankmachine5_row_opened = 1'd0; +reg litedramcore_bankmachine5_sink_first = 1'd0; +reg litedramcore_bankmachine5_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine5_sink_payload_addr; +wire litedramcore_bankmachine5_sink_payload_we; +wire litedramcore_bankmachine5_sink_ready; +wire litedramcore_bankmachine5_sink_sink_first; +wire litedramcore_bankmachine5_sink_sink_last; +wire [21:0] litedramcore_bankmachine5_sink_sink_payload_addr; +wire litedramcore_bankmachine5_sink_sink_payload_we; +wire litedramcore_bankmachine5_sink_sink_ready; +wire litedramcore_bankmachine5_sink_sink_valid; +wire litedramcore_bankmachine5_sink_valid; +wire litedramcore_bankmachine5_source_first; +wire litedramcore_bankmachine5_source_last; +wire [21:0] litedramcore_bankmachine5_source_payload_addr; +wire litedramcore_bankmachine5_source_payload_we; +wire litedramcore_bankmachine5_source_ready; +wire litedramcore_bankmachine5_source_source_first; +wire litedramcore_bankmachine5_source_source_last; +wire [21:0] litedramcore_bankmachine5_source_source_payload_addr; +wire litedramcore_bankmachine5_source_source_payload_we; +wire litedramcore_bankmachine5_source_source_ready; +wire litedramcore_bankmachine5_source_source_valid; +wire litedramcore_bankmachine5_source_valid; +wire [24:0] litedramcore_bankmachine5_syncfifo5_din; +wire [24:0] litedramcore_bankmachine5_syncfifo5_dout; +wire litedramcore_bankmachine5_syncfifo5_re; +wire litedramcore_bankmachine5_syncfifo5_readable; +wire litedramcore_bankmachine5_syncfifo5_we; +wire litedramcore_bankmachine5_syncfifo5_writable; +reg [1:0] litedramcore_bankmachine5_trascon_count = 2'd0; +reg litedramcore_bankmachine5_trascon_ready = 1'd0; +wire litedramcore_bankmachine5_trascon_valid; +reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; +reg litedramcore_bankmachine5_trccon_ready = 1'd0; +wire litedramcore_bankmachine5_trccon_valid; +reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; +reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine5_twtpcon_valid; +reg [2:0] litedramcore_bankmachine5_wrport_adr = 3'd0; +wire [24:0] litedramcore_bankmachine5_wrport_dat_r; +wire [24:0] litedramcore_bankmachine5_wrport_dat_w; +wire litedramcore_bankmachine5_wrport_we; +reg litedramcore_bankmachine6_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; +reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine6_cmd_ready = 1'd0; +reg litedramcore_bankmachine6_cmd_valid = 1'd0; +reg [2:0] litedramcore_bankmachine6_consume = 3'd0; +wire litedramcore_bankmachine6_do_read; +wire litedramcore_bankmachine6_fifo_in_first; +wire litedramcore_bankmachine6_fifo_in_last; +wire [21:0] litedramcore_bankmachine6_fifo_in_payload_addr; +wire litedramcore_bankmachine6_fifo_in_payload_we; +wire litedramcore_bankmachine6_fifo_out_first; +wire litedramcore_bankmachine6_fifo_out_last; +wire [21:0] litedramcore_bankmachine6_fifo_out_payload_addr; +wire litedramcore_bankmachine6_fifo_out_payload_we; +reg [3:0] litedramcore_bankmachine6_level = 4'd0; +wire litedramcore_bankmachine6_pipe_valid_sink_first; +wire litedramcore_bankmachine6_pipe_valid_sink_last; +wire [21:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr; +wire litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine6_pipe_valid_sink_ready; +wire litedramcore_bankmachine6_pipe_valid_sink_valid; +reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; +reg [21:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine6_pipe_valid_source_ready; +reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +reg [2:0] litedramcore_bankmachine6_produce = 3'd0; +wire [2:0] litedramcore_bankmachine6_rdport_adr; +wire [24:0] litedramcore_bankmachine6_rdport_dat_r; +reg litedramcore_bankmachine6_refresh_gnt = 1'd0; +wire litedramcore_bankmachine6_refresh_req; +reg litedramcore_bankmachine6_replace = 1'd0; +wire [21:0] litedramcore_bankmachine6_req_addr; +wire litedramcore_bankmachine6_req_lock; +reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine6_req_ready; +wire litedramcore_bankmachine6_req_valid; +reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine6_req_we; +reg [14:0] litedramcore_bankmachine6_row = 15'd0; +reg litedramcore_bankmachine6_row_close = 1'd0; +reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine6_row_hit; +reg litedramcore_bankmachine6_row_open = 1'd0; +reg litedramcore_bankmachine6_row_opened = 1'd0; +reg litedramcore_bankmachine6_sink_first = 1'd0; +reg litedramcore_bankmachine6_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine6_sink_payload_addr; +wire litedramcore_bankmachine6_sink_payload_we; +wire litedramcore_bankmachine6_sink_ready; +wire litedramcore_bankmachine6_sink_sink_first; +wire litedramcore_bankmachine6_sink_sink_last; +wire [21:0] litedramcore_bankmachine6_sink_sink_payload_addr; +wire litedramcore_bankmachine6_sink_sink_payload_we; +wire litedramcore_bankmachine6_sink_sink_ready; +wire litedramcore_bankmachine6_sink_sink_valid; +wire litedramcore_bankmachine6_sink_valid; +wire litedramcore_bankmachine6_source_first; +wire litedramcore_bankmachine6_source_last; +wire [21:0] litedramcore_bankmachine6_source_payload_addr; +wire litedramcore_bankmachine6_source_payload_we; +wire litedramcore_bankmachine6_source_ready; +wire litedramcore_bankmachine6_source_source_first; +wire litedramcore_bankmachine6_source_source_last; +wire [21:0] litedramcore_bankmachine6_source_source_payload_addr; +wire litedramcore_bankmachine6_source_source_payload_we; +wire litedramcore_bankmachine6_source_source_ready; +wire litedramcore_bankmachine6_source_source_valid; +wire litedramcore_bankmachine6_source_valid; +wire [24:0] litedramcore_bankmachine6_syncfifo6_din; +wire [24:0] litedramcore_bankmachine6_syncfifo6_dout; +wire litedramcore_bankmachine6_syncfifo6_re; +wire litedramcore_bankmachine6_syncfifo6_readable; +wire litedramcore_bankmachine6_syncfifo6_we; +wire litedramcore_bankmachine6_syncfifo6_writable; +reg [1:0] litedramcore_bankmachine6_trascon_count = 2'd0; +reg litedramcore_bankmachine6_trascon_ready = 1'd0; +wire litedramcore_bankmachine6_trascon_valid; +reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; +reg litedramcore_bankmachine6_trccon_ready = 1'd0; +wire litedramcore_bankmachine6_trccon_valid; +reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; +reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine6_twtpcon_valid; +reg [2:0] litedramcore_bankmachine6_wrport_adr = 3'd0; +wire [24:0] litedramcore_bankmachine6_wrport_dat_r; +wire [24:0] litedramcore_bankmachine6_wrport_dat_w; +wire litedramcore_bankmachine6_wrport_we; +reg litedramcore_bankmachine7_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; +reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine7_cmd_ready = 1'd0; +reg litedramcore_bankmachine7_cmd_valid = 1'd0; +reg [2:0] litedramcore_bankmachine7_consume = 3'd0; +wire litedramcore_bankmachine7_do_read; +wire litedramcore_bankmachine7_fifo_in_first; +wire litedramcore_bankmachine7_fifo_in_last; +wire [21:0] litedramcore_bankmachine7_fifo_in_payload_addr; +wire litedramcore_bankmachine7_fifo_in_payload_we; +wire litedramcore_bankmachine7_fifo_out_first; +wire litedramcore_bankmachine7_fifo_out_last; +wire [21:0] litedramcore_bankmachine7_fifo_out_payload_addr; +wire litedramcore_bankmachine7_fifo_out_payload_we; +reg [3:0] litedramcore_bankmachine7_level = 4'd0; +wire litedramcore_bankmachine7_pipe_valid_sink_first; +wire litedramcore_bankmachine7_pipe_valid_sink_last; +wire [21:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr; +wire litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine7_pipe_valid_sink_ready; +wire litedramcore_bankmachine7_pipe_valid_sink_valid; +reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; +reg [21:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine7_pipe_valid_source_ready; +reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +reg [2:0] litedramcore_bankmachine7_produce = 3'd0; +wire [2:0] litedramcore_bankmachine7_rdport_adr; +wire [24:0] litedramcore_bankmachine7_rdport_dat_r; +reg litedramcore_bankmachine7_refresh_gnt = 1'd0; +wire litedramcore_bankmachine7_refresh_req; +reg litedramcore_bankmachine7_replace = 1'd0; +wire [21:0] litedramcore_bankmachine7_req_addr; +wire litedramcore_bankmachine7_req_lock; +reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine7_req_ready; +wire litedramcore_bankmachine7_req_valid; +reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine7_req_we; +reg [14:0] litedramcore_bankmachine7_row = 15'd0; +reg litedramcore_bankmachine7_row_close = 1'd0; +reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine7_row_hit; +reg litedramcore_bankmachine7_row_open = 1'd0; +reg litedramcore_bankmachine7_row_opened = 1'd0; +reg litedramcore_bankmachine7_sink_first = 1'd0; +reg litedramcore_bankmachine7_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine7_sink_payload_addr; +wire litedramcore_bankmachine7_sink_payload_we; +wire litedramcore_bankmachine7_sink_ready; +wire litedramcore_bankmachine7_sink_sink_first; +wire litedramcore_bankmachine7_sink_sink_last; +wire [21:0] litedramcore_bankmachine7_sink_sink_payload_addr; +wire litedramcore_bankmachine7_sink_sink_payload_we; +wire litedramcore_bankmachine7_sink_sink_ready; +wire litedramcore_bankmachine7_sink_sink_valid; +wire litedramcore_bankmachine7_sink_valid; +wire litedramcore_bankmachine7_source_first; +wire litedramcore_bankmachine7_source_last; +wire [21:0] litedramcore_bankmachine7_source_payload_addr; +wire litedramcore_bankmachine7_source_payload_we; +wire litedramcore_bankmachine7_source_ready; +wire litedramcore_bankmachine7_source_source_first; +wire litedramcore_bankmachine7_source_source_last; +wire [21:0] litedramcore_bankmachine7_source_source_payload_addr; +wire litedramcore_bankmachine7_source_source_payload_we; +wire litedramcore_bankmachine7_source_source_ready; +wire litedramcore_bankmachine7_source_source_valid; +wire litedramcore_bankmachine7_source_valid; +wire [24:0] litedramcore_bankmachine7_syncfifo7_din; +wire [24:0] litedramcore_bankmachine7_syncfifo7_dout; +wire litedramcore_bankmachine7_syncfifo7_re; +wire litedramcore_bankmachine7_syncfifo7_readable; +wire litedramcore_bankmachine7_syncfifo7_we; +wire litedramcore_bankmachine7_syncfifo7_writable; +reg [1:0] litedramcore_bankmachine7_trascon_count = 2'd0; +reg litedramcore_bankmachine7_trascon_ready = 1'd0; +wire litedramcore_bankmachine7_trascon_valid; +reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; +reg litedramcore_bankmachine7_trccon_ready = 1'd0; +wire litedramcore_bankmachine7_trccon_valid; +reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; +reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine7_twtpcon_valid; +reg [2:0] litedramcore_bankmachine7_wrport_adr = 3'd0; +wire [24:0] litedramcore_bankmachine7_wrport_dat_r; +wire [24:0] litedramcore_bankmachine7_wrport_dat_w; +wire litedramcore_bankmachine7_wrport_we; +wire litedramcore_cas_allowed; +wire litedramcore_choose_cmd_ce; +wire [14:0] litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; +reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +wire litedramcore_choose_cmd_cmd_payload_is_cmd; +wire litedramcore_choose_cmd_cmd_payload_is_read; +wire litedramcore_choose_cmd_cmd_payload_is_write; +reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; +reg litedramcore_choose_cmd_cmd_ready = 1'd0; +wire litedramcore_choose_cmd_cmd_valid; +reg [2:0] litedramcore_choose_cmd_grant = 3'd0; +wire [7:0] litedramcore_choose_cmd_request; +reg [7:0] litedramcore_choose_cmd_valids = 8'd0; +reg litedramcore_choose_cmd_want_activates = 1'd0; +reg litedramcore_choose_cmd_want_cmds = 1'd0; +reg litedramcore_choose_cmd_want_reads = 1'd0; +reg litedramcore_choose_cmd_want_writes = 1'd0; +wire litedramcore_choose_req_ce; +wire [14:0] litedramcore_choose_req_cmd_payload_a; +wire [2:0] litedramcore_choose_req_cmd_payload_ba; +reg litedramcore_choose_req_cmd_payload_cas = 1'd0; +wire litedramcore_choose_req_cmd_payload_is_cmd; +wire litedramcore_choose_req_cmd_payload_is_read; +wire litedramcore_choose_req_cmd_payload_is_write; +reg litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg litedramcore_choose_req_cmd_payload_we = 1'd0; +reg litedramcore_choose_req_cmd_ready = 1'd0; +wire litedramcore_choose_req_cmd_valid; +reg [2:0] litedramcore_choose_req_grant = 3'd0; +wire [7:0] litedramcore_choose_req_request; +reg [7:0] litedramcore_choose_req_valids = 8'd0; +reg litedramcore_choose_req_want_activates = 1'd0; +reg litedramcore_choose_req_want_cmds = 1'd0; +reg litedramcore_choose_req_want_reads = 1'd0; +reg litedramcore_choose_req_want_writes = 1'd0; +wire litedramcore_cke; +reg litedramcore_cmd_last = 1'd0; +reg [14:0] litedramcore_cmd_payload_a = 15'd0; +reg [2:0] litedramcore_cmd_payload_ba = 3'd0; +reg litedramcore_cmd_payload_cas = 1'd0; +reg litedramcore_cmd_payload_is_read = 1'd0; +reg litedramcore_cmd_payload_is_write = 1'd0; +reg litedramcore_cmd_payload_ras = 1'd0; +reg litedramcore_cmd_payload_we = 1'd0; +reg litedramcore_cmd_ready = 1'd0; +reg litedramcore_cmd_valid = 1'd0; +reg litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [14:0] litedramcore_csr_dfi_p0_address; +wire [2:0] litedramcore_csr_dfi_p0_bank; +reg litedramcore_csr_dfi_p0_cas_n = 1'd1; +wire litedramcore_csr_dfi_p0_cke; +reg litedramcore_csr_dfi_p0_cs_n = 1'd1; +wire litedramcore_csr_dfi_p0_odt; +reg litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0; +wire litedramcore_csr_dfi_p0_rddata_en; +reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire litedramcore_csr_dfi_p0_reset_n; +reg litedramcore_csr_dfi_p0_we_n = 1'd1; +wire [63:0] litedramcore_csr_dfi_p0_wrdata; +wire litedramcore_csr_dfi_p0_wrdata_en; +wire [7:0] litedramcore_csr_dfi_p0_wrdata_mask; +reg litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [14:0] litedramcore_csr_dfi_p1_address; +wire [2:0] litedramcore_csr_dfi_p1_bank; +reg litedramcore_csr_dfi_p1_cas_n = 1'd1; +wire litedramcore_csr_dfi_p1_cke; +reg litedramcore_csr_dfi_p1_cs_n = 1'd1; +wire litedramcore_csr_dfi_p1_odt; +reg litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0; +wire litedramcore_csr_dfi_p1_rddata_en; +reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +wire litedramcore_csr_dfi_p1_reset_n; +reg litedramcore_csr_dfi_p1_we_n = 1'd1; +wire [63:0] litedramcore_csr_dfi_p1_wrdata; +wire litedramcore_csr_dfi_p1_wrdata_en; +wire [7:0] litedramcore_csr_dfi_p1_wrdata_mask; +reg litedramcore_dfi_p0_act_n = 1'd1; +reg [14:0] litedramcore_dfi_p0_address = 15'd0; +reg [2:0] litedramcore_dfi_p0_bank = 3'd0; +reg litedramcore_dfi_p0_cas_n = 1'd1; +wire litedramcore_dfi_p0_cke; +reg litedramcore_dfi_p0_cs_n = 1'd1; +wire litedramcore_dfi_p0_odt; +reg litedramcore_dfi_p0_ras_n = 1'd1; +wire [63:0] litedramcore_dfi_p0_rddata; +reg litedramcore_dfi_p0_rddata_en = 1'd0; +wire litedramcore_dfi_p0_rddata_valid; +wire litedramcore_dfi_p0_reset_n; +reg litedramcore_dfi_p0_we_n = 1'd1; +wire [63:0] litedramcore_dfi_p0_wrdata; +reg litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [7:0] litedramcore_dfi_p0_wrdata_mask; +reg litedramcore_dfi_p1_act_n = 1'd1; +reg [14:0] litedramcore_dfi_p1_address = 15'd0; +reg [2:0] litedramcore_dfi_p1_bank = 3'd0; +reg litedramcore_dfi_p1_cas_n = 1'd1; +wire litedramcore_dfi_p1_cke; +reg litedramcore_dfi_p1_cs_n = 1'd1; +wire litedramcore_dfi_p1_odt; +reg litedramcore_dfi_p1_ras_n = 1'd1; +wire [63:0] litedramcore_dfi_p1_rddata; +reg litedramcore_dfi_p1_rddata_en = 1'd0; +wire litedramcore_dfi_p1_rddata_valid; +wire litedramcore_dfi_p1_reset_n; +reg litedramcore_dfi_p1_we_n = 1'd1; +wire [63:0] litedramcore_dfi_p1_wrdata; +reg litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [7:0] litedramcore_dfi_p1_wrdata_mask; +reg litedramcore_en0 = 1'd0; +reg litedramcore_en1 = 1'd0; +reg litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0; +reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; +reg litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg litedramcore_ext_dfi_p0_cke = 1'd0; +reg litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg litedramcore_ext_dfi_p0_odt = 1'd0; +reg litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0; +reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg litedramcore_ext_dfi_p0_we_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0; +reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0; +reg litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0; +reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; +reg litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg litedramcore_ext_dfi_p1_cke = 1'd0; +reg litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg litedramcore_ext_dfi_p1_odt = 1'd0; +reg litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0; +reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg litedramcore_ext_dfi_p1_we_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0; +reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0; +reg litedramcore_ext_dfi_sel = 1'd0; +wire litedramcore_go_to_refresh; +wire [21:0] litedramcore_interface_bank0_addr; +wire litedramcore_interface_bank0_lock; +wire litedramcore_interface_bank0_rdata_valid; +wire litedramcore_interface_bank0_ready; +wire litedramcore_interface_bank0_valid; +wire litedramcore_interface_bank0_wdata_ready; +wire litedramcore_interface_bank0_we; +wire [21:0] litedramcore_interface_bank1_addr; +wire litedramcore_interface_bank1_lock; +wire litedramcore_interface_bank1_rdata_valid; +wire litedramcore_interface_bank1_ready; +wire litedramcore_interface_bank1_valid; +wire litedramcore_interface_bank1_wdata_ready; +wire litedramcore_interface_bank1_we; +wire [21:0] litedramcore_interface_bank2_addr; +wire litedramcore_interface_bank2_lock; +wire litedramcore_interface_bank2_rdata_valid; +wire litedramcore_interface_bank2_ready; +wire litedramcore_interface_bank2_valid; +wire litedramcore_interface_bank2_wdata_ready; +wire litedramcore_interface_bank2_we; +wire [21:0] litedramcore_interface_bank3_addr; +wire litedramcore_interface_bank3_lock; +wire litedramcore_interface_bank3_rdata_valid; +wire litedramcore_interface_bank3_ready; +wire litedramcore_interface_bank3_valid; +wire litedramcore_interface_bank3_wdata_ready; +wire litedramcore_interface_bank3_we; +wire [21:0] litedramcore_interface_bank4_addr; +wire litedramcore_interface_bank4_lock; +wire litedramcore_interface_bank4_rdata_valid; +wire litedramcore_interface_bank4_ready; +wire litedramcore_interface_bank4_valid; +wire litedramcore_interface_bank4_wdata_ready; +wire litedramcore_interface_bank4_we; +wire [21:0] litedramcore_interface_bank5_addr; +wire litedramcore_interface_bank5_lock; +wire litedramcore_interface_bank5_rdata_valid; +wire litedramcore_interface_bank5_ready; +wire litedramcore_interface_bank5_valid; +wire litedramcore_interface_bank5_wdata_ready; +wire litedramcore_interface_bank5_we; +wire [21:0] litedramcore_interface_bank6_addr; +wire litedramcore_interface_bank6_lock; +wire litedramcore_interface_bank6_rdata_valid; +wire litedramcore_interface_bank6_ready; +wire litedramcore_interface_bank6_valid; +wire litedramcore_interface_bank6_wdata_ready; +wire litedramcore_interface_bank6_we; +wire [21:0] litedramcore_interface_bank7_addr; +wire litedramcore_interface_bank7_lock; +wire litedramcore_interface_bank7_rdata_valid; +wire litedramcore_interface_bank7_ready; +wire litedramcore_interface_bank7_valid; +wire litedramcore_interface_bank7_wdata_ready; +wire litedramcore_interface_bank7_we; +wire [127:0] litedramcore_interface_rdata; +reg [127:0] litedramcore_interface_wdata = 128'd0; +reg [15:0] litedramcore_interface_wdata_we = 16'd0; +reg litedramcore_master_p0_act_n = 1'd1; +reg [14:0] litedramcore_master_p0_address = 15'd0; +reg [2:0] litedramcore_master_p0_bank = 3'd0; +reg litedramcore_master_p0_cas_n = 1'd1; +reg litedramcore_master_p0_cke = 1'd0; +reg litedramcore_master_p0_cs_n = 1'd1; +reg litedramcore_master_p0_odt = 1'd0; +reg litedramcore_master_p0_ras_n = 1'd1; +wire [63:0] litedramcore_master_p0_rddata; +reg litedramcore_master_p0_rddata_en = 1'd0; +wire litedramcore_master_p0_rddata_valid; +reg litedramcore_master_p0_reset_n = 1'd0; +reg litedramcore_master_p0_we_n = 1'd1; +reg [63:0] litedramcore_master_p0_wrdata = 64'd0; +reg litedramcore_master_p0_wrdata_en = 1'd0; +reg [7:0] litedramcore_master_p0_wrdata_mask = 8'd0; +reg litedramcore_master_p1_act_n = 1'd1; +reg [14:0] litedramcore_master_p1_address = 15'd0; +reg [2:0] litedramcore_master_p1_bank = 3'd0; +reg litedramcore_master_p1_cas_n = 1'd1; +reg litedramcore_master_p1_cke = 1'd0; +reg litedramcore_master_p1_cs_n = 1'd1; +reg litedramcore_master_p1_odt = 1'd0; +reg litedramcore_master_p1_ras_n = 1'd1; +wire [63:0] litedramcore_master_p1_rddata; +reg litedramcore_master_p1_rddata_en = 1'd0; +wire litedramcore_master_p1_rddata_valid; +reg litedramcore_master_p1_reset_n = 1'd0; +reg litedramcore_master_p1_we_n = 1'd1; +reg [63:0] litedramcore_master_p1_wrdata = 64'd0; +reg litedramcore_master_p1_wrdata_en = 1'd0; +reg [7:0] litedramcore_master_p1_wrdata_mask = 8'd0; +wire litedramcore_max_time0; +wire litedramcore_max_time1; +reg [14:0] litedramcore_nop_a = 15'd0; +reg [2:0] litedramcore_nop_ba = 3'd0; +wire litedramcore_odt; +reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0; +reg litedramcore_phaseinjector0_address_wr_stb = 1'd0; +reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg litedramcore_phaseinjector0_baddress_wr_stb = 1'd0; +wire litedramcore_phaseinjector0_cas; +wire litedramcore_phaseinjector0_command_issue_r; +reg litedramcore_phaseinjector0_command_issue_re = 1'd0; +reg litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg [7:0] litedramcore_phaseinjector0_command_storage = 8'd0; +reg litedramcore_phaseinjector0_command_wr_stb = 1'd0; +wire litedramcore_phaseinjector0_cs; +wire litedramcore_phaseinjector0_cs_bottom; +wire litedramcore_phaseinjector0_cs_top; +wire litedramcore_phaseinjector0_ras; +wire litedramcore_phaseinjector0_rddata_rd_stb; +reg [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0; +reg litedramcore_phaseinjector0_rddata_wr_stb = 1'd0; +wire litedramcore_phaseinjector0_rden; +wire litedramcore_phaseinjector0_we; +reg [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0; +reg litedramcore_phaseinjector0_wrdata_wr_stb = 1'd0; +wire litedramcore_phaseinjector0_wren; +reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0; +reg litedramcore_phaseinjector1_address_wr_stb = 1'd0; +reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg litedramcore_phaseinjector1_baddress_wr_stb = 1'd0; +wire litedramcore_phaseinjector1_cas; +wire litedramcore_phaseinjector1_command_issue_r; +reg litedramcore_phaseinjector1_command_issue_re = 1'd0; +reg litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg [7:0] litedramcore_phaseinjector1_command_storage = 8'd0; +reg litedramcore_phaseinjector1_command_wr_stb = 1'd0; +wire litedramcore_phaseinjector1_cs; +wire litedramcore_phaseinjector1_cs_bottom; +wire litedramcore_phaseinjector1_cs_top; +wire litedramcore_phaseinjector1_ras; +wire litedramcore_phaseinjector1_rddata_rd_stb; +reg [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0; +reg litedramcore_phaseinjector1_rddata_wr_stb = 1'd0; +wire litedramcore_phaseinjector1_rden; +wire litedramcore_phaseinjector1_we; +reg [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0; +reg litedramcore_phaseinjector1_wrdata_wr_stb = 1'd0; +wire litedramcore_phaseinjector1_wren; +reg litedramcore_postponer_count = 1'd0; +wire litedramcore_postponer_req_i; +reg litedramcore_postponer_req_o = 1'd0; +wire litedramcore_ras_allowed; +wire litedramcore_read_available; +wire litedramcore_reset_n; +wire litedramcore_sel; +reg litedramcore_sequencer_count = 1'd0; +wire litedramcore_sequencer_done0; +reg litedramcore_sequencer_done1 = 1'd0; +reg litedramcore_sequencer_start0 = 1'd0; +wire litedramcore_sequencer_start1; +reg [6:0] litedramcore_sequencer_trigger = 7'd0; +wire litedramcore_slave_p0_act_n; +wire [14:0] litedramcore_slave_p0_address; +wire [2:0] litedramcore_slave_p0_bank; +wire litedramcore_slave_p0_cas_n; +wire litedramcore_slave_p0_cke; +wire litedramcore_slave_p0_cs_n; +wire litedramcore_slave_p0_odt; +wire litedramcore_slave_p0_ras_n; +reg [63:0] litedramcore_slave_p0_rddata = 64'd0; +wire litedramcore_slave_p0_rddata_en; +reg litedramcore_slave_p0_rddata_valid = 1'd0; +wire litedramcore_slave_p0_reset_n; +wire litedramcore_slave_p0_we_n; +wire [63:0] litedramcore_slave_p0_wrdata; +wire litedramcore_slave_p0_wrdata_en; +wire [7:0] litedramcore_slave_p0_wrdata_mask; +wire litedramcore_slave_p1_act_n; +wire [14:0] litedramcore_slave_p1_address; +wire [2:0] litedramcore_slave_p1_bank; +wire litedramcore_slave_p1_cas_n; +wire litedramcore_slave_p1_cke; +wire litedramcore_slave_p1_cs_n; +wire litedramcore_slave_p1_odt; +wire litedramcore_slave_p1_ras_n; +reg [63:0] litedramcore_slave_p1_rddata = 64'd0; +wire litedramcore_slave_p1_rddata_en; +reg litedramcore_slave_p1_rddata_valid = 1'd0; +wire litedramcore_slave_p1_reset_n; +wire litedramcore_slave_p1_we_n; +wire [63:0] litedramcore_slave_p1_wrdata; +wire litedramcore_slave_p1_wrdata_en; +wire [7:0] litedramcore_slave_p1_wrdata_mask; +reg litedramcore_steerer0 = 1'd1; +reg litedramcore_steerer1 = 1'd1; +reg litedramcore_steerer2 = 1'd1; +reg litedramcore_steerer3 = 1'd1; +reg [1:0] litedramcore_steerer_sel0 = 2'd0; +reg [1:0] litedramcore_steerer_sel1 = 2'd0; +reg [3:0] litedramcore_storage = 4'd1; +reg litedramcore_tccdcon_count = 1'd0; +reg litedramcore_tccdcon_ready = 1'd0; +wire litedramcore_tccdcon_valid; +wire [1:0] litedramcore_tfawcon_count; +reg litedramcore_tfawcon_ready = 1'd1; +wire litedramcore_tfawcon_valid; +reg [3:0] litedramcore_tfawcon_window = 4'd0; +reg [4:0] litedramcore_time0 = 5'd0; +reg [3:0] litedramcore_time1 = 4'd0; +wire [9:0] litedramcore_timer_count0; +reg [9:0] litedramcore_timer_count1 = 10'd585; +wire litedramcore_timer_done0; +wire litedramcore_timer_done1; +wire litedramcore_timer_wait; +reg [1:0] litedramcore_trrdcon_count = 2'd0; +reg litedramcore_trrdcon_ready = 1'd0; +wire litedramcore_trrdcon_valid; +reg [2:0] litedramcore_twtrcon_count = 3'd0; +reg litedramcore_twtrcon_ready = 1'd0; +wire litedramcore_twtrcon_valid; +wire litedramcore_wants_refresh; +wire litedramcore_wants_zqcs; +reg litedramcore_wr_stb = 1'd0; +wire litedramcore_write_available; +reg litedramcore_zqcs_executer_done = 1'd0; +reg litedramcore_zqcs_executer_start = 1'd0; +reg [5:0] litedramcore_zqcs_executer_trigger = 6'd0; +wire [26:0] litedramcore_zqcs_timer_count0; +reg [26:0] litedramcore_zqcs_timer_count1 = 27'd74999999; +wire litedramcore_zqcs_timer_done0; +wire litedramcore_zqcs_timer_done1; +wire litedramcore_zqcs_timer_wait; +reg locked0 = 1'd0; +reg locked1 = 1'd0; +reg locked2 = 1'd0; +reg locked3 = 1'd0; +reg locked4 = 1'd0; +reg locked5 = 1'd0; +reg locked6 = 1'd0; +reg locked7 = 1'd0; +wire master; +reg [3:0] multiplexer_next_state = 4'd0; +reg [3:0] multiplexer_state = 4'd0; +reg new_master_rdata_valid0 = 1'd0; +reg new_master_rdata_valid1 = 1'd0; +reg new_master_rdata_valid10 = 1'd0; +reg new_master_rdata_valid11 = 1'd0; +reg new_master_rdata_valid12 = 1'd0; +reg new_master_rdata_valid13 = 1'd0; +reg new_master_rdata_valid2 = 1'd0; +reg new_master_rdata_valid3 = 1'd0; +reg new_master_rdata_valid4 = 1'd0; +reg new_master_rdata_valid5 = 1'd0; +reg new_master_rdata_valid6 = 1'd0; +reg new_master_rdata_valid7 = 1'd0; +reg new_master_rdata_valid8 = 1'd0; +reg new_master_rdata_valid9 = 1'd0; +reg new_master_wdata_ready0 = 1'd0; +reg new_master_wdata_ready1 = 1'd0; +reg new_master_wdata_ready2 = 1'd0; +reg new_master_wdata_ready3 = 1'd0; +reg [1:0] next_state = 2'd0; +wire por_clk; +wire re; +reg [1:0] refresher_next_state = 2'd0; +reg [1:0] refresher_state = 2'd0; +reg regs0 = 1'd0; +reg regs1 = 1'd0; +wire request; +reg [29:0] rhs_self0 = 30'd0; +reg [31:0] rhs_self1 = 32'd0; +reg [2:0] rhs_self10 = 3'd0; +reg rhs_self11 = 1'd0; +reg rhs_self12 = 1'd0; +reg rhs_self13 = 1'd0; +reg rhs_self14 = 1'd0; +reg [14:0] rhs_self15 = 15'd0; +reg [2:0] rhs_self16 = 3'd0; +reg rhs_self17 = 1'd0; +reg rhs_self18 = 1'd0; +reg rhs_self19 = 1'd0; +reg [3:0] rhs_self2 = 4'd0; +reg [21:0] rhs_self20 = 22'd0; +reg rhs_self21 = 1'd0; +reg rhs_self22 = 1'd0; +reg [21:0] rhs_self23 = 22'd0; +reg rhs_self24 = 1'd0; +reg rhs_self25 = 1'd0; +reg [21:0] rhs_self26 = 22'd0; +reg rhs_self27 = 1'd0; +reg rhs_self28 = 1'd0; +reg [21:0] rhs_self29 = 22'd0; +reg rhs_self3 = 1'd0; +reg rhs_self30 = 1'd0; +reg rhs_self31 = 1'd0; +reg [21:0] rhs_self32 = 22'd0; +reg rhs_self33 = 1'd0; +reg rhs_self34 = 1'd0; +reg [21:0] rhs_self35 = 22'd0; +reg rhs_self36 = 1'd0; +reg rhs_self37 = 1'd0; +reg [21:0] rhs_self38 = 22'd0; +reg rhs_self39 = 1'd0; +reg rhs_self4 = 1'd0; +reg rhs_self40 = 1'd0; +reg [21:0] rhs_self41 = 22'd0; +reg rhs_self42 = 1'd0; +reg rhs_self43 = 1'd0; +reg rhs_self5 = 1'd0; +reg [2:0] rhs_self6 = 3'd0; +reg [1:0] rhs_self7 = 2'd0; +reg rhs_self8 = 1'd0; +reg [14:0] rhs_self9 = 15'd0; +wire roundrobin0_ce; +wire roundrobin0_grant; +wire roundrobin0_request; +wire roundrobin1_ce; +wire roundrobin1_grant; +wire roundrobin1_request; +wire roundrobin2_ce; +wire roundrobin2_grant; +wire roundrobin2_request; +wire roundrobin3_ce; +wire roundrobin3_grant; +wire roundrobin3_request; +wire roundrobin4_ce; +wire roundrobin4_grant; +wire roundrobin4_request; +wire roundrobin5_ce; +wire roundrobin5_grant; +wire roundrobin5_request; +wire roundrobin6_ce; +wire roundrobin6_grant; +wire roundrobin6_request; +wire roundrobin7_ce; +wire roundrobin7_grant; +wire roundrobin7_request; +reg selected_r = 1'd0; +reg selected_r_next_value1 = 1'd0; +reg selected_r_next_value_ce1 = 1'd0; +reg [2:0] self0 = 3'd0; +reg [14:0] self1 = 15'd0; +reg self10 = 1'd0; +reg self11 = 1'd0; +reg self12 = 1'd0; +reg self13 = 1'd0; +reg self2 = 1'd0; +reg self3 = 1'd0; +reg self4 = 1'd0; +reg self5 = 1'd0; +reg self6 = 1'd0; +reg [2:0] self7 = 3'd0; +reg [14:0] self8 = 15'd0; +reg self9 = 1'd0; +reg shared_ack = 1'd0; +wire [29:0] shared_adr; +wire [1:0] shared_bte; +wire [2:0] shared_cti; +wire shared_cyc; +reg [31:0] shared_dat_r = 32'd0; +wire [31:0] shared_dat_w; +wire shared_err; +wire [3:0] shared_sel; +wire shared_stb; +wire shared_we; +reg slaves = 1'd0; +reg [1:0] state = 2'd0; +wire sys2x_clk; +wire sys2x_i_clk; +wire sys2x_rst; +wire sys_clk; +wire sys_rst; +reg t_self0 = 1'd0; +reg t_self1 = 1'd0; +reg t_self2 = 1'd0; +reg t_self3 = 1'd0; +reg t_self4 = 1'd0; +reg t_self5 = 1'd0; +reg user_enable = 1'd0; +wire [24:0] user_port_cmd_payload_addr; +wire user_port_cmd_payload_we; +wire user_port_cmd_ready; +wire user_port_cmd_valid; +wire [127:0] user_port_rdata_payload_data; +wire user_port_rdata_ready; +wire user_port_rdata_valid; +wire [127:0] user_port_wdata_payload_data; +wire [15:0] user_port_wdata_payload_we; +wire user_port_wdata_ready; +wire user_port_wdata_valid; +wire wait_1; +wire wb_bus_ack; +wire [29:0] wb_bus_adr; +wire [1:0] wb_bus_bte; +wire [2:0] wb_bus_cti; +wire wb_bus_cyc; +wire [31:0] wb_bus_dat_r; +wire [31:0] wb_bus_dat_w; +wire wb_bus_err; +wire [3:0] wb_bus_sel; +wire wb_bus_stb; +wire wb_bus_we; +wire we; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign crg_stop = ddrphy_stop0; +assign crg_reset0 = ddrphy_reset0; +assign init_done = init_done_storage; +assign init_error = init_error_storage; +assign wb_bus_adr = wb_ctrl_adr; +assign wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = wb_bus_dat_r; +assign wb_bus_sel = wb_ctrl_sel; +assign wb_bus_cyc = wb_ctrl_cyc; +assign wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = wb_bus_ack; +assign wb_bus_we = wb_ctrl_we; +assign wb_bus_cti = wb_ctrl_cti; +assign wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = wb_bus_err; +assign user_clk = sys_clk; +assign user_rst = sys_rst; +assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable); +assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable); +assign user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable); +assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable); +assign user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable); +assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable); +assign user_port_native_0_rdata_data = user_port_rdata_payload_data; +assign shared_adr = rhs_self0; +assign shared_dat_w = rhs_self1; +assign shared_sel = rhs_self2; +assign shared_cyc = rhs_self3; +assign shared_stb = rhs_self4; +assign shared_we = rhs_self5; +assign shared_cti = rhs_self6; +assign shared_bte = rhs_self7; +assign wb_bus_dat_r = shared_dat_r; +assign wb_bus_ack = (shared_ack & (grant == 1'd0)); +assign wb_bus_err = (shared_err & (grant == 1'd0)); +assign request = {wb_bus_cyc}; +assign grant = 1'd0; +assign master = (shared_adr[29:14] == 1'd0); +assign interface0_adr = shared_adr; +assign interface0_dat_w = shared_dat_w; +assign interface0_sel = shared_sel; +assign interface0_stb = shared_stb; +assign interface0_we = shared_we; +assign interface0_cti = shared_cti; +assign interface0_bte = shared_bte; +assign interface0_cyc = (shared_cyc & master); +assign shared_err = interface0_err; +assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack)); +always @(*) begin + error = 1'd0; + shared_ack = 1'd0; + shared_dat_r = 32'd0; + shared_ack = interface0_ack; + shared_dat_r = ({32{slaves}} & interface0_dat_r); + if (done) begin + shared_dat_r = 32'hffffffff; + shared_ack = 1'd1; + error = 1'd1; + end +end +assign done = (count == 1'd0); +assign por_clk = clk; +assign crg_por_done = (crg_por_count == 1'd0); +assign crg_reset1 = (((~crg_por_done) | rst) | crg_rst); +assign pll_locked = crg_locked; +assign crg_clkin_signal = clk; +assign sys2x_i_clk = crg_clkout0; +assign init_clk = crg_clkout1; +assign crg_locked = (ecp5pll_locked & (~crg_reset1)); +always @(*) begin + ddrphy_dm_o_data0 = 8'd0; + ddrphy_dm_o_data0[0] = ddrphy_dfi_p0_wrdata_mask[0]; + ddrphy_dm_o_data0[1] = ddrphy_dfi_p0_wrdata_mask[2]; + ddrphy_dm_o_data0[2] = ddrphy_dfi_p0_wrdata_mask[4]; + ddrphy_dm_o_data0[3] = ddrphy_dfi_p0_wrdata_mask[6]; + ddrphy_dm_o_data0[4] = ddrphy_dfi_p1_wrdata_mask[0]; + ddrphy_dm_o_data0[5] = ddrphy_dfi_p1_wrdata_mask[2]; + ddrphy_dm_o_data0[6] = ddrphy_dfi_p1_wrdata_mask[4]; + ddrphy_dm_o_data0[7] = ddrphy_dfi_p1_wrdata_mask[6]; +end +always @(*) begin + ddrphy_dq_o_data0 = 8'd0; + ddrphy_dq_o_data0[0] = ddrphy_dfi_p0_wrdata[0]; + ddrphy_dq_o_data0[1] = ddrphy_dfi_p0_wrdata[16]; + ddrphy_dq_o_data0[2] = ddrphy_dfi_p0_wrdata[32]; + ddrphy_dq_o_data0[3] = ddrphy_dfi_p0_wrdata[48]; + ddrphy_dq_o_data0[4] = ddrphy_dfi_p1_wrdata[0]; + ddrphy_dq_o_data0[5] = ddrphy_dfi_p1_wrdata[16]; + ddrphy_dq_o_data0[6] = ddrphy_dfi_p1_wrdata[32]; + ddrphy_dq_o_data0[7] = ddrphy_dfi_p1_wrdata[48]; +end +assign ddrphy_dq_i_data0 = {ddrphy_bitslip0_o, ddrphy_dq_i_bitslip_o_d0}; +always @(*) begin + ddrphy_dq_o_data1 = 8'd0; + ddrphy_dq_o_data1[0] = ddrphy_dfi_p0_wrdata[1]; + ddrphy_dq_o_data1[1] = ddrphy_dfi_p0_wrdata[17]; + ddrphy_dq_o_data1[2] = ddrphy_dfi_p0_wrdata[33]; + ddrphy_dq_o_data1[3] = ddrphy_dfi_p0_wrdata[49]; + ddrphy_dq_o_data1[4] = ddrphy_dfi_p1_wrdata[1]; + ddrphy_dq_o_data1[5] = ddrphy_dfi_p1_wrdata[17]; + ddrphy_dq_o_data1[6] = ddrphy_dfi_p1_wrdata[33]; + ddrphy_dq_o_data1[7] = ddrphy_dfi_p1_wrdata[49]; +end +assign ddrphy_dq_i_data1 = {ddrphy_bitslip1_o, ddrphy_dq_i_bitslip_o_d1}; +always @(*) begin + ddrphy_dq_o_data2 = 8'd0; + ddrphy_dq_o_data2[0] = ddrphy_dfi_p0_wrdata[2]; + ddrphy_dq_o_data2[1] = ddrphy_dfi_p0_wrdata[18]; + ddrphy_dq_o_data2[2] = ddrphy_dfi_p0_wrdata[34]; + ddrphy_dq_o_data2[3] = ddrphy_dfi_p0_wrdata[50]; + ddrphy_dq_o_data2[4] = ddrphy_dfi_p1_wrdata[2]; + ddrphy_dq_o_data2[5] = ddrphy_dfi_p1_wrdata[18]; + ddrphy_dq_o_data2[6] = ddrphy_dfi_p1_wrdata[34]; + ddrphy_dq_o_data2[7] = ddrphy_dfi_p1_wrdata[50]; +end +assign ddrphy_dq_i_data2 = {ddrphy_bitslip2_o, ddrphy_dq_i_bitslip_o_d2}; +always @(*) begin + ddrphy_dq_o_data3 = 8'd0; + ddrphy_dq_o_data3[0] = ddrphy_dfi_p0_wrdata[3]; + ddrphy_dq_o_data3[1] = ddrphy_dfi_p0_wrdata[19]; + ddrphy_dq_o_data3[2] = ddrphy_dfi_p0_wrdata[35]; + ddrphy_dq_o_data3[3] = ddrphy_dfi_p0_wrdata[51]; + ddrphy_dq_o_data3[4] = ddrphy_dfi_p1_wrdata[3]; + ddrphy_dq_o_data3[5] = ddrphy_dfi_p1_wrdata[19]; + ddrphy_dq_o_data3[6] = ddrphy_dfi_p1_wrdata[35]; + ddrphy_dq_o_data3[7] = ddrphy_dfi_p1_wrdata[51]; +end +assign ddrphy_dq_i_data3 = {ddrphy_bitslip3_o, ddrphy_dq_i_bitslip_o_d3}; +always @(*) begin + ddrphy_dq_o_data4 = 8'd0; + ddrphy_dq_o_data4[0] = ddrphy_dfi_p0_wrdata[4]; + ddrphy_dq_o_data4[1] = ddrphy_dfi_p0_wrdata[20]; + ddrphy_dq_o_data4[2] = ddrphy_dfi_p0_wrdata[36]; + ddrphy_dq_o_data4[3] = ddrphy_dfi_p0_wrdata[52]; + ddrphy_dq_o_data4[4] = ddrphy_dfi_p1_wrdata[4]; + ddrphy_dq_o_data4[5] = ddrphy_dfi_p1_wrdata[20]; + ddrphy_dq_o_data4[6] = ddrphy_dfi_p1_wrdata[36]; + ddrphy_dq_o_data4[7] = ddrphy_dfi_p1_wrdata[52]; +end +assign ddrphy_dq_i_data4 = {ddrphy_bitslip4_o, ddrphy_dq_i_bitslip_o_d4}; +always @(*) begin + ddrphy_dq_o_data5 = 8'd0; + ddrphy_dq_o_data5[0] = ddrphy_dfi_p0_wrdata[5]; + ddrphy_dq_o_data5[1] = ddrphy_dfi_p0_wrdata[21]; + ddrphy_dq_o_data5[2] = ddrphy_dfi_p0_wrdata[37]; + ddrphy_dq_o_data5[3] = ddrphy_dfi_p0_wrdata[53]; + ddrphy_dq_o_data5[4] = ddrphy_dfi_p1_wrdata[5]; + ddrphy_dq_o_data5[5] = ddrphy_dfi_p1_wrdata[21]; + ddrphy_dq_o_data5[6] = ddrphy_dfi_p1_wrdata[37]; + ddrphy_dq_o_data5[7] = ddrphy_dfi_p1_wrdata[53]; +end +assign ddrphy_dq_i_data5 = {ddrphy_bitslip5_o, ddrphy_dq_i_bitslip_o_d5}; +always @(*) begin + ddrphy_dq_o_data6 = 8'd0; + ddrphy_dq_o_data6[0] = ddrphy_dfi_p0_wrdata[6]; + ddrphy_dq_o_data6[1] = ddrphy_dfi_p0_wrdata[22]; + ddrphy_dq_o_data6[2] = ddrphy_dfi_p0_wrdata[38]; + ddrphy_dq_o_data6[3] = ddrphy_dfi_p0_wrdata[54]; + ddrphy_dq_o_data6[4] = ddrphy_dfi_p1_wrdata[6]; + ddrphy_dq_o_data6[5] = ddrphy_dfi_p1_wrdata[22]; + ddrphy_dq_o_data6[6] = ddrphy_dfi_p1_wrdata[38]; + ddrphy_dq_o_data6[7] = ddrphy_dfi_p1_wrdata[54]; +end +assign ddrphy_dq_i_data6 = {ddrphy_bitslip6_o, ddrphy_dq_i_bitslip_o_d6}; +always @(*) begin + ddrphy_dq_o_data7 = 8'd0; + ddrphy_dq_o_data7[0] = ddrphy_dfi_p0_wrdata[7]; + ddrphy_dq_o_data7[1] = ddrphy_dfi_p0_wrdata[23]; + ddrphy_dq_o_data7[2] = ddrphy_dfi_p0_wrdata[39]; + ddrphy_dq_o_data7[3] = ddrphy_dfi_p0_wrdata[55]; + ddrphy_dq_o_data7[4] = ddrphy_dfi_p1_wrdata[7]; + ddrphy_dq_o_data7[5] = ddrphy_dfi_p1_wrdata[23]; + ddrphy_dq_o_data7[6] = ddrphy_dfi_p1_wrdata[39]; + ddrphy_dq_o_data7[7] = ddrphy_dfi_p1_wrdata[55]; +end +assign ddrphy_dq_i_data7 = {ddrphy_bitslip7_o, ddrphy_dq_i_bitslip_o_d7}; +always @(*) begin + ddrphy_dm_o_data1 = 8'd0; + ddrphy_dm_o_data1[0] = ddrphy_dfi_p0_wrdata_mask[1]; + ddrphy_dm_o_data1[1] = ddrphy_dfi_p0_wrdata_mask[3]; + ddrphy_dm_o_data1[2] = ddrphy_dfi_p0_wrdata_mask[5]; + ddrphy_dm_o_data1[3] = ddrphy_dfi_p0_wrdata_mask[7]; + ddrphy_dm_o_data1[4] = ddrphy_dfi_p1_wrdata_mask[1]; + ddrphy_dm_o_data1[5] = ddrphy_dfi_p1_wrdata_mask[3]; + ddrphy_dm_o_data1[6] = ddrphy_dfi_p1_wrdata_mask[5]; + ddrphy_dm_o_data1[7] = ddrphy_dfi_p1_wrdata_mask[7]; +end +always @(*) begin + ddrphy_dq_o_data8 = 8'd0; + ddrphy_dq_o_data8[0] = ddrphy_dfi_p0_wrdata[8]; + ddrphy_dq_o_data8[1] = ddrphy_dfi_p0_wrdata[24]; + ddrphy_dq_o_data8[2] = ddrphy_dfi_p0_wrdata[40]; + ddrphy_dq_o_data8[3] = ddrphy_dfi_p0_wrdata[56]; + ddrphy_dq_o_data8[4] = ddrphy_dfi_p1_wrdata[8]; + ddrphy_dq_o_data8[5] = ddrphy_dfi_p1_wrdata[24]; + ddrphy_dq_o_data8[6] = ddrphy_dfi_p1_wrdata[40]; + ddrphy_dq_o_data8[7] = ddrphy_dfi_p1_wrdata[56]; +end +assign ddrphy_dq_i_data8 = {ddrphy_bitslip8_o, ddrphy_dq_i_bitslip_o_d8}; +always @(*) begin + ddrphy_dq_o_data9 = 8'd0; + ddrphy_dq_o_data9[0] = ddrphy_dfi_p0_wrdata[9]; + ddrphy_dq_o_data9[1] = ddrphy_dfi_p0_wrdata[25]; + ddrphy_dq_o_data9[2] = ddrphy_dfi_p0_wrdata[41]; + ddrphy_dq_o_data9[3] = ddrphy_dfi_p0_wrdata[57]; + ddrphy_dq_o_data9[4] = ddrphy_dfi_p1_wrdata[9]; + ddrphy_dq_o_data9[5] = ddrphy_dfi_p1_wrdata[25]; + ddrphy_dq_o_data9[6] = ddrphy_dfi_p1_wrdata[41]; + ddrphy_dq_o_data9[7] = ddrphy_dfi_p1_wrdata[57]; +end +assign ddrphy_dq_i_data9 = {ddrphy_bitslip9_o, ddrphy_dq_i_bitslip_o_d9}; +always @(*) begin + ddrphy_dq_o_data10 = 8'd0; + ddrphy_dq_o_data10[0] = ddrphy_dfi_p0_wrdata[10]; + ddrphy_dq_o_data10[1] = ddrphy_dfi_p0_wrdata[26]; + ddrphy_dq_o_data10[2] = ddrphy_dfi_p0_wrdata[42]; + ddrphy_dq_o_data10[3] = ddrphy_dfi_p0_wrdata[58]; + ddrphy_dq_o_data10[4] = ddrphy_dfi_p1_wrdata[10]; + ddrphy_dq_o_data10[5] = ddrphy_dfi_p1_wrdata[26]; + ddrphy_dq_o_data10[6] = ddrphy_dfi_p1_wrdata[42]; + ddrphy_dq_o_data10[7] = ddrphy_dfi_p1_wrdata[58]; +end +assign ddrphy_dq_i_data10 = {ddrphy_bitslip10_o, ddrphy_dq_i_bitslip_o_d10}; +always @(*) begin + ddrphy_dq_o_data11 = 8'd0; + ddrphy_dq_o_data11[0] = ddrphy_dfi_p0_wrdata[11]; + ddrphy_dq_o_data11[1] = ddrphy_dfi_p0_wrdata[27]; + ddrphy_dq_o_data11[2] = ddrphy_dfi_p0_wrdata[43]; + ddrphy_dq_o_data11[3] = ddrphy_dfi_p0_wrdata[59]; + ddrphy_dq_o_data11[4] = ddrphy_dfi_p1_wrdata[11]; + ddrphy_dq_o_data11[5] = ddrphy_dfi_p1_wrdata[27]; + ddrphy_dq_o_data11[6] = ddrphy_dfi_p1_wrdata[43]; + ddrphy_dq_o_data11[7] = ddrphy_dfi_p1_wrdata[59]; +end +assign ddrphy_dq_i_data11 = {ddrphy_bitslip11_o, ddrphy_dq_i_bitslip_o_d11}; +always @(*) begin + ddrphy_dq_o_data12 = 8'd0; + ddrphy_dq_o_data12[0] = ddrphy_dfi_p0_wrdata[12]; + ddrphy_dq_o_data12[1] = ddrphy_dfi_p0_wrdata[28]; + ddrphy_dq_o_data12[2] = ddrphy_dfi_p0_wrdata[44]; + ddrphy_dq_o_data12[3] = ddrphy_dfi_p0_wrdata[60]; + ddrphy_dq_o_data12[4] = ddrphy_dfi_p1_wrdata[12]; + ddrphy_dq_o_data12[5] = ddrphy_dfi_p1_wrdata[28]; + ddrphy_dq_o_data12[6] = ddrphy_dfi_p1_wrdata[44]; + ddrphy_dq_o_data12[7] = ddrphy_dfi_p1_wrdata[60]; +end +assign ddrphy_dq_i_data12 = {ddrphy_bitslip12_o, ddrphy_dq_i_bitslip_o_d12}; +always @(*) begin + ddrphy_dq_o_data13 = 8'd0; + ddrphy_dq_o_data13[0] = ddrphy_dfi_p0_wrdata[13]; + ddrphy_dq_o_data13[1] = ddrphy_dfi_p0_wrdata[29]; + ddrphy_dq_o_data13[2] = ddrphy_dfi_p0_wrdata[45]; + ddrphy_dq_o_data13[3] = ddrphy_dfi_p0_wrdata[61]; + ddrphy_dq_o_data13[4] = ddrphy_dfi_p1_wrdata[13]; + ddrphy_dq_o_data13[5] = ddrphy_dfi_p1_wrdata[29]; + ddrphy_dq_o_data13[6] = ddrphy_dfi_p1_wrdata[45]; + ddrphy_dq_o_data13[7] = ddrphy_dfi_p1_wrdata[61]; +end +assign ddrphy_dq_i_data13 = {ddrphy_bitslip13_o, ddrphy_dq_i_bitslip_o_d13}; +always @(*) begin + ddrphy_dq_o_data14 = 8'd0; + ddrphy_dq_o_data14[0] = ddrphy_dfi_p0_wrdata[14]; + ddrphy_dq_o_data14[1] = ddrphy_dfi_p0_wrdata[30]; + ddrphy_dq_o_data14[2] = ddrphy_dfi_p0_wrdata[46]; + ddrphy_dq_o_data14[3] = ddrphy_dfi_p0_wrdata[62]; + ddrphy_dq_o_data14[4] = ddrphy_dfi_p1_wrdata[14]; + ddrphy_dq_o_data14[5] = ddrphy_dfi_p1_wrdata[30]; + ddrphy_dq_o_data14[6] = ddrphy_dfi_p1_wrdata[46]; + ddrphy_dq_o_data14[7] = ddrphy_dfi_p1_wrdata[62]; +end +assign ddrphy_dq_i_data14 = {ddrphy_bitslip14_o, ddrphy_dq_i_bitslip_o_d14}; +always @(*) begin + ddrphy_dq_o_data15 = 8'd0; + ddrphy_dq_o_data15[0] = ddrphy_dfi_p0_wrdata[15]; + ddrphy_dq_o_data15[1] = ddrphy_dfi_p0_wrdata[31]; + ddrphy_dq_o_data15[2] = ddrphy_dfi_p0_wrdata[47]; + ddrphy_dq_o_data15[3] = ddrphy_dfi_p0_wrdata[63]; + ddrphy_dq_o_data15[4] = ddrphy_dfi_p1_wrdata[15]; + ddrphy_dq_o_data15[5] = ddrphy_dfi_p1_wrdata[31]; + ddrphy_dq_o_data15[6] = ddrphy_dfi_p1_wrdata[47]; + ddrphy_dq_o_data15[7] = ddrphy_dfi_p1_wrdata[63]; +end +assign ddrphy_dq_i_data15 = {ddrphy_bitslip15_o, ddrphy_dq_i_bitslip_o_d15}; +always @(*) begin + ddrphy_dfi_p0_rddata = 64'd0; + ddrphy_dfi_p0_rddata[0] = ddrphy_dq_i_data0[0]; + ddrphy_dfi_p0_rddata[16] = ddrphy_dq_i_data0[1]; + ddrphy_dfi_p0_rddata[32] = ddrphy_dq_i_data0[2]; + ddrphy_dfi_p0_rddata[48] = ddrphy_dq_i_data0[3]; + ddrphy_dfi_p0_rddata[1] = ddrphy_dq_i_data1[0]; + ddrphy_dfi_p0_rddata[17] = ddrphy_dq_i_data1[1]; + ddrphy_dfi_p0_rddata[33] = ddrphy_dq_i_data1[2]; + ddrphy_dfi_p0_rddata[49] = ddrphy_dq_i_data1[3]; + ddrphy_dfi_p0_rddata[2] = ddrphy_dq_i_data2[0]; + ddrphy_dfi_p0_rddata[18] = ddrphy_dq_i_data2[1]; + ddrphy_dfi_p0_rddata[34] = ddrphy_dq_i_data2[2]; + ddrphy_dfi_p0_rddata[50] = ddrphy_dq_i_data2[3]; + ddrphy_dfi_p0_rddata[3] = ddrphy_dq_i_data3[0]; + ddrphy_dfi_p0_rddata[19] = ddrphy_dq_i_data3[1]; + ddrphy_dfi_p0_rddata[35] = ddrphy_dq_i_data3[2]; + ddrphy_dfi_p0_rddata[51] = ddrphy_dq_i_data3[3]; + ddrphy_dfi_p0_rddata[4] = ddrphy_dq_i_data4[0]; + ddrphy_dfi_p0_rddata[20] = ddrphy_dq_i_data4[1]; + ddrphy_dfi_p0_rddata[36] = ddrphy_dq_i_data4[2]; + ddrphy_dfi_p0_rddata[52] = ddrphy_dq_i_data4[3]; + ddrphy_dfi_p0_rddata[5] = ddrphy_dq_i_data5[0]; + ddrphy_dfi_p0_rddata[21] = ddrphy_dq_i_data5[1]; + ddrphy_dfi_p0_rddata[37] = ddrphy_dq_i_data5[2]; + ddrphy_dfi_p0_rddata[53] = ddrphy_dq_i_data5[3]; + ddrphy_dfi_p0_rddata[6] = ddrphy_dq_i_data6[0]; + ddrphy_dfi_p0_rddata[22] = ddrphy_dq_i_data6[1]; + ddrphy_dfi_p0_rddata[38] = ddrphy_dq_i_data6[2]; + ddrphy_dfi_p0_rddata[54] = ddrphy_dq_i_data6[3]; + ddrphy_dfi_p0_rddata[7] = ddrphy_dq_i_data7[0]; + ddrphy_dfi_p0_rddata[23] = ddrphy_dq_i_data7[1]; + ddrphy_dfi_p0_rddata[39] = ddrphy_dq_i_data7[2]; + ddrphy_dfi_p0_rddata[55] = ddrphy_dq_i_data7[3]; + ddrphy_dfi_p0_rddata[8] = ddrphy_dq_i_data8[0]; + ddrphy_dfi_p0_rddata[24] = ddrphy_dq_i_data8[1]; + ddrphy_dfi_p0_rddata[40] = ddrphy_dq_i_data8[2]; + ddrphy_dfi_p0_rddata[56] = ddrphy_dq_i_data8[3]; + ddrphy_dfi_p0_rddata[9] = ddrphy_dq_i_data9[0]; + ddrphy_dfi_p0_rddata[25] = ddrphy_dq_i_data9[1]; + ddrphy_dfi_p0_rddata[41] = ddrphy_dq_i_data9[2]; + ddrphy_dfi_p0_rddata[57] = ddrphy_dq_i_data9[3]; + ddrphy_dfi_p0_rddata[10] = ddrphy_dq_i_data10[0]; + ddrphy_dfi_p0_rddata[26] = ddrphy_dq_i_data10[1]; + ddrphy_dfi_p0_rddata[42] = ddrphy_dq_i_data10[2]; + ddrphy_dfi_p0_rddata[58] = ddrphy_dq_i_data10[3]; + ddrphy_dfi_p0_rddata[11] = ddrphy_dq_i_data11[0]; + ddrphy_dfi_p0_rddata[27] = ddrphy_dq_i_data11[1]; + ddrphy_dfi_p0_rddata[43] = ddrphy_dq_i_data11[2]; + ddrphy_dfi_p0_rddata[59] = ddrphy_dq_i_data11[3]; + ddrphy_dfi_p0_rddata[12] = ddrphy_dq_i_data12[0]; + ddrphy_dfi_p0_rddata[28] = ddrphy_dq_i_data12[1]; + ddrphy_dfi_p0_rddata[44] = ddrphy_dq_i_data12[2]; + ddrphy_dfi_p0_rddata[60] = ddrphy_dq_i_data12[3]; + ddrphy_dfi_p0_rddata[13] = ddrphy_dq_i_data13[0]; + ddrphy_dfi_p0_rddata[29] = ddrphy_dq_i_data13[1]; + ddrphy_dfi_p0_rddata[45] = ddrphy_dq_i_data13[2]; + ddrphy_dfi_p0_rddata[61] = ddrphy_dq_i_data13[3]; + ddrphy_dfi_p0_rddata[14] = ddrphy_dq_i_data14[0]; + ddrphy_dfi_p0_rddata[30] = ddrphy_dq_i_data14[1]; + ddrphy_dfi_p0_rddata[46] = ddrphy_dq_i_data14[2]; + ddrphy_dfi_p0_rddata[62] = ddrphy_dq_i_data14[3]; + ddrphy_dfi_p0_rddata[15] = ddrphy_dq_i_data15[0]; + ddrphy_dfi_p0_rddata[31] = ddrphy_dq_i_data15[1]; + ddrphy_dfi_p0_rddata[47] = ddrphy_dq_i_data15[2]; + ddrphy_dfi_p0_rddata[63] = ddrphy_dq_i_data15[3]; +end +always @(*) begin + ddrphy_dfi_p1_rddata = 64'd0; + ddrphy_dfi_p1_rddata[0] = ddrphy_dq_i_data0[4]; + ddrphy_dfi_p1_rddata[16] = ddrphy_dq_i_data0[5]; + ddrphy_dfi_p1_rddata[32] = ddrphy_dq_i_data0[6]; + ddrphy_dfi_p1_rddata[48] = ddrphy_dq_i_data0[7]; + ddrphy_dfi_p1_rddata[1] = ddrphy_dq_i_data1[4]; + ddrphy_dfi_p1_rddata[17] = ddrphy_dq_i_data1[5]; + ddrphy_dfi_p1_rddata[33] = ddrphy_dq_i_data1[6]; + ddrphy_dfi_p1_rddata[49] = ddrphy_dq_i_data1[7]; + ddrphy_dfi_p1_rddata[2] = ddrphy_dq_i_data2[4]; + ddrphy_dfi_p1_rddata[18] = ddrphy_dq_i_data2[5]; + ddrphy_dfi_p1_rddata[34] = ddrphy_dq_i_data2[6]; + ddrphy_dfi_p1_rddata[50] = ddrphy_dq_i_data2[7]; + ddrphy_dfi_p1_rddata[3] = ddrphy_dq_i_data3[4]; + ddrphy_dfi_p1_rddata[19] = ddrphy_dq_i_data3[5]; + ddrphy_dfi_p1_rddata[35] = ddrphy_dq_i_data3[6]; + ddrphy_dfi_p1_rddata[51] = ddrphy_dq_i_data3[7]; + ddrphy_dfi_p1_rddata[4] = ddrphy_dq_i_data4[4]; + ddrphy_dfi_p1_rddata[20] = ddrphy_dq_i_data4[5]; + ddrphy_dfi_p1_rddata[36] = ddrphy_dq_i_data4[6]; + ddrphy_dfi_p1_rddata[52] = ddrphy_dq_i_data4[7]; + ddrphy_dfi_p1_rddata[5] = ddrphy_dq_i_data5[4]; + ddrphy_dfi_p1_rddata[21] = ddrphy_dq_i_data5[5]; + ddrphy_dfi_p1_rddata[37] = ddrphy_dq_i_data5[6]; + ddrphy_dfi_p1_rddata[53] = ddrphy_dq_i_data5[7]; + ddrphy_dfi_p1_rddata[6] = ddrphy_dq_i_data6[4]; + ddrphy_dfi_p1_rddata[22] = ddrphy_dq_i_data6[5]; + ddrphy_dfi_p1_rddata[38] = ddrphy_dq_i_data6[6]; + ddrphy_dfi_p1_rddata[54] = ddrphy_dq_i_data6[7]; + ddrphy_dfi_p1_rddata[7] = ddrphy_dq_i_data7[4]; + ddrphy_dfi_p1_rddata[23] = ddrphy_dq_i_data7[5]; + ddrphy_dfi_p1_rddata[39] = ddrphy_dq_i_data7[6]; + ddrphy_dfi_p1_rddata[55] = ddrphy_dq_i_data7[7]; + ddrphy_dfi_p1_rddata[8] = ddrphy_dq_i_data8[4]; + ddrphy_dfi_p1_rddata[24] = ddrphy_dq_i_data8[5]; + ddrphy_dfi_p1_rddata[40] = ddrphy_dq_i_data8[6]; + ddrphy_dfi_p1_rddata[56] = ddrphy_dq_i_data8[7]; + ddrphy_dfi_p1_rddata[9] = ddrphy_dq_i_data9[4]; + ddrphy_dfi_p1_rddata[25] = ddrphy_dq_i_data9[5]; + ddrphy_dfi_p1_rddata[41] = ddrphy_dq_i_data9[6]; + ddrphy_dfi_p1_rddata[57] = ddrphy_dq_i_data9[7]; + ddrphy_dfi_p1_rddata[10] = ddrphy_dq_i_data10[4]; + ddrphy_dfi_p1_rddata[26] = ddrphy_dq_i_data10[5]; + ddrphy_dfi_p1_rddata[42] = ddrphy_dq_i_data10[6]; + ddrphy_dfi_p1_rddata[58] = ddrphy_dq_i_data10[7]; + ddrphy_dfi_p1_rddata[11] = ddrphy_dq_i_data11[4]; + ddrphy_dfi_p1_rddata[27] = ddrphy_dq_i_data11[5]; + ddrphy_dfi_p1_rddata[43] = ddrphy_dq_i_data11[6]; + ddrphy_dfi_p1_rddata[59] = ddrphy_dq_i_data11[7]; + ddrphy_dfi_p1_rddata[12] = ddrphy_dq_i_data12[4]; + ddrphy_dfi_p1_rddata[28] = ddrphy_dq_i_data12[5]; + ddrphy_dfi_p1_rddata[44] = ddrphy_dq_i_data12[6]; + ddrphy_dfi_p1_rddata[60] = ddrphy_dq_i_data12[7]; + ddrphy_dfi_p1_rddata[13] = ddrphy_dq_i_data13[4]; + ddrphy_dfi_p1_rddata[29] = ddrphy_dq_i_data13[5]; + ddrphy_dfi_p1_rddata[45] = ddrphy_dq_i_data13[6]; + ddrphy_dfi_p1_rddata[61] = ddrphy_dq_i_data13[7]; + ddrphy_dfi_p1_rddata[14] = ddrphy_dq_i_data14[4]; + ddrphy_dfi_p1_rddata[30] = ddrphy_dq_i_data14[5]; + ddrphy_dfi_p1_rddata[46] = ddrphy_dq_i_data14[6]; + ddrphy_dfi_p1_rddata[62] = ddrphy_dq_i_data14[7]; + ddrphy_dfi_p1_rddata[15] = ddrphy_dq_i_data15[4]; + ddrphy_dfi_p1_rddata[31] = ddrphy_dq_i_data15[5]; + ddrphy_dfi_p1_rddata[47] = ddrphy_dq_i_data15[6]; + ddrphy_dfi_p1_rddata[63] = ddrphy_dq_i_data15[7]; +end +assign ddrphy_dfi_p0_rddata_valid = ddrphy_rddata_en_tappeddelayline12; +assign ddrphy_dfi_p1_rddata_valid = ddrphy_rddata_en_tappeddelayline12; +assign ddrphy_dqs_re = (ddrphy_rddata_en_tappeddelayline3 | ddrphy_rddata_en_tappeddelayline4); +assign ddrphy_dq_oe = (ddrphy_wrdata_en_tappeddelayline3 | ddrphy_wrdata_en_tappeddelayline4); +assign ddrphy_bl8_chunk = ddrphy_wrdata_en_tappeddelayline3; +assign ddrphy_dqs_oe = ddrphy_dq_oe; +assign ddrphy_dqs_preamble = (ddrphy_wrdata_en_tappeddelayline2 & (~ddrphy_wrdata_en_tappeddelayline3)); +assign ddrphy_dqs_postamble = (ddrphy_wrdata_en_tappeddelayline5 & (~ddrphy_wrdata_en_tappeddelayline4)); +assign ddrphy_new_lock = (ddrphy_lock1 & (~ddrphy_lock_d)); +assign ddrphy_pause0 = ddrphy_pause1; +assign ddrphy_stop0 = ddrphy_stop1; +assign ddrphy_delay0 = ddrphy_delay1; +assign ddrphy_reset0 = ddrphy_reset1; +always @(*) begin + ddrphy_bitslip0_o = 4'd0; + case (ddrphy_bitslip0_value) + 1'd0: begin + ddrphy_bitslip0_o = ddrphy_bitslip0_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip0_o = ddrphy_bitslip0_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip0_o = ddrphy_bitslip0_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip0_o = ddrphy_bitslip0_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip1_o = 4'd0; + case (ddrphy_bitslip1_value) + 1'd0: begin + ddrphy_bitslip1_o = ddrphy_bitslip1_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip1_o = ddrphy_bitslip1_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip1_o = ddrphy_bitslip1_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip1_o = ddrphy_bitslip1_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip2_o = 4'd0; + case (ddrphy_bitslip2_value) + 1'd0: begin + ddrphy_bitslip2_o = ddrphy_bitslip2_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip2_o = ddrphy_bitslip2_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip2_o = ddrphy_bitslip2_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip2_o = ddrphy_bitslip2_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip3_o = 4'd0; + case (ddrphy_bitslip3_value) + 1'd0: begin + ddrphy_bitslip3_o = ddrphy_bitslip3_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip3_o = ddrphy_bitslip3_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip3_o = ddrphy_bitslip3_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip3_o = ddrphy_bitslip3_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip4_o = 4'd0; + case (ddrphy_bitslip4_value) + 1'd0: begin + ddrphy_bitslip4_o = ddrphy_bitslip4_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip4_o = ddrphy_bitslip4_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip4_o = ddrphy_bitslip4_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip4_o = ddrphy_bitslip4_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip5_o = 4'd0; + case (ddrphy_bitslip5_value) + 1'd0: begin + ddrphy_bitslip5_o = ddrphy_bitslip5_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip5_o = ddrphy_bitslip5_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip5_o = ddrphy_bitslip5_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip5_o = ddrphy_bitslip5_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip6_o = 4'd0; + case (ddrphy_bitslip6_value) + 1'd0: begin + ddrphy_bitslip6_o = ddrphy_bitslip6_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip6_o = ddrphy_bitslip6_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip6_o = ddrphy_bitslip6_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip6_o = ddrphy_bitslip6_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip7_o = 4'd0; + case (ddrphy_bitslip7_value) + 1'd0: begin + ddrphy_bitslip7_o = ddrphy_bitslip7_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip7_o = ddrphy_bitslip7_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip7_o = ddrphy_bitslip7_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip7_o = ddrphy_bitslip7_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip8_o = 4'd0; + case (ddrphy_bitslip8_value) + 1'd0: begin + ddrphy_bitslip8_o = ddrphy_bitslip8_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip8_o = ddrphy_bitslip8_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip8_o = ddrphy_bitslip8_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip8_o = ddrphy_bitslip8_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip9_o = 4'd0; + case (ddrphy_bitslip9_value) + 1'd0: begin + ddrphy_bitslip9_o = ddrphy_bitslip9_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip9_o = ddrphy_bitslip9_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip9_o = ddrphy_bitslip9_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip9_o = ddrphy_bitslip9_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip10_o = 4'd0; + case (ddrphy_bitslip10_value) + 1'd0: begin + ddrphy_bitslip10_o = ddrphy_bitslip10_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip10_o = ddrphy_bitslip10_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip10_o = ddrphy_bitslip10_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip10_o = ddrphy_bitslip10_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip11_o = 4'd0; + case (ddrphy_bitslip11_value) + 1'd0: begin + ddrphy_bitslip11_o = ddrphy_bitslip11_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip11_o = ddrphy_bitslip11_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip11_o = ddrphy_bitslip11_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip11_o = ddrphy_bitslip11_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip12_o = 4'd0; + case (ddrphy_bitslip12_value) + 1'd0: begin + ddrphy_bitslip12_o = ddrphy_bitslip12_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip12_o = ddrphy_bitslip12_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip12_o = ddrphy_bitslip12_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip12_o = ddrphy_bitslip12_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip13_o = 4'd0; + case (ddrphy_bitslip13_value) + 1'd0: begin + ddrphy_bitslip13_o = ddrphy_bitslip13_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip13_o = ddrphy_bitslip13_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip13_o = ddrphy_bitslip13_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip13_o = ddrphy_bitslip13_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip14_o = 4'd0; + case (ddrphy_bitslip14_value) + 1'd0: begin + ddrphy_bitslip14_o = ddrphy_bitslip14_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip14_o = ddrphy_bitslip14_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip14_o = ddrphy_bitslip14_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip14_o = ddrphy_bitslip14_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip15_o = 4'd0; + case (ddrphy_bitslip15_value) + 1'd0: begin + ddrphy_bitslip15_o = ddrphy_bitslip15_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip15_o = ddrphy_bitslip15_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip15_o = ddrphy_bitslip15_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip15_o = ddrphy_bitslip15_r[6:3]; + end + endcase +end +assign ddrphy_dfi_p0_address = litedramcore_master_p0_address; +assign ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; +assign ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n; +assign ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n; +assign ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n; +assign ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n; +assign ddrphy_dfi_p0_cke = litedramcore_master_p0_cke; +assign ddrphy_dfi_p0_odt = litedramcore_master_p0_odt; +assign ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n; +assign ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n; +assign ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata; +assign ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en; +assign ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask; +assign ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en; +assign litedramcore_master_p0_rddata = ddrphy_dfi_p0_rddata; +assign litedramcore_master_p0_rddata_valid = ddrphy_dfi_p0_rddata_valid; +assign ddrphy_dfi_p1_address = litedramcore_master_p1_address; +assign ddrphy_dfi_p1_bank = litedramcore_master_p1_bank; +assign ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n; +assign ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n; +assign ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n; +assign ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n; +assign ddrphy_dfi_p1_cke = litedramcore_master_p1_cke; +assign ddrphy_dfi_p1_odt = litedramcore_master_p1_odt; +assign ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n; +assign ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n; +assign ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata; +assign ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en; +assign ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask; +assign ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en; +assign litedramcore_master_p1_rddata = ddrphy_dfi_p1_rddata; +assign litedramcore_master_p1_rddata_valid = ddrphy_dfi_p1_rddata_valid; +assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address; +assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank; +assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n; +assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n; +assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n; +assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n; +assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke; +assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt; +assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n; +assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n; +assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata; +assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en; +assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask; +assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en; +assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata; +assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid; +assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address; +assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank; +assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n; +assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n; +assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n; +assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n; +assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke; +assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt; +assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n; +assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n; +assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata; +assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en; +assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask; +assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en; +assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata; +assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid; +always @(*) begin + litedramcore_csr_dfi_p0_rddata = 64'd0; + litedramcore_csr_dfi_p0_rddata_valid = 1'd0; + litedramcore_csr_dfi_p1_rddata = 64'd0; + litedramcore_csr_dfi_p1_rddata_valid = 1'd0; + litedramcore_ext_dfi_p0_rddata = 64'd0; + litedramcore_ext_dfi_p0_rddata_valid = 1'd0; + litedramcore_ext_dfi_p1_rddata = 64'd0; + litedramcore_ext_dfi_p1_rddata_valid = 1'd0; + litedramcore_master_p0_act_n = 1'd1; + litedramcore_master_p0_address = 15'd0; + litedramcore_master_p0_bank = 3'd0; + litedramcore_master_p0_cas_n = 1'd1; + litedramcore_master_p0_cke = 1'd0; + litedramcore_master_p0_cs_n = 1'd1; + litedramcore_master_p0_odt = 1'd0; + litedramcore_master_p0_ras_n = 1'd1; + litedramcore_master_p0_rddata_en = 1'd0; + litedramcore_master_p0_reset_n = 1'd0; + litedramcore_master_p0_we_n = 1'd1; + litedramcore_master_p0_wrdata = 64'd0; + litedramcore_master_p0_wrdata_en = 1'd0; + litedramcore_master_p0_wrdata_mask = 8'd0; + litedramcore_master_p1_act_n = 1'd1; + litedramcore_master_p1_address = 15'd0; + litedramcore_master_p1_bank = 3'd0; + litedramcore_master_p1_cas_n = 1'd1; + litedramcore_master_p1_cke = 1'd0; + litedramcore_master_p1_cs_n = 1'd1; + litedramcore_master_p1_odt = 1'd0; + litedramcore_master_p1_ras_n = 1'd1; + litedramcore_master_p1_rddata_en = 1'd0; + litedramcore_master_p1_reset_n = 1'd0; + litedramcore_master_p1_we_n = 1'd1; + litedramcore_master_p1_wrdata = 64'd0; + litedramcore_master_p1_wrdata_en = 1'd0; + litedramcore_master_p1_wrdata_mask = 8'd0; + litedramcore_slave_p0_rddata = 64'd0; + litedramcore_slave_p0_rddata_valid = 1'd0; + litedramcore_slave_p1_rddata = 64'd0; + litedramcore_slave_p1_rddata_valid = 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_address = litedramcore_ext_dfi_p0_address; + litedramcore_master_p0_bank = litedramcore_ext_dfi_p0_bank; + litedramcore_master_p0_cas_n = litedramcore_ext_dfi_p0_cas_n; + litedramcore_master_p0_cs_n = litedramcore_ext_dfi_p0_cs_n; + litedramcore_master_p0_ras_n = litedramcore_ext_dfi_p0_ras_n; + litedramcore_master_p0_we_n = litedramcore_ext_dfi_p0_we_n; + litedramcore_master_p0_cke = litedramcore_ext_dfi_p0_cke; + litedramcore_master_p0_odt = litedramcore_ext_dfi_p0_odt; + litedramcore_master_p0_reset_n = litedramcore_ext_dfi_p0_reset_n; + litedramcore_master_p0_act_n = litedramcore_ext_dfi_p0_act_n; + litedramcore_master_p0_wrdata = litedramcore_ext_dfi_p0_wrdata; + litedramcore_master_p0_wrdata_en = litedramcore_ext_dfi_p0_wrdata_en; + litedramcore_master_p0_wrdata_mask = litedramcore_ext_dfi_p0_wrdata_mask; + litedramcore_master_p0_rddata_en = litedramcore_ext_dfi_p0_rddata_en; + litedramcore_ext_dfi_p0_rddata = litedramcore_master_p0_rddata; + litedramcore_ext_dfi_p0_rddata_valid = litedramcore_master_p0_rddata_valid; + litedramcore_master_p1_address = litedramcore_ext_dfi_p1_address; + litedramcore_master_p1_bank = litedramcore_ext_dfi_p1_bank; + litedramcore_master_p1_cas_n = litedramcore_ext_dfi_p1_cas_n; + litedramcore_master_p1_cs_n = litedramcore_ext_dfi_p1_cs_n; + litedramcore_master_p1_ras_n = litedramcore_ext_dfi_p1_ras_n; + litedramcore_master_p1_we_n = litedramcore_ext_dfi_p1_we_n; + litedramcore_master_p1_cke = litedramcore_ext_dfi_p1_cke; + litedramcore_master_p1_odt = litedramcore_ext_dfi_p1_odt; + litedramcore_master_p1_reset_n = litedramcore_ext_dfi_p1_reset_n; + litedramcore_master_p1_act_n = litedramcore_ext_dfi_p1_act_n; + litedramcore_master_p1_wrdata = litedramcore_ext_dfi_p1_wrdata; + litedramcore_master_p1_wrdata_en = litedramcore_ext_dfi_p1_wrdata_en; + litedramcore_master_p1_wrdata_mask = litedramcore_ext_dfi_p1_wrdata_mask; + litedramcore_master_p1_rddata_en = litedramcore_ext_dfi_p1_rddata_en; + litedramcore_ext_dfi_p1_rddata = litedramcore_master_p1_rddata; + litedramcore_ext_dfi_p1_rddata_valid = litedramcore_master_p1_rddata_valid; + end else begin + litedramcore_master_p0_address = litedramcore_slave_p0_address; + litedramcore_master_p0_bank = litedramcore_slave_p0_bank; + litedramcore_master_p0_cas_n = litedramcore_slave_p0_cas_n; + litedramcore_master_p0_cs_n = litedramcore_slave_p0_cs_n; + litedramcore_master_p0_ras_n = litedramcore_slave_p0_ras_n; + litedramcore_master_p0_we_n = litedramcore_slave_p0_we_n; + litedramcore_master_p0_cke = litedramcore_slave_p0_cke; + litedramcore_master_p0_odt = litedramcore_slave_p0_odt; + litedramcore_master_p0_reset_n = litedramcore_slave_p0_reset_n; + litedramcore_master_p0_act_n = litedramcore_slave_p0_act_n; + litedramcore_master_p0_wrdata = litedramcore_slave_p0_wrdata; + litedramcore_master_p0_wrdata_en = litedramcore_slave_p0_wrdata_en; + litedramcore_master_p0_wrdata_mask = litedramcore_slave_p0_wrdata_mask; + litedramcore_master_p0_rddata_en = litedramcore_slave_p0_rddata_en; + litedramcore_slave_p0_rddata = litedramcore_master_p0_rddata; + litedramcore_slave_p0_rddata_valid = litedramcore_master_p0_rddata_valid; + litedramcore_master_p1_address = litedramcore_slave_p1_address; + litedramcore_master_p1_bank = litedramcore_slave_p1_bank; + litedramcore_master_p1_cas_n = litedramcore_slave_p1_cas_n; + litedramcore_master_p1_cs_n = litedramcore_slave_p1_cs_n; + litedramcore_master_p1_ras_n = litedramcore_slave_p1_ras_n; + litedramcore_master_p1_we_n = litedramcore_slave_p1_we_n; + litedramcore_master_p1_cke = litedramcore_slave_p1_cke; + litedramcore_master_p1_odt = litedramcore_slave_p1_odt; + litedramcore_master_p1_reset_n = litedramcore_slave_p1_reset_n; + litedramcore_master_p1_act_n = litedramcore_slave_p1_act_n; + litedramcore_master_p1_wrdata = litedramcore_slave_p1_wrdata; + litedramcore_master_p1_wrdata_en = litedramcore_slave_p1_wrdata_en; + litedramcore_master_p1_wrdata_mask = litedramcore_slave_p1_wrdata_mask; + litedramcore_master_p1_rddata_en = litedramcore_slave_p1_rddata_en; + litedramcore_slave_p1_rddata = litedramcore_master_p1_rddata; + litedramcore_slave_p1_rddata_valid = litedramcore_master_p1_rddata_valid; + if (1'd0) begin + litedramcore_master_p0_cs_n = {2{litedramcore_slave_p0_cs_n}}; + litedramcore_master_p1_cs_n = {2{litedramcore_slave_p1_cs_n}}; + end + end + end else begin + litedramcore_master_p0_address = litedramcore_csr_dfi_p0_address; + litedramcore_master_p0_bank = litedramcore_csr_dfi_p0_bank; + litedramcore_master_p0_cas_n = litedramcore_csr_dfi_p0_cas_n; + litedramcore_master_p0_cs_n = litedramcore_csr_dfi_p0_cs_n; + litedramcore_master_p0_ras_n = litedramcore_csr_dfi_p0_ras_n; + litedramcore_master_p0_we_n = litedramcore_csr_dfi_p0_we_n; + litedramcore_master_p0_cke = litedramcore_csr_dfi_p0_cke; + litedramcore_master_p0_odt = litedramcore_csr_dfi_p0_odt; + litedramcore_master_p0_reset_n = litedramcore_csr_dfi_p0_reset_n; + litedramcore_master_p0_act_n = litedramcore_csr_dfi_p0_act_n; + litedramcore_master_p0_wrdata = litedramcore_csr_dfi_p0_wrdata; + litedramcore_master_p0_wrdata_en = litedramcore_csr_dfi_p0_wrdata_en; + litedramcore_master_p0_wrdata_mask = litedramcore_csr_dfi_p0_wrdata_mask; + litedramcore_master_p0_rddata_en = litedramcore_csr_dfi_p0_rddata_en; + litedramcore_csr_dfi_p0_rddata = litedramcore_master_p0_rddata; + litedramcore_csr_dfi_p0_rddata_valid = litedramcore_master_p0_rddata_valid; + litedramcore_master_p1_address = litedramcore_csr_dfi_p1_address; + litedramcore_master_p1_bank = litedramcore_csr_dfi_p1_bank; + litedramcore_master_p1_cas_n = litedramcore_csr_dfi_p1_cas_n; + litedramcore_master_p1_cs_n = litedramcore_csr_dfi_p1_cs_n; + litedramcore_master_p1_ras_n = litedramcore_csr_dfi_p1_ras_n; + litedramcore_master_p1_we_n = litedramcore_csr_dfi_p1_we_n; + litedramcore_master_p1_cke = litedramcore_csr_dfi_p1_cke; + litedramcore_master_p1_odt = litedramcore_csr_dfi_p1_odt; + litedramcore_master_p1_reset_n = litedramcore_csr_dfi_p1_reset_n; + litedramcore_master_p1_act_n = litedramcore_csr_dfi_p1_act_n; + litedramcore_master_p1_wrdata = litedramcore_csr_dfi_p1_wrdata; + litedramcore_master_p1_wrdata_en = litedramcore_csr_dfi_p1_wrdata_en; + litedramcore_master_p1_wrdata_mask = litedramcore_csr_dfi_p1_wrdata_mask; + litedramcore_master_p1_rddata_en = litedramcore_csr_dfi_p1_rddata_en; + litedramcore_csr_dfi_p1_rddata = litedramcore_master_p1_rddata; + litedramcore_csr_dfi_p1_rddata_valid = litedramcore_master_p1_rddata_valid; + end +end +assign litedramcore_csr_dfi_p0_cke = litedramcore_cke; +assign litedramcore_csr_dfi_p1_cke = litedramcore_cke; +assign litedramcore_csr_dfi_p0_odt = litedramcore_odt; +assign litedramcore_csr_dfi_p1_odt = litedramcore_odt; +assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n; +assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; +always @(*) begin + litedramcore_csr_dfi_p0_cas_n = 1'd1; + litedramcore_csr_dfi_p0_cs_n = 1'd1; + litedramcore_csr_dfi_p0_ras_n = 1'd1; + litedramcore_csr_dfi_p0_we_n = 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + if (litedramcore_phaseinjector0_cs_top) begin + litedramcore_csr_dfi_p0_cs_n = 2'd2; + end else begin + if (litedramcore_phaseinjector0_cs_bottom) begin + litedramcore_csr_dfi_p0_cs_n = 1'd1; + end else begin + litedramcore_csr_dfi_p0_cs_n = {1{(~litedramcore_phaseinjector0_cs)}}; + end + end + litedramcore_csr_dfi_p0_we_n = (~litedramcore_phaseinjector0_we); + litedramcore_csr_dfi_p0_cas_n = (~litedramcore_phaseinjector0_cas); + litedramcore_csr_dfi_p0_ras_n = (~litedramcore_phaseinjector0_ras); + end else begin + litedramcore_csr_dfi_p0_cs_n = {1{1'd1}}; + litedramcore_csr_dfi_p0_we_n = 1'd1; + litedramcore_csr_dfi_p0_cas_n = 1'd1; + litedramcore_csr_dfi_p0_ras_n = 1'd1; + end +end +assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage; +assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage; +assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_wren); +assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_rden); +assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; +assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; +always @(*) begin + litedramcore_csr_dfi_p1_cas_n = 1'd1; + litedramcore_csr_dfi_p1_cs_n = 1'd1; + litedramcore_csr_dfi_p1_ras_n = 1'd1; + litedramcore_csr_dfi_p1_we_n = 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + if (litedramcore_phaseinjector1_cs_top) begin + litedramcore_csr_dfi_p1_cs_n = 2'd2; + end else begin + if (litedramcore_phaseinjector1_cs_bottom) begin + litedramcore_csr_dfi_p1_cs_n = 1'd1; + end else begin + litedramcore_csr_dfi_p1_cs_n = {1{(~litedramcore_phaseinjector1_cs)}}; + end + end + litedramcore_csr_dfi_p1_we_n = (~litedramcore_phaseinjector1_we); + litedramcore_csr_dfi_p1_cas_n = (~litedramcore_phaseinjector1_cas); + litedramcore_csr_dfi_p1_ras_n = (~litedramcore_phaseinjector1_ras); + end else begin + litedramcore_csr_dfi_p1_cs_n = {1{1'd1}}; + litedramcore_csr_dfi_p1_we_n = 1'd1; + litedramcore_csr_dfi_p1_cas_n = 1'd1; + litedramcore_csr_dfi_p1_ras_n = 1'd1; + end +end +assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage; +assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage; +assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_wren); +assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_rden); +assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; +assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; +assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid; +assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready; +assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we; +assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr; +assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock; +assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready; +assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid; +assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid; +assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready; +assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we; +assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr; +assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock; +assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready; +assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid; +assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid; +assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready; +assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we; +assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr; +assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock; +assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready; +assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid; +assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid; +assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready; +assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we; +assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr; +assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock; +assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready; +assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid; +assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid; +assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready; +assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we; +assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr; +assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock; +assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready; +assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid; +assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid; +assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready; +assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we; +assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr; +assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock; +assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready; +assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid; +assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid; +assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready; +assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we; +assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr; +assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock; +assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready; +assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid; +assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid; +assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready; +assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we; +assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr; +assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock; +assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready; +assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid; +assign litedramcore_timer_wait = (~litedramcore_timer_done0); +assign litedramcore_postponer_req_i = litedramcore_timer_done0; +assign litedramcore_wants_refresh = litedramcore_postponer_req_o; +assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0; +assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done); +assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0); +assign litedramcore_timer_done0 = litedramcore_timer_done1; +assign litedramcore_timer_count0 = litedramcore_timer_count1; +assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0)); +assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0)); +assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); +assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; +assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; +always @(*) begin + litedramcore_cmd_last = 1'd0; + litedramcore_cmd_valid = 1'd0; + litedramcore_sequencer_start0 = 1'd0; + litedramcore_zqcs_executer_start = 1'd0; + refresher_next_state = 2'd0; + refresher_next_state = refresher_state; + case (refresher_state) + 1'd1: begin + litedramcore_cmd_valid = 1'd1; + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 = 1'd1; + refresher_next_state = 2'd2; + end + end + 2'd2: begin + litedramcore_cmd_valid = 1'd1; + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_zqcs_executer_start = 1'd1; + refresher_next_state = 2'd3; + end else begin + litedramcore_cmd_valid = 1'd0; + litedramcore_cmd_last = 1'd1; + refresher_next_state = 1'd0; + end + end + end + 2'd3: begin + litedramcore_cmd_valid = 1'd1; + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_valid = 1'd0; + litedramcore_cmd_last = 1'd1; + refresher_next_state = 1'd0; + end + end + default: begin + if (1'd1) begin + if (litedramcore_wants_refresh) begin + refresher_next_state = 1'd1; + end + end + end + endcase +end +assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid; +assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready; +assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we; +assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr; +assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid; +assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready; +assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first; +assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last; +assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we; +assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr; +assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); +assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid); +assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[21:7]); +assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; +always @(*) begin + litedramcore_bankmachine0_cmd_payload_a = 15'd0; + if (litedramcore_bankmachine0_row_col_n_addr_sel) begin + litedramcore_bankmachine0_cmd_payload_a = litedramcore_bankmachine0_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine0_cmd_payload_a = ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); +assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); +assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); +always @(*) begin + litedramcore_bankmachine0_auto_precharge = 1'd0; + if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin + if ((litedramcore_bankmachine0_source_payload_addr[21:7] != litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine0_auto_precharge = (litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we}; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable; +assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid; +assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first; +assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last; +assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we; +assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr; +assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable; +assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first; +assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last; +assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we; +assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr; +assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready; +always @(*) begin + litedramcore_bankmachine0_wrport_adr = 3'd0; + if (litedramcore_bankmachine0_replace) begin + litedramcore_bankmachine0_wrport_adr = (litedramcore_bankmachine0_produce - 1'd1); + end else begin + litedramcore_bankmachine0_wrport_adr = litedramcore_bankmachine0_produce; + end +end +assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din; +assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace)); +assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re); +assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume; +assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r; +assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 4'd8); +assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0); +assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready); +assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid; +assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready; +assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first; +assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last; +assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we; +assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr; +assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid; +assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready; +assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first; +assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last; +assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we; +assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr; +always @(*) begin + bankmachine0_next_state = 3'd0; + litedramcore_bankmachine0_cmd_payload_cas = 1'd0; + litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; + litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; + litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine0_cmd_payload_ras = 1'd0; + litedramcore_bankmachine0_cmd_payload_we = 1'd0; + litedramcore_bankmachine0_cmd_valid = 1'd0; + litedramcore_bankmachine0_refresh_gnt = 1'd0; + litedramcore_bankmachine0_req_rdata_valid = 1'd0; + litedramcore_bankmachine0_req_wdata_ready = 1'd0; + litedramcore_bankmachine0_row_close = 1'd0; + litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine0_row_open = 1'd0; + bankmachine0_next_state = bankmachine0_state; + case (bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_valid = 1'd1; + if (litedramcore_bankmachine0_cmd_ready) begin + bankmachine0_next_state = 3'd5; + end + litedramcore_bankmachine0_cmd_payload_ras = 1'd1; + litedramcore_bankmachine0_cmd_payload_we = 1'd1; + litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; + end + litedramcore_bankmachine0_row_close = 1'd1; + end + 2'd2: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + bankmachine0_next_state = 3'd5; + end + litedramcore_bankmachine0_row_close = 1'd1; + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1; + litedramcore_bankmachine0_row_open = 1'd1; + litedramcore_bankmachine0_cmd_valid = 1'd1; + litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; + if (litedramcore_bankmachine0_cmd_ready) begin + bankmachine0_next_state = 3'd6; + end + litedramcore_bankmachine0_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + if (litedramcore_bankmachine0_twtpcon_ready) begin + litedramcore_bankmachine0_refresh_gnt = 1'd1; + end + litedramcore_bankmachine0_row_close = 1'd1; + litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; + if ((~litedramcore_bankmachine0_refresh_req)) begin + bankmachine0_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine0_next_state = 2'd3; + end + 3'd6: begin + bankmachine0_next_state = 1'd0; + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + bankmachine0_next_state = 3'd4; + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_valid = 1'd1; + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready = litedramcore_bankmachine0_cmd_ready; + litedramcore_bankmachine0_cmd_payload_is_write = 1'd1; + litedramcore_bankmachine0_cmd_payload_we = 1'd1; + end else begin + litedramcore_bankmachine0_req_rdata_valid = litedramcore_bankmachine0_cmd_ready; + litedramcore_bankmachine0_cmd_payload_is_read = 1'd1; + end + litedramcore_bankmachine0_cmd_payload_cas = 1'd1; + if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin + bankmachine0_next_state = 2'd2; + end + end else begin + bankmachine0_next_state = 1'd1; + end + end else begin + bankmachine0_next_state = 2'd3; + end + end + end + end + endcase +end +assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; +assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; +assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; +assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr; +assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid; +assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready; +assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first; +assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last; +assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we; +assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr; +assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); +assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid); +assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[21:7]); +assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; +always @(*) begin + litedramcore_bankmachine1_cmd_payload_a = 15'd0; + if (litedramcore_bankmachine1_row_col_n_addr_sel) begin + litedramcore_bankmachine1_cmd_payload_a = litedramcore_bankmachine1_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine1_cmd_payload_a = ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); +assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); +assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); +always @(*) begin + litedramcore_bankmachine1_auto_precharge = 1'd0; + if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin + if ((litedramcore_bankmachine1_source_payload_addr[21:7] != litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine1_auto_precharge = (litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we}; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable; +assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid; +assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first; +assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last; +assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we; +assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr; +assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable; +assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first; +assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last; +assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we; +assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr; +assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready; +always @(*) begin + litedramcore_bankmachine1_wrport_adr = 3'd0; + if (litedramcore_bankmachine1_replace) begin + litedramcore_bankmachine1_wrport_adr = (litedramcore_bankmachine1_produce - 1'd1); + end else begin + litedramcore_bankmachine1_wrport_adr = litedramcore_bankmachine1_produce; + end +end +assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din; +assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace)); +assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re); +assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume; +assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r; +assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 4'd8); +assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0); +assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready); +assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid; +assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready; +assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first; +assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last; +assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we; +assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr; +assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid; +assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready; +assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first; +assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last; +assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we; +assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr; +always @(*) begin + bankmachine1_next_state = 3'd0; + litedramcore_bankmachine1_cmd_payload_cas = 1'd0; + litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; + litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; + litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine1_cmd_payload_ras = 1'd0; + litedramcore_bankmachine1_cmd_payload_we = 1'd0; + litedramcore_bankmachine1_cmd_valid = 1'd0; + litedramcore_bankmachine1_refresh_gnt = 1'd0; + litedramcore_bankmachine1_req_rdata_valid = 1'd0; + litedramcore_bankmachine1_req_wdata_ready = 1'd0; + litedramcore_bankmachine1_row_close = 1'd0; + litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine1_row_open = 1'd0; + bankmachine1_next_state = bankmachine1_state; + case (bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid = 1'd1; + if (litedramcore_bankmachine1_cmd_ready) begin + bankmachine1_next_state = 3'd5; + end + litedramcore_bankmachine1_cmd_payload_ras = 1'd1; + litedramcore_bankmachine1_cmd_payload_we = 1'd1; + litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + end + litedramcore_bankmachine1_row_close = 1'd1; + end + 2'd2: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + bankmachine1_next_state = 3'd5; + end + litedramcore_bankmachine1_row_close = 1'd1; + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1; + litedramcore_bankmachine1_row_open = 1'd1; + litedramcore_bankmachine1_cmd_valid = 1'd1; + litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + if (litedramcore_bankmachine1_cmd_ready) begin + bankmachine1_next_state = 3'd6; + end + litedramcore_bankmachine1_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt = 1'd1; + end + litedramcore_bankmachine1_row_close = 1'd1; + litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + if ((~litedramcore_bankmachine1_refresh_req)) begin + bankmachine1_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine1_next_state = 2'd3; + end + 3'd6: begin + bankmachine1_next_state = 1'd0; + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + bankmachine1_next_state = 3'd4; + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid = 1'd1; + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready = litedramcore_bankmachine1_cmd_ready; + litedramcore_bankmachine1_cmd_payload_is_write = 1'd1; + litedramcore_bankmachine1_cmd_payload_we = 1'd1; + end else begin + litedramcore_bankmachine1_req_rdata_valid = litedramcore_bankmachine1_cmd_ready; + litedramcore_bankmachine1_cmd_payload_is_read = 1'd1; + end + litedramcore_bankmachine1_cmd_payload_cas = 1'd1; + if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin + bankmachine1_next_state = 2'd2; + end + end else begin + bankmachine1_next_state = 1'd1; + end + end else begin + bankmachine1_next_state = 2'd3; + end + end + end + end + endcase +end +assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid; +assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready; +assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we; +assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr; +assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid; +assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready; +assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first; +assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last; +assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we; +assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr; +assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); +assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid); +assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[21:7]); +assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; +always @(*) begin + litedramcore_bankmachine2_cmd_payload_a = 15'd0; + if (litedramcore_bankmachine2_row_col_n_addr_sel) begin + litedramcore_bankmachine2_cmd_payload_a = litedramcore_bankmachine2_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine2_cmd_payload_a = ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); +assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); +assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); +always @(*) begin + litedramcore_bankmachine2_auto_precharge = 1'd0; + if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin + if ((litedramcore_bankmachine2_source_payload_addr[21:7] != litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine2_auto_precharge = (litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we}; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable; +assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid; +assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first; +assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last; +assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we; +assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr; +assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable; +assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first; +assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last; +assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we; +assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr; +assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready; +always @(*) begin + litedramcore_bankmachine2_wrport_adr = 3'd0; + if (litedramcore_bankmachine2_replace) begin + litedramcore_bankmachine2_wrport_adr = (litedramcore_bankmachine2_produce - 1'd1); + end else begin + litedramcore_bankmachine2_wrport_adr = litedramcore_bankmachine2_produce; + end +end +assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din; +assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace)); +assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re); +assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume; +assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r; +assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 4'd8); +assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0); +assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready); +assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid; +assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready; +assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first; +assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last; +assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we; +assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr; +assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid; +assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready; +assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first; +assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last; +assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we; +assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr; +always @(*) begin + bankmachine2_next_state = 3'd0; + litedramcore_bankmachine2_cmd_payload_cas = 1'd0; + litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; + litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; + litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine2_cmd_payload_ras = 1'd0; + litedramcore_bankmachine2_cmd_payload_we = 1'd0; + litedramcore_bankmachine2_cmd_valid = 1'd0; + litedramcore_bankmachine2_refresh_gnt = 1'd0; + litedramcore_bankmachine2_req_rdata_valid = 1'd0; + litedramcore_bankmachine2_req_wdata_ready = 1'd0; + litedramcore_bankmachine2_row_close = 1'd0; + litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine2_row_open = 1'd0; + bankmachine2_next_state = bankmachine2_state; + case (bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_valid = 1'd1; + if (litedramcore_bankmachine2_cmd_ready) begin + bankmachine2_next_state = 3'd5; + end + litedramcore_bankmachine2_cmd_payload_ras = 1'd1; + litedramcore_bankmachine2_cmd_payload_we = 1'd1; + litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; + end + litedramcore_bankmachine2_row_close = 1'd1; + end + 2'd2: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + bankmachine2_next_state = 3'd5; + end + litedramcore_bankmachine2_row_close = 1'd1; + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1; + litedramcore_bankmachine2_row_open = 1'd1; + litedramcore_bankmachine2_cmd_valid = 1'd1; + litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; + if (litedramcore_bankmachine2_cmd_ready) begin + bankmachine2_next_state = 3'd6; + end + litedramcore_bankmachine2_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt = 1'd1; + end + litedramcore_bankmachine2_row_close = 1'd1; + litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; + if ((~litedramcore_bankmachine2_refresh_req)) begin + bankmachine2_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine2_next_state = 2'd3; + end + 3'd6: begin + bankmachine2_next_state = 1'd0; + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + bankmachine2_next_state = 3'd4; + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_valid = 1'd1; + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready = litedramcore_bankmachine2_cmd_ready; + litedramcore_bankmachine2_cmd_payload_is_write = 1'd1; + litedramcore_bankmachine2_cmd_payload_we = 1'd1; + end else begin + litedramcore_bankmachine2_req_rdata_valid = litedramcore_bankmachine2_cmd_ready; + litedramcore_bankmachine2_cmd_payload_is_read = 1'd1; + end + litedramcore_bankmachine2_cmd_payload_cas = 1'd1; + if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin + bankmachine2_next_state = 2'd2; + end + end else begin + bankmachine2_next_state = 1'd1; + end + end else begin + bankmachine2_next_state = 2'd3; + end + end + end + end + endcase +end +assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid; +assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready; +assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we; +assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr; +assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid; +assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready; +assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first; +assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last; +assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we; +assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr; +assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); +assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid); +assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[21:7]); +assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; +always @(*) begin + litedramcore_bankmachine3_cmd_payload_a = 15'd0; + if (litedramcore_bankmachine3_row_col_n_addr_sel) begin + litedramcore_bankmachine3_cmd_payload_a = litedramcore_bankmachine3_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine3_cmd_payload_a = ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); +assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); +assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); +always @(*) begin + litedramcore_bankmachine3_auto_precharge = 1'd0; + if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin + if ((litedramcore_bankmachine3_source_payload_addr[21:7] != litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine3_auto_precharge = (litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we}; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable; +assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid; +assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first; +assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last; +assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we; +assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr; +assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable; +assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first; +assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last; +assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we; +assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr; +assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready; +always @(*) begin + litedramcore_bankmachine3_wrport_adr = 3'd0; + if (litedramcore_bankmachine3_replace) begin + litedramcore_bankmachine3_wrport_adr = (litedramcore_bankmachine3_produce - 1'd1); + end else begin + litedramcore_bankmachine3_wrport_adr = litedramcore_bankmachine3_produce; + end +end +assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din; +assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace)); +assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re); +assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume; +assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r; +assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 4'd8); +assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0); +assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready); +assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid; +assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready; +assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first; +assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last; +assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we; +assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr; +assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid; +assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready; +assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first; +assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last; +assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we; +assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr; +always @(*) begin + bankmachine3_next_state = 3'd0; + litedramcore_bankmachine3_cmd_payload_cas = 1'd0; + litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; + litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; + litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine3_cmd_payload_ras = 1'd0; + litedramcore_bankmachine3_cmd_payload_we = 1'd0; + litedramcore_bankmachine3_cmd_valid = 1'd0; + litedramcore_bankmachine3_refresh_gnt = 1'd0; + litedramcore_bankmachine3_req_rdata_valid = 1'd0; + litedramcore_bankmachine3_req_wdata_ready = 1'd0; + litedramcore_bankmachine3_row_close = 1'd0; + litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine3_row_open = 1'd0; + bankmachine3_next_state = bankmachine3_state; + case (bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid = 1'd1; + if (litedramcore_bankmachine3_cmd_ready) begin + bankmachine3_next_state = 3'd5; + end + litedramcore_bankmachine3_cmd_payload_ras = 1'd1; + litedramcore_bankmachine3_cmd_payload_we = 1'd1; + litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + end + litedramcore_bankmachine3_row_close = 1'd1; + end + 2'd2: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + bankmachine3_next_state = 3'd5; + end + litedramcore_bankmachine3_row_close = 1'd1; + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel = 1'd1; + litedramcore_bankmachine3_row_open = 1'd1; + litedramcore_bankmachine3_cmd_valid = 1'd1; + litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + if (litedramcore_bankmachine3_cmd_ready) begin + bankmachine3_next_state = 3'd6; + end + litedramcore_bankmachine3_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt = 1'd1; + end + litedramcore_bankmachine3_row_close = 1'd1; + litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + if ((~litedramcore_bankmachine3_refresh_req)) begin + bankmachine3_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine3_next_state = 2'd3; + end + 3'd6: begin + bankmachine3_next_state = 1'd0; + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + bankmachine3_next_state = 3'd4; + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_valid = 1'd1; + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready = litedramcore_bankmachine3_cmd_ready; + litedramcore_bankmachine3_cmd_payload_is_write = 1'd1; + litedramcore_bankmachine3_cmd_payload_we = 1'd1; + end else begin + litedramcore_bankmachine3_req_rdata_valid = litedramcore_bankmachine3_cmd_ready; + litedramcore_bankmachine3_cmd_payload_is_read = 1'd1; + end + litedramcore_bankmachine3_cmd_payload_cas = 1'd1; + if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin + bankmachine3_next_state = 2'd2; + end + end else begin + bankmachine3_next_state = 1'd1; + end + end else begin + bankmachine3_next_state = 2'd3; + end + end + end + end + endcase +end +assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid; +assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready; +assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we; +assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr; +assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid; +assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready; +assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first; +assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last; +assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we; +assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr; +assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); +assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid); +assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[21:7]); +assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; +always @(*) begin + litedramcore_bankmachine4_cmd_payload_a = 15'd0; + if (litedramcore_bankmachine4_row_col_n_addr_sel) begin + litedramcore_bankmachine4_cmd_payload_a = litedramcore_bankmachine4_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine4_cmd_payload_a = ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); +assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); +assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); +always @(*) begin + litedramcore_bankmachine4_auto_precharge = 1'd0; + if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin + if ((litedramcore_bankmachine4_source_payload_addr[21:7] != litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine4_auto_precharge = (litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we}; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable; +assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid; +assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first; +assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last; +assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we; +assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr; +assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable; +assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first; +assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last; +assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we; +assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr; +assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready; +always @(*) begin + litedramcore_bankmachine4_wrport_adr = 3'd0; + if (litedramcore_bankmachine4_replace) begin + litedramcore_bankmachine4_wrport_adr = (litedramcore_bankmachine4_produce - 1'd1); + end else begin + litedramcore_bankmachine4_wrport_adr = litedramcore_bankmachine4_produce; + end +end +assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din; +assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace)); +assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re); +assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume; +assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r; +assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 4'd8); +assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0); +assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready); +assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid; +assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready; +assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first; +assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last; +assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we; +assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr; +assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid; +assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready; +assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first; +assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last; +assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we; +assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr; +always @(*) begin + bankmachine4_next_state = 3'd0; + litedramcore_bankmachine4_cmd_payload_cas = 1'd0; + litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; + litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; + litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine4_cmd_payload_ras = 1'd0; + litedramcore_bankmachine4_cmd_payload_we = 1'd0; + litedramcore_bankmachine4_cmd_valid = 1'd0; + litedramcore_bankmachine4_refresh_gnt = 1'd0; + litedramcore_bankmachine4_req_rdata_valid = 1'd0; + litedramcore_bankmachine4_req_wdata_ready = 1'd0; + litedramcore_bankmachine4_row_close = 1'd0; + litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine4_row_open = 1'd0; + bankmachine4_next_state = bankmachine4_state; + case (bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid = 1'd1; + if (litedramcore_bankmachine4_cmd_ready) begin + bankmachine4_next_state = 3'd5; + end + litedramcore_bankmachine4_cmd_payload_ras = 1'd1; + litedramcore_bankmachine4_cmd_payload_we = 1'd1; + litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + end + litedramcore_bankmachine4_row_close = 1'd1; + end + 2'd2: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + bankmachine4_next_state = 3'd5; + end + litedramcore_bankmachine4_row_close = 1'd1; + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_col_n_addr_sel = 1'd1; + litedramcore_bankmachine4_row_open = 1'd1; + litedramcore_bankmachine4_cmd_valid = 1'd1; + litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + if (litedramcore_bankmachine4_cmd_ready) begin + bankmachine4_next_state = 3'd6; + end + litedramcore_bankmachine4_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt = 1'd1; + end + litedramcore_bankmachine4_row_close = 1'd1; + litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + if ((~litedramcore_bankmachine4_refresh_req)) begin + bankmachine4_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine4_next_state = 2'd3; + end + 3'd6: begin + bankmachine4_next_state = 1'd0; + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + bankmachine4_next_state = 3'd4; + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid = 1'd1; + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready = litedramcore_bankmachine4_cmd_ready; + litedramcore_bankmachine4_cmd_payload_is_write = 1'd1; + litedramcore_bankmachine4_cmd_payload_we = 1'd1; + end else begin + litedramcore_bankmachine4_req_rdata_valid = litedramcore_bankmachine4_cmd_ready; + litedramcore_bankmachine4_cmd_payload_is_read = 1'd1; + end + litedramcore_bankmachine4_cmd_payload_cas = 1'd1; + if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin + bankmachine4_next_state = 2'd2; + end + end else begin + bankmachine4_next_state = 1'd1; + end + end else begin + bankmachine4_next_state = 2'd3; + end + end + end + end + endcase +end +assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid; +assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready; +assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we; +assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr; +assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid; +assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready; +assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first; +assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last; +assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we; +assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr; +assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); +assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid); +assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[21:7]); +assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; +always @(*) begin + litedramcore_bankmachine5_cmd_payload_a = 15'd0; + if (litedramcore_bankmachine5_row_col_n_addr_sel) begin + litedramcore_bankmachine5_cmd_payload_a = litedramcore_bankmachine5_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine5_cmd_payload_a = ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); +assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); +assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); +always @(*) begin + litedramcore_bankmachine5_auto_precharge = 1'd0; + if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin + if ((litedramcore_bankmachine5_source_payload_addr[21:7] != litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine5_auto_precharge = (litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we}; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable; +assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid; +assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first; +assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last; +assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we; +assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr; +assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable; +assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first; +assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last; +assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we; +assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr; +assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready; +always @(*) begin + litedramcore_bankmachine5_wrport_adr = 3'd0; + if (litedramcore_bankmachine5_replace) begin + litedramcore_bankmachine5_wrport_adr = (litedramcore_bankmachine5_produce - 1'd1); + end else begin + litedramcore_bankmachine5_wrport_adr = litedramcore_bankmachine5_produce; + end +end +assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din; +assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace)); +assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re); +assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume; +assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r; +assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 4'd8); +assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0); +assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready); +assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid; +assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready; +assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first; +assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last; +assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we; +assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr; +assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid; +assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready; +assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first; +assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last; +assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we; +assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr; +always @(*) begin + bankmachine5_next_state = 3'd0; + litedramcore_bankmachine5_cmd_payload_cas = 1'd0; + litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; + litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; + litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine5_cmd_payload_ras = 1'd0; + litedramcore_bankmachine5_cmd_payload_we = 1'd0; + litedramcore_bankmachine5_cmd_valid = 1'd0; + litedramcore_bankmachine5_refresh_gnt = 1'd0; + litedramcore_bankmachine5_req_rdata_valid = 1'd0; + litedramcore_bankmachine5_req_wdata_ready = 1'd0; + litedramcore_bankmachine5_row_close = 1'd0; + litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine5_row_open = 1'd0; + bankmachine5_next_state = bankmachine5_state; + case (bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid = 1'd1; + if (litedramcore_bankmachine5_cmd_ready) begin + bankmachine5_next_state = 3'd5; + end + litedramcore_bankmachine5_cmd_payload_ras = 1'd1; + litedramcore_bankmachine5_cmd_payload_we = 1'd1; + litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + end + litedramcore_bankmachine5_row_close = 1'd1; + end + 2'd2: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + bankmachine5_next_state = 3'd5; + end + litedramcore_bankmachine5_row_close = 1'd1; + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_col_n_addr_sel = 1'd1; + litedramcore_bankmachine5_row_open = 1'd1; + litedramcore_bankmachine5_cmd_valid = 1'd1; + litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + if (litedramcore_bankmachine5_cmd_ready) begin + bankmachine5_next_state = 3'd6; + end + litedramcore_bankmachine5_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt = 1'd1; + end + litedramcore_bankmachine5_row_close = 1'd1; + litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + if ((~litedramcore_bankmachine5_refresh_req)) begin + bankmachine5_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine5_next_state = 2'd3; + end + 3'd6: begin + bankmachine5_next_state = 1'd0; + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + bankmachine5_next_state = 3'd4; + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid = 1'd1; + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready = litedramcore_bankmachine5_cmd_ready; + litedramcore_bankmachine5_cmd_payload_is_write = 1'd1; + litedramcore_bankmachine5_cmd_payload_we = 1'd1; + end else begin + litedramcore_bankmachine5_req_rdata_valid = litedramcore_bankmachine5_cmd_ready; + litedramcore_bankmachine5_cmd_payload_is_read = 1'd1; + end + litedramcore_bankmachine5_cmd_payload_cas = 1'd1; + if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin + bankmachine5_next_state = 2'd2; + end + end else begin + bankmachine5_next_state = 1'd1; + end + end else begin + bankmachine5_next_state = 2'd3; + end + end + end + end + endcase +end +assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid; +assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready; +assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we; +assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr; +assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid; +assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready; +assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first; +assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last; +assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we; +assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr; +assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); +assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid); +assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[21:7]); +assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; +always @(*) begin + litedramcore_bankmachine6_cmd_payload_a = 15'd0; + if (litedramcore_bankmachine6_row_col_n_addr_sel) begin + litedramcore_bankmachine6_cmd_payload_a = litedramcore_bankmachine6_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine6_cmd_payload_a = ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); +assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); +assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); +always @(*) begin + litedramcore_bankmachine6_auto_precharge = 1'd0; + if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin + if ((litedramcore_bankmachine6_source_payload_addr[21:7] != litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine6_auto_precharge = (litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we}; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable; +assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid; +assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first; +assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last; +assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we; +assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr; +assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable; +assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first; +assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last; +assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we; +assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr; +assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready; +always @(*) begin + litedramcore_bankmachine6_wrport_adr = 3'd0; + if (litedramcore_bankmachine6_replace) begin + litedramcore_bankmachine6_wrport_adr = (litedramcore_bankmachine6_produce - 1'd1); + end else begin + litedramcore_bankmachine6_wrport_adr = litedramcore_bankmachine6_produce; + end +end +assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din; +assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace)); +assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re); +assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume; +assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r; +assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 4'd8); +assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0); +assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready); +assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid; +assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready; +assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first; +assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last; +assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we; +assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr; +assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid; +assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready; +assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first; +assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last; +assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we; +assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr; +always @(*) begin + bankmachine6_next_state = 3'd0; + litedramcore_bankmachine6_cmd_payload_cas = 1'd0; + litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; + litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; + litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine6_cmd_payload_ras = 1'd0; + litedramcore_bankmachine6_cmd_payload_we = 1'd0; + litedramcore_bankmachine6_cmd_valid = 1'd0; + litedramcore_bankmachine6_refresh_gnt = 1'd0; + litedramcore_bankmachine6_req_rdata_valid = 1'd0; + litedramcore_bankmachine6_req_wdata_ready = 1'd0; + litedramcore_bankmachine6_row_close = 1'd0; + litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine6_row_open = 1'd0; + bankmachine6_next_state = bankmachine6_state; + case (bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_valid = 1'd1; + if (litedramcore_bankmachine6_cmd_ready) begin + bankmachine6_next_state = 3'd5; + end + litedramcore_bankmachine6_cmd_payload_ras = 1'd1; + litedramcore_bankmachine6_cmd_payload_we = 1'd1; + litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; + end + litedramcore_bankmachine6_row_close = 1'd1; + end + 2'd2: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + bankmachine6_next_state = 3'd5; + end + litedramcore_bankmachine6_row_close = 1'd1; + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel = 1'd1; + litedramcore_bankmachine6_row_open = 1'd1; + litedramcore_bankmachine6_cmd_valid = 1'd1; + litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; + if (litedramcore_bankmachine6_cmd_ready) begin + bankmachine6_next_state = 3'd6; + end + litedramcore_bankmachine6_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt = 1'd1; + end + litedramcore_bankmachine6_row_close = 1'd1; + litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; + if ((~litedramcore_bankmachine6_refresh_req)) begin + bankmachine6_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine6_next_state = 2'd3; + end + 3'd6: begin + bankmachine6_next_state = 1'd0; + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + bankmachine6_next_state = 3'd4; + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_valid = 1'd1; + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready = litedramcore_bankmachine6_cmd_ready; + litedramcore_bankmachine6_cmd_payload_is_write = 1'd1; + litedramcore_bankmachine6_cmd_payload_we = 1'd1; + end else begin + litedramcore_bankmachine6_req_rdata_valid = litedramcore_bankmachine6_cmd_ready; + litedramcore_bankmachine6_cmd_payload_is_read = 1'd1; + end + litedramcore_bankmachine6_cmd_payload_cas = 1'd1; + if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin + bankmachine6_next_state = 2'd2; + end + end else begin + bankmachine6_next_state = 1'd1; + end + end else begin + bankmachine6_next_state = 2'd3; + end + end + end + end + endcase +end +assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid; +assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready; +assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we; +assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr; +assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid; +assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready; +assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first; +assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last; +assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we; +assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr; +assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); +assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid); +assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[21:7]); +assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; +always @(*) begin + litedramcore_bankmachine7_cmd_payload_a = 15'd0; + if (litedramcore_bankmachine7_row_col_n_addr_sel) begin + litedramcore_bankmachine7_cmd_payload_a = litedramcore_bankmachine7_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine7_cmd_payload_a = ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); +assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); +assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); +always @(*) begin + litedramcore_bankmachine7_auto_precharge = 1'd0; + if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin + if ((litedramcore_bankmachine7_source_payload_addr[21:7] != litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine7_auto_precharge = (litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we}; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable; +assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid; +assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first; +assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last; +assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we; +assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr; +assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable; +assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first; +assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last; +assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we; +assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr; +assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready; +always @(*) begin + litedramcore_bankmachine7_wrport_adr = 3'd0; + if (litedramcore_bankmachine7_replace) begin + litedramcore_bankmachine7_wrport_adr = (litedramcore_bankmachine7_produce - 1'd1); + end else begin + litedramcore_bankmachine7_wrport_adr = litedramcore_bankmachine7_produce; + end +end +assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din; +assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace)); +assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re); +assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume; +assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r; +assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 4'd8); +assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0); +assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready); +assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid; +assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready; +assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first; +assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last; +assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we; +assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr; +assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid; +assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready; +assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first; +assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last; +assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we; +assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr; +always @(*) begin + bankmachine7_next_state = 3'd0; + litedramcore_bankmachine7_cmd_payload_cas = 1'd0; + litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; + litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; + litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine7_cmd_payload_ras = 1'd0; + litedramcore_bankmachine7_cmd_payload_we = 1'd0; + litedramcore_bankmachine7_cmd_valid = 1'd0; + litedramcore_bankmachine7_refresh_gnt = 1'd0; + litedramcore_bankmachine7_req_rdata_valid = 1'd0; + litedramcore_bankmachine7_req_wdata_ready = 1'd0; + litedramcore_bankmachine7_row_close = 1'd0; + litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine7_row_open = 1'd0; + bankmachine7_next_state = bankmachine7_state; + case (bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid = 1'd1; + if (litedramcore_bankmachine7_cmd_ready) begin + bankmachine7_next_state = 3'd5; + end + litedramcore_bankmachine7_cmd_payload_ras = 1'd1; + litedramcore_bankmachine7_cmd_payload_we = 1'd1; + litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + end + litedramcore_bankmachine7_row_close = 1'd1; + end + 2'd2: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + bankmachine7_next_state = 3'd5; + end + litedramcore_bankmachine7_row_close = 1'd1; + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel = 1'd1; + litedramcore_bankmachine7_row_open = 1'd1; + litedramcore_bankmachine7_cmd_valid = 1'd1; + litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + if (litedramcore_bankmachine7_cmd_ready) begin + bankmachine7_next_state = 3'd6; + end + litedramcore_bankmachine7_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt = 1'd1; + end + litedramcore_bankmachine7_row_close = 1'd1; + litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + if ((~litedramcore_bankmachine7_refresh_req)) begin + bankmachine7_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine7_next_state = 2'd3; + end + 3'd6: begin + bankmachine7_next_state = 1'd0; + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + bankmachine7_next_state = 3'd4; + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_valid = 1'd1; + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready = litedramcore_bankmachine7_cmd_ready; + litedramcore_bankmachine7_cmd_payload_is_write = 1'd1; + litedramcore_bankmachine7_cmd_payload_we = 1'd1; + end else begin + litedramcore_bankmachine7_req_rdata_valid = litedramcore_bankmachine7_cmd_ready; + litedramcore_bankmachine7_cmd_payload_is_read = 1'd1; + end + litedramcore_bankmachine7_cmd_payload_cas = 1'd1; + if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin + bankmachine7_next_state = 2'd2; + end + end else begin + bankmachine7_next_state = 1'd1; + end + end else begin + bankmachine7_next_state = 2'd3; + end + end + end + end + endcase +end +assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); +assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); +assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready); +assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read)); +assign litedramcore_cas_allowed = litedramcore_tccdcon_ready; +assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); +assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read)); +assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write)); +assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0); +assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0); +assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid; +assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt); +assign litedramcore_interface_rdata = {litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata}; +assign {litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +always @(*) begin + litedramcore_choose_cmd_valids = 8'd0; + litedramcore_choose_cmd_valids[0] = (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[1] = (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[2] = (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[3] = (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[4] = (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[5] = (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[6] = (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[7] = (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); +end +assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; +assign litedramcore_choose_cmd_cmd_valid = rhs_self8; +assign litedramcore_choose_cmd_cmd_payload_a = rhs_self9; +assign litedramcore_choose_cmd_cmd_payload_ba = rhs_self10; +assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_self11; +assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_self12; +assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_self13; +always @(*) begin + litedramcore_choose_cmd_cmd_payload_cas = 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_cas = t_self0; + end +end +always @(*) begin + litedramcore_choose_cmd_cmd_payload_ras = 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_ras = t_self1; + end +end +always @(*) begin + litedramcore_choose_cmd_cmd_payload_we = 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_we = t_self2; + end +end +assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); +always @(*) begin + litedramcore_choose_req_valids = 8'd0; + litedramcore_choose_req_valids[0] = (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[1] = (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[2] = (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[3] = (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[4] = (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[5] = (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[6] = (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[7] = (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); +end +assign litedramcore_choose_req_request = litedramcore_choose_req_valids; +assign litedramcore_choose_req_cmd_valid = rhs_self14; +assign litedramcore_choose_req_cmd_payload_a = rhs_self15; +assign litedramcore_choose_req_cmd_payload_ba = rhs_self16; +assign litedramcore_choose_req_cmd_payload_is_read = rhs_self17; +assign litedramcore_choose_req_cmd_payload_is_write = rhs_self18; +assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_self19; +always @(*) begin + litedramcore_choose_req_cmd_payload_cas = 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_cas = t_self3; + end +end +always @(*) begin + litedramcore_choose_req_cmd_payload_ras = 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_ras = t_self4; + end +end +always @(*) begin + litedramcore_choose_req_cmd_payload_we = 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_we = t_self5; + end +end +always @(*) begin + litedramcore_bankmachine0_cmd_ready = 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready = 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready = 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine1_cmd_ready = 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready = 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready = 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine2_cmd_ready = 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready = 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready = 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine3_cmd_ready = 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready = 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready = 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine4_cmd_ready = 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready = 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready = 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine5_cmd_ready = 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready = 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready = 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine6_cmd_ready = 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready = 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready = 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine7_cmd_ready = 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready = 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready = 1'd1; + end +end +assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); +assign litedramcore_dfi_p0_reset_n = 1'd1; +assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}}; +assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}}; +assign litedramcore_dfi_p1_reset_n = 1'd1; +assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}}; +assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}}; +assign litedramcore_tfawcon_count = (((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]); +always @(*) begin + litedramcore_choose_cmd_cmd_ready = 1'd0; + litedramcore_choose_cmd_want_activates = 1'd0; + litedramcore_choose_req_cmd_ready = 1'd0; + litedramcore_choose_req_want_reads = 1'd0; + litedramcore_choose_req_want_writes = 1'd0; + litedramcore_cmd_ready = 1'd0; + litedramcore_en0 = 1'd0; + litedramcore_en1 = 1'd0; + litedramcore_steerer_sel0 = 2'd0; + litedramcore_steerer_sel1 = 2'd0; + multiplexer_next_state = 4'd0; + multiplexer_next_state = multiplexer_state; + case (multiplexer_state) + 1'd1: begin + litedramcore_en1 = 1'd1; + litedramcore_choose_req_want_writes = 1'd1; + if (1'd0) begin + litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed; + litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed; + end + litedramcore_steerer_sel0 = 1'd0; + if (1'd0) begin + litedramcore_steerer_sel0 = 2'd2; + end + if (1'd1) begin + litedramcore_steerer_sel0 = 1'd1; + end + litedramcore_steerer_sel1 = 1'd0; + if (1'd1) begin + litedramcore_steerer_sel1 = 2'd2; + end + if (1'd0) begin + litedramcore_steerer_sel1 = 1'd1; + end + if (litedramcore_read_available) begin + if (((~litedramcore_write_available) | litedramcore_max_time1)) begin + multiplexer_next_state = 2'd3; + end + end + if (litedramcore_go_to_refresh) begin + multiplexer_next_state = 2'd2; + end + end + 2'd2: begin + litedramcore_steerer_sel0 = 2'd3; + litedramcore_cmd_ready = 1'd1; + if (litedramcore_cmd_last) begin + multiplexer_next_state = 1'd0; + end + end + 2'd3: begin + if (litedramcore_twtrcon_ready) begin + multiplexer_next_state = 1'd0; + end + end + 3'd4: begin + multiplexer_next_state = 3'd5; + end + 3'd5: begin + multiplexer_next_state = 3'd6; + end + 3'd6: begin + multiplexer_next_state = 3'd7; + end + 3'd7: begin + multiplexer_next_state = 4'd8; + end + 4'd8: begin + multiplexer_next_state = 4'd9; + end + 4'd9: begin + multiplexer_next_state = 4'd10; + end + 4'd10: begin + multiplexer_next_state = 4'd11; + end + 4'd11: begin + multiplexer_next_state = 4'd12; + end + 4'd12: begin + multiplexer_next_state = 4'd13; + end + 4'd13: begin + multiplexer_next_state = 4'd14; + end + 4'd14: begin + multiplexer_next_state = 4'd15; + end + 4'd15: begin + multiplexer_next_state = 1'd1; + end + default: begin + litedramcore_en0 = 1'd1; + litedramcore_choose_req_want_reads = 1'd1; + if (1'd0) begin + litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed; + litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed; + end + litedramcore_steerer_sel0 = 1'd0; + if (1'd1) begin + litedramcore_steerer_sel0 = 2'd2; + end + if (1'd0) begin + litedramcore_steerer_sel0 = 1'd1; + end + litedramcore_steerer_sel1 = 1'd0; + if (1'd0) begin + litedramcore_steerer_sel1 = 2'd2; + end + if (1'd1) begin + litedramcore_steerer_sel1 = 1'd1; + end + if (litedramcore_write_available) begin + if (((~litedramcore_read_available) | litedramcore_max_time0)) begin + multiplexer_next_state = 3'd4; + end + end + if (litedramcore_go_to_refresh) begin + multiplexer_next_state = 2'd2; + end + end + endcase +end +assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); +assign litedramcore_interface_bank0_addr = rhs_self20; +assign litedramcore_interface_bank0_we = rhs_self21; +assign litedramcore_interface_bank0_valid = rhs_self22; +assign roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock)); +assign litedramcore_interface_bank1_addr = rhs_self23; +assign litedramcore_interface_bank1_we = rhs_self24; +assign litedramcore_interface_bank1_valid = rhs_self25; +assign roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock)); +assign litedramcore_interface_bank2_addr = rhs_self26; +assign litedramcore_interface_bank2_we = rhs_self27; +assign litedramcore_interface_bank2_valid = rhs_self28; +assign roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock)); +assign litedramcore_interface_bank3_addr = rhs_self29; +assign litedramcore_interface_bank3_we = rhs_self30; +assign litedramcore_interface_bank3_valid = rhs_self31; +assign roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock)); +assign litedramcore_interface_bank4_addr = rhs_self32; +assign litedramcore_interface_bank4_we = rhs_self33; +assign litedramcore_interface_bank4_valid = rhs_self34; +assign roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock)); +assign litedramcore_interface_bank5_addr = rhs_self35; +assign litedramcore_interface_bank5_we = rhs_self36; +assign litedramcore_interface_bank5_valid = rhs_self37; +assign roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock)); +assign litedramcore_interface_bank6_addr = rhs_self38; +assign litedramcore_interface_bank6_we = rhs_self39; +assign litedramcore_interface_bank6_valid = rhs_self40; +assign roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock)); +assign litedramcore_interface_bank7_addr = rhs_self41; +assign litedramcore_interface_bank7_we = rhs_self42; +assign litedramcore_interface_bank7_valid = rhs_self43; +assign user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready)); +assign user_port_wdata_ready = new_master_wdata_ready3; +assign user_port_rdata_valid = new_master_rdata_valid13; +always @(*) begin + litedramcore_interface_wdata = 128'd0; + litedramcore_interface_wdata_we = 16'd0; + case ({new_master_wdata_ready3}) + 1'd1: begin + litedramcore_interface_wdata = user_port_wdata_payload_data; + litedramcore_interface_wdata_we = user_port_wdata_payload_we; + end + default: begin + litedramcore_interface_wdata = 1'd0; + litedramcore_interface_wdata_we = 1'd0; + end + endcase +end +assign user_port_rdata_payload_data = litedramcore_interface_rdata; +assign roundrobin0_grant = 1'd0; +assign roundrobin1_grant = 1'd0; +assign roundrobin2_grant = 1'd0; +assign roundrobin3_grant = 1'd0; +assign roundrobin4_grant = 1'd0; +assign roundrobin5_grant = 1'd0; +assign roundrobin6_grant = 1'd0; +assign roundrobin7_grant = 1'd0; +always @(*) begin + csr_data_width = 1'd0; + csr_data_width = 1'd0; + if ((interface0_sel != 1'd0)) begin + csr_data_width = 1'd0; + end +end +always @(*) begin + interface0_ack = 1'd0; + interface0_dat_r = 32'd0; + interface1_adr_next_value2 = 14'd0; + interface1_adr_next_value_ce2 = 1'd0; + interface1_dat_w_next_value0 = 32'd0; + interface1_dat_w_next_value_ce0 = 1'd0; + interface1_re_next_value3 = 1'd0; + interface1_re_next_value_ce3 = 1'd0; + interface1_we_next_value4 = 1'd0; + interface1_we_next_value_ce4 = 1'd0; + next_state = 2'd0; + selected_r_next_value1 = 1'd0; + selected_r_next_value_ce1 = 1'd0; + next_state = state; + case (state) + 1'd1: begin + interface1_adr_next_value2 = 1'd0; + interface1_adr_next_value_ce2 = 1'd1; + interface1_re_next_value3 = 1'd0; + interface1_re_next_value_ce3 = 1'd1; + interface1_we_next_value4 = 1'd0; + interface1_we_next_value_ce4 = 1'd1; + next_state = 2'd2; + end + 2'd2: begin + interface0_ack = 1'd1; + interface0_dat_r = 1'd0; + case (selected_r) + 1'd0: begin + interface0_dat_r = interface1_dat_r; + end + endcase + next_state = 1'd0; + end + default: begin + interface1_dat_w_next_value0 = cases_self; + interface1_dat_w_next_value_ce0 = 1'd1; + if ((interface0_cyc & interface0_stb)) begin + selected_r_next_value1 = csr_data_width; + selected_r_next_value_ce1 = 1'd1; + interface1_adr_next_value2 = interface0_adr; + interface1_adr_next_value_ce2 = 1'd1; + interface1_re_next_value3 = ((~interface0_we) & (interface0_sel != 1'd0)); + interface1_re_next_value_ce3 = 1'd1; + interface1_we_next_value4 = (interface0_we & (interface0_sel != 1'd0)); + interface1_we_next_value_ce4 = 1'd1; + next_state = 1'd1; + end + end + endcase +end +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); +assign csrbank0_init_done_r = interface0_bank_bus_dat_w[0]; +always @(*) begin + csrbank0_init_done_re = 1'd0; + csrbank0_init_done_we = 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done_re = interface0_bank_bus_we; + csrbank0_init_done_we = interface0_bank_bus_re; + end +end +assign csrbank0_init_error_r = interface0_bank_bus_dat_w[0]; +always @(*) begin + csrbank0_init_error_re = 1'd0; + csrbank0_init_error_we = 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error_re = interface0_bank_bus_we; + csrbank0_init_error_we = interface0_bank_bus_re; + end +end +assign csrbank0_init_done_w = init_done_storage; +assign csrbank0_init_error_w = init_error_storage; +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); +assign csrbank1_dly_sel_r = interface1_bank_bus_dat_w[1:0]; +always @(*) begin + csrbank1_dly_sel_re = 1'd0; + csrbank1_dly_sel_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dly_sel_re = interface1_bank_bus_we; + csrbank1_dly_sel_we = interface1_bank_bus_re; + end +end +assign ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + ddrphy_rdly_dq_rst_re = 1'd0; + ddrphy_rdly_dq_rst_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + ddrphy_rdly_dq_rst_re = interface1_bank_bus_we; + ddrphy_rdly_dq_rst_we = interface1_bank_bus_re; + end +end +assign ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + ddrphy_rdly_dq_inc_re = 1'd0; + ddrphy_rdly_dq_inc_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + ddrphy_rdly_dq_inc_re = interface1_bank_bus_we; + ddrphy_rdly_dq_inc_we = interface1_bank_bus_re; + end +end +assign ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + ddrphy_rdly_dq_bitslip_rst_re = 1'd0; + ddrphy_rdly_dq_bitslip_rst_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + ddrphy_rdly_dq_bitslip_rst_re = interface1_bank_bus_we; + ddrphy_rdly_dq_bitslip_rst_we = interface1_bank_bus_re; + end +end +assign ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + ddrphy_rdly_dq_bitslip_re = 1'd0; + ddrphy_rdly_dq_bitslip_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + ddrphy_rdly_dq_bitslip_re = interface1_bank_bus_we; + ddrphy_rdly_dq_bitslip_we = interface1_bank_bus_re; + end +end +assign ddrphy_burstdet_clr_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + ddrphy_burstdet_clr_re = 1'd0; + ddrphy_burstdet_clr_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + ddrphy_burstdet_clr_re = interface1_bank_bus_we; + ddrphy_burstdet_clr_we = interface1_bank_bus_re; + end +end +assign csrbank1_burstdet_seen_r = interface1_bank_bus_dat_w[1:0]; +always @(*) begin + csrbank1_burstdet_seen_re = 1'd0; + csrbank1_burstdet_seen_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_burstdet_seen_re = interface1_bank_bus_we; + csrbank1_burstdet_seen_we = interface1_bank_bus_re; + end +end +assign csrbank1_dly_sel_w = ddrphy_dly_sel_storage; +assign csrbank1_burstdet_seen_w = ddrphy_burstdet_seen_status; +assign ddrphy_burstdet_seen_rd_stb = csrbank1_burstdet_seen_we; +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); +assign csrbank2_dfii_control_r = interface2_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank2_dfii_control_re = 1'd0; + csrbank2_dfii_control_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control_re = interface2_bank_bus_we; + csrbank2_dfii_control_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi0_command_r = interface2_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank2_dfii_pi0_command_re = 1'd0; + csrbank2_dfii_pi0_command_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command_re = interface2_bank_bus_we; + csrbank2_dfii_pi0_command_we = interface2_bank_bus_re; + end +end +assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; +always @(*) begin + litedramcore_phaseinjector0_command_issue_re = 1'd0; + litedramcore_phaseinjector0_command_issue_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_re = interface2_bank_bus_we; + litedramcore_phaseinjector0_command_issue_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi0_address_r = interface2_bank_bus_dat_w[14:0]; +always @(*) begin + csrbank2_dfii_pi0_address_re = 1'd0; + csrbank2_dfii_pi0_address_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address_re = interface2_bank_bus_we; + csrbank2_dfii_pi0_address_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi0_baddress_r = interface2_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank2_dfii_pi0_baddress_re = 1'd0; + csrbank2_dfii_pi0_baddress_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress_re = interface2_bank_bus_we; + csrbank2_dfii_pi0_baddress_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w; +always @(*) begin + csrbank2_dfii_pi0_wrdata1_re = 1'd0; + csrbank2_dfii_pi0_wrdata1_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata1_re = interface2_bank_bus_we; + csrbank2_dfii_pi0_wrdata1_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w; +always @(*) begin + csrbank2_dfii_pi0_wrdata0_re = 1'd0; + csrbank2_dfii_pi0_wrdata0_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_wrdata0_re = interface2_bank_bus_we; + csrbank2_dfii_pi0_wrdata0_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w; +always @(*) begin + csrbank2_dfii_pi0_rddata1_re = 1'd0; + csrbank2_dfii_pi0_rddata1_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi0_rddata1_re = interface2_bank_bus_we; + csrbank2_dfii_pi0_rddata1_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w; +always @(*) begin + csrbank2_dfii_pi0_rddata0_re = 1'd0; + csrbank2_dfii_pi0_rddata0_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + csrbank2_dfii_pi0_rddata0_re = interface2_bank_bus_we; + csrbank2_dfii_pi0_rddata0_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi1_command_r = interface2_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank2_dfii_pi1_command_re = 1'd0; + csrbank2_dfii_pi1_command_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_command_re = interface2_bank_bus_we; + csrbank2_dfii_pi1_command_we = interface2_bank_bus_re; + end +end +assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; +always @(*) begin + litedramcore_phaseinjector1_command_issue_re = 1'd0; + litedramcore_phaseinjector1_command_issue_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + litedramcore_phaseinjector1_command_issue_re = interface2_bank_bus_we; + litedramcore_phaseinjector1_command_issue_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi1_address_r = interface2_bank_bus_dat_w[14:0]; +always @(*) begin + csrbank2_dfii_pi1_address_re = 1'd0; + csrbank2_dfii_pi1_address_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_address_re = interface2_bank_bus_we; + csrbank2_dfii_pi1_address_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi1_baddress_r = interface2_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank2_dfii_pi1_baddress_re = 1'd0; + csrbank2_dfii_pi1_baddress_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_baddress_re = interface2_bank_bus_we; + csrbank2_dfii_pi1_baddress_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w; +always @(*) begin + csrbank2_dfii_pi1_wrdata1_re = 1'd0; + csrbank2_dfii_pi1_wrdata1_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi1_wrdata1_re = interface2_bank_bus_we; + csrbank2_dfii_pi1_wrdata1_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w; +always @(*) begin + csrbank2_dfii_pi1_wrdata0_re = 1'd0; + csrbank2_dfii_pi1_wrdata0_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + csrbank2_dfii_pi1_wrdata0_re = interface2_bank_bus_we; + csrbank2_dfii_pi1_wrdata0_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w; +always @(*) begin + csrbank2_dfii_pi1_rddata1_re = 1'd0; + csrbank2_dfii_pi1_rddata1_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi1_rddata1_re = interface2_bank_bus_we; + csrbank2_dfii_pi1_rddata1_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w; +always @(*) begin + csrbank2_dfii_pi1_rddata0_re = 1'd0; + csrbank2_dfii_pi1_rddata0_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi1_rddata0_re = interface2_bank_bus_we; + csrbank2_dfii_pi1_rddata0_we = interface2_bank_bus_re; + end +end +assign litedramcore_sel = litedramcore_storage[0]; +assign litedramcore_cke = litedramcore_storage[1]; +assign litedramcore_odt = litedramcore_storage[2]; +assign litedramcore_reset_n = litedramcore_storage[3]; +assign csrbank2_dfii_control_w = litedramcore_storage; +assign litedramcore_phaseinjector0_cs = litedramcore_phaseinjector0_command_storage[0]; +assign litedramcore_phaseinjector0_we = litedramcore_phaseinjector0_command_storage[1]; +assign litedramcore_phaseinjector0_cas = litedramcore_phaseinjector0_command_storage[2]; +assign litedramcore_phaseinjector0_ras = litedramcore_phaseinjector0_command_storage[3]; +assign litedramcore_phaseinjector0_wren = litedramcore_phaseinjector0_command_storage[4]; +assign litedramcore_phaseinjector0_rden = litedramcore_phaseinjector0_command_storage[5]; +assign litedramcore_phaseinjector0_cs_top = litedramcore_phaseinjector0_command_storage[6]; +assign litedramcore_phaseinjector0_cs_bottom = litedramcore_phaseinjector0_command_storage[7]; +assign csrbank2_dfii_pi0_command_w = litedramcore_phaseinjector0_command_storage; +assign csrbank2_dfii_pi0_address_w = litedramcore_phaseinjector0_address_storage; +assign csrbank2_dfii_pi0_baddress_w = litedramcore_phaseinjector0_baddress_storage; +assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[63:32]; +assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_rddata_status[63:32]; +assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_rddata_status[31:0]; +assign litedramcore_phaseinjector0_rddata_rd_stb = csrbank2_dfii_pi0_rddata0_we; +assign litedramcore_phaseinjector1_cs = litedramcore_phaseinjector1_command_storage[0]; +assign litedramcore_phaseinjector1_we = litedramcore_phaseinjector1_command_storage[1]; +assign litedramcore_phaseinjector1_cas = litedramcore_phaseinjector1_command_storage[2]; +assign litedramcore_phaseinjector1_ras = litedramcore_phaseinjector1_command_storage[3]; +assign litedramcore_phaseinjector1_wren = litedramcore_phaseinjector1_command_storage[4]; +assign litedramcore_phaseinjector1_rden = litedramcore_phaseinjector1_command_storage[5]; +assign litedramcore_phaseinjector1_cs_top = litedramcore_phaseinjector1_command_storage[6]; +assign litedramcore_phaseinjector1_cs_bottom = litedramcore_phaseinjector1_command_storage[7]; +assign csrbank2_dfii_pi1_command_w = litedramcore_phaseinjector1_command_storage; +assign csrbank2_dfii_pi1_address_w = litedramcore_phaseinjector1_address_storage; +assign csrbank2_dfii_pi1_baddress_w = litedramcore_phaseinjector1_baddress_storage; +assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[63:32]; +assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_rddata_status[63:32]; +assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_rddata_status[31:0]; +assign litedramcore_phaseinjector1_rddata_rd_stb = csrbank2_dfii_pi1_rddata0_we; +assign adr = interface1_adr; +assign re = interface1_re; +assign we = interface1_we; +assign dat_w = interface1_dat_w; +assign interface1_dat_r = dat_r; +assign interface0_bank_bus_adr = adr; +assign interface1_bank_bus_adr = adr; +assign interface2_bank_bus_adr = adr; +assign interface0_bank_bus_re = re; +assign interface1_bank_bus_re = re; +assign interface2_bank_bus_re = re; +assign interface0_bank_bus_we = we; +assign interface1_bank_bus_we = we; +assign interface2_bank_bus_we = we; +assign interface0_bank_bus_dat_w = dat_w; +assign interface1_bank_bus_dat_w = dat_w; +assign interface2_bank_bus_dat_w = dat_w; +assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); +always @(*) begin + rhs_self0 = 30'd0; + case (grant) + default: begin + rhs_self0 = wb_bus_adr; + end + endcase +end +always @(*) begin + rhs_self1 = 32'd0; + case (grant) + default: begin + rhs_self1 = wb_bus_dat_w; + end + endcase +end +always @(*) begin + rhs_self2 = 4'd0; + case (grant) + default: begin + rhs_self2 = wb_bus_sel; + end + endcase +end +always @(*) begin + rhs_self3 = 1'd0; + case (grant) + default: begin + rhs_self3 = wb_bus_cyc; + end + endcase +end +always @(*) begin + rhs_self4 = 1'd0; + case (grant) + default: begin + rhs_self4 = wb_bus_stb; + end + endcase +end +always @(*) begin + rhs_self5 = 1'd0; + case (grant) + default: begin + rhs_self5 = wb_bus_we; + end + endcase +end +always @(*) begin + rhs_self6 = 3'd0; + case (grant) + default: begin + rhs_self6 = wb_bus_cti; + end + endcase +end +always @(*) begin + rhs_self7 = 2'd0; + case (grant) + default: begin + rhs_self7 = wb_bus_bte; + end + endcase +end +always @(*) begin + rhs_self8 = 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self8 = litedramcore_choose_cmd_valids[0]; + end + 1'd1: begin + rhs_self8 = litedramcore_choose_cmd_valids[1]; + end + 2'd2: begin + rhs_self8 = litedramcore_choose_cmd_valids[2]; + end + 2'd3: begin + rhs_self8 = litedramcore_choose_cmd_valids[3]; + end + 3'd4: begin + rhs_self8 = litedramcore_choose_cmd_valids[4]; + end + 3'd5: begin + rhs_self8 = litedramcore_choose_cmd_valids[5]; + end + 3'd6: begin + rhs_self8 = litedramcore_choose_cmd_valids[6]; + end + default: begin + rhs_self8 = litedramcore_choose_cmd_valids[7]; + end + endcase +end +always @(*) begin + rhs_self9 = 15'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self9 = litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_self9 = litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_self9 = litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_self9 = litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_self9 = litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_self9 = litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_self9 = litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_self9 = litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_self10 = 3'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self10 = litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_self10 = litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_self10 = litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_self10 = litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_self10 = litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_self10 = litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_self10 = litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_self10 = litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_self11 = 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self11 = litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_self11 = litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_self11 = litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_self11 = litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_self11 = litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_self11 = litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_self11 = litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_self11 = litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_self12 = 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self12 = litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_self12 = litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_self12 = litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_self12 = litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_self12 = litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_self12 = litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_self12 = litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_self12 = litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_self13 = 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self13 = litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_self13 = litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_self13 = litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_self13 = litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_self13 = litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_self13 = litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_self13 = litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_self13 = litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_self0 = 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_self0 = litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_self0 = litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_self0 = litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_self0 = litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_self0 = litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_self0 = litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_self0 = litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_self0 = litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_self1 = 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_self1 = litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_self1 = litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_self1 = litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_self1 = litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_self1 = litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_self1 = litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_self1 = litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_self1 = litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_self2 = 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_self2 = litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_self2 = litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_self2 = litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_self2 = litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_self2 = litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_self2 = litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_self2 = litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_self2 = litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self14 = 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_self14 = litedramcore_choose_req_valids[0]; + end + 1'd1: begin + rhs_self14 = litedramcore_choose_req_valids[1]; + end + 2'd2: begin + rhs_self14 = litedramcore_choose_req_valids[2]; + end + 2'd3: begin + rhs_self14 = litedramcore_choose_req_valids[3]; + end + 3'd4: begin + rhs_self14 = litedramcore_choose_req_valids[4]; + end + 3'd5: begin + rhs_self14 = litedramcore_choose_req_valids[5]; + end + 3'd6: begin + rhs_self14 = litedramcore_choose_req_valids[6]; + end + default: begin + rhs_self14 = litedramcore_choose_req_valids[7]; + end + endcase +end +always @(*) begin + rhs_self15 = 15'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_self15 = litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_self15 = litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_self15 = litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_self15 = litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_self15 = litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_self15 = litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_self15 = litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_self15 = litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_self16 = 3'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_self16 = litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_self16 = litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_self16 = litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_self16 = litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_self16 = litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_self16 = litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_self16 = litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_self16 = litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_self17 = 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_self17 = litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_self17 = litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_self17 = litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_self17 = litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_self17 = litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_self17 = litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_self17 = litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_self17 = litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_self18 = 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_self18 = litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_self18 = litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_self18 = litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_self18 = litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_self18 = litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_self18 = litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_self18 = litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_self18 = litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_self19 = 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_self19 = litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_self19 = litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_self19 = litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_self19 = litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_self19 = litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_self19 = litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_self19 = litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_self19 = litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_self3 = 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_self3 = litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_self3 = litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_self3 = litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_self3 = litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_self3 = litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_self3 = litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_self3 = litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_self3 = litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_self4 = 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_self4 = litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_self4 = litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_self4 = litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_self4 = litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_self4 = litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_self4 = litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_self4 = litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_self4 = litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_self5 = 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_self5 = litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_self5 = litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_self5 = litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_self5 = litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_self5 = litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_self5 = litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_self5 = litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_self5 = litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self20 = 22'd0; + case (roundrobin0_grant) + default: begin + rhs_self20 = {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self21 = 1'd0; + case (roundrobin0_grant) + default: begin + rhs_self21 = user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self22 = 1'd0; + case (roundrobin0_grant) + default: begin + rhs_self22 = (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self23 = 22'd0; + case (roundrobin1_grant) + default: begin + rhs_self23 = {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self24 = 1'd0; + case (roundrobin1_grant) + default: begin + rhs_self24 = user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self25 = 1'd0; + case (roundrobin1_grant) + default: begin + rhs_self25 = (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self26 = 22'd0; + case (roundrobin2_grant) + default: begin + rhs_self26 = {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self27 = 1'd0; + case (roundrobin2_grant) + default: begin + rhs_self27 = user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self28 = 1'd0; + case (roundrobin2_grant) + default: begin + rhs_self28 = (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self29 = 22'd0; + case (roundrobin3_grant) + default: begin + rhs_self29 = {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self30 = 1'd0; + case (roundrobin3_grant) + default: begin + rhs_self30 = user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self31 = 1'd0; + case (roundrobin3_grant) + default: begin + rhs_self31 = (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self32 = 22'd0; + case (roundrobin4_grant) + default: begin + rhs_self32 = {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self33 = 1'd0; + case (roundrobin4_grant) + default: begin + rhs_self33 = user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self34 = 1'd0; + case (roundrobin4_grant) + default: begin + rhs_self34 = (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self35 = 22'd0; + case (roundrobin5_grant) + default: begin + rhs_self35 = {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self36 = 1'd0; + case (roundrobin5_grant) + default: begin + rhs_self36 = user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self37 = 1'd0; + case (roundrobin5_grant) + default: begin + rhs_self37 = (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self38 = 22'd0; + case (roundrobin6_grant) + default: begin + rhs_self38 = {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self39 = 1'd0; + case (roundrobin6_grant) + default: begin + rhs_self39 = user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self40 = 1'd0; + case (roundrobin6_grant) + default: begin + rhs_self40 = (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self41 = 22'd0; + case (roundrobin7_grant) + default: begin + rhs_self41 = {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self42 = 1'd0; + case (roundrobin7_grant) + default: begin + rhs_self42 = user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self43 = 1'd0; + case (roundrobin7_grant) + default: begin + rhs_self43 = (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + cases_self = 32'd0; + case (csr_data_width) + default: begin + cases_self = interface0_dat_w; + end + endcase +end +always @(*) begin + self0 = 3'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + self0 = litedramcore_nop_ba; + end + 1'd1: begin + self0 = litedramcore_choose_cmd_cmd_payload_ba; + end + 2'd2: begin + self0 = litedramcore_choose_req_cmd_payload_ba; + end + default: begin + self0 = litedramcore_cmd_payload_ba; + end + endcase +end +always @(*) begin + self1 = 15'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + self1 = litedramcore_nop_a; + end + 1'd1: begin + self1 = litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + self1 = litedramcore_choose_req_cmd_payload_a; + end + default: begin + self1 = litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + self2 = 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + self2 = 1'd0; + end + 1'd1: begin + self2 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + self2 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + self2 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + self3 = 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + self3 = 1'd0; + end + 1'd1: begin + self3 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + self3 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + self3 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + self4 = 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + self4 = 1'd0; + end + 1'd1: begin + self4 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + self4 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + self4 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + self5 = 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + self5 = 1'd0; + end + 1'd1: begin + self5 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + self5 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + self5 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + self6 = 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + self6 = 1'd0; + end + 1'd1: begin + self6 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + self6 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + self6 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + self7 = 3'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + self7 = litedramcore_nop_ba; + end + 1'd1: begin + self7 = litedramcore_choose_cmd_cmd_payload_ba; + end + 2'd2: begin + self7 = litedramcore_choose_req_cmd_payload_ba; + end + default: begin + self7 = litedramcore_cmd_payload_ba; + end + endcase +end +always @(*) begin + self8 = 15'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + self8 = litedramcore_nop_a; + end + 1'd1: begin + self8 = litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + self8 = litedramcore_choose_req_cmd_payload_a; + end + default: begin + self8 = litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + self9 = 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + self9 = 1'd0; + end + 1'd1: begin + self9 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + self9 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + self9 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + self10 = 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + self10 = 1'd0; + end + 1'd1: begin + self10 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + self10 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + self10 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + self11 = 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + self11 = 1'd0; + end + 1'd1: begin + self11 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + self11 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + self11 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + self12 = 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + self12 = 1'd0; + end + 1'd1: begin + self12 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + self12 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + self12 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + self13 = 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + self13 = 1'd0; + end + 1'd1: begin + self13 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + self13 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + self13 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +assign ddrphy_lock1 = regs1; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge init_clk) begin + ddrphy_lock_d <= ddrphy_lock1; + if ((ddrphy_trigger == 4'd8)) begin + ddrphy_freeze <= 1'd1; + end + if ((ddrphy_trigger == 5'd16)) begin + ddrphy_stop1 <= 1'd1; + end + if ((ddrphy_trigger == 5'd24)) begin + ddrphy_reset1 <= 1'd1; + end + if ((ddrphy_trigger == 6'd32)) begin + ddrphy_reset1 <= 1'd0; + end + if ((ddrphy_trigger == 6'd40)) begin + ddrphy_stop1 <= 1'd0; + end + if ((ddrphy_trigger == 6'd48)) begin + ddrphy_freeze <= 1'd0; + end + if ((ddrphy_trigger == 6'd56)) begin + ddrphy_pause1 <= 1'd1; + end + if ((ddrphy_trigger == 7'd64)) begin + ddrphy_update <= 1'd1; + end + if ((ddrphy_trigger == 7'd72)) begin + ddrphy_update <= 1'd0; + end + if ((ddrphy_trigger == 7'd80)) begin + ddrphy_pause1 <= 1'd0; + end + if ((ddrphy_trigger == 7'd80)) begin + ddrphy_trigger <= 1'd0; + end else begin + if ((ddrphy_trigger != 1'd0)) begin + ddrphy_trigger <= (ddrphy_trigger + 1'd1); + end else begin + if (ddrphy_new_lock) begin + ddrphy_trigger <= 1'd1; + end + end + end + if (init_rst) begin + ddrphy_update <= 1'd0; + ddrphy_stop1 <= 1'd0; + ddrphy_freeze <= 1'd0; + ddrphy_pause1 <= 1'd0; + ddrphy_reset1 <= 1'd0; + ddrphy_lock_d <= 1'd0; + ddrphy_trigger <= 7'd0; + end + regs0 <= ddrphy_lock0; + regs1 <= regs0; +end + +always @(posedge por_clk) begin + if ((~crg_por_done)) begin + crg_por_count <= (crg_por_count - 1'd1); + end +end + +always @(posedge sys_clk) begin + user_enable <= (init_done_storage & (~init_error_storage)); + slaves <= master; + if (wait_1) begin + if ((~done)) begin + count <= (count - 1'd1); + end + end else begin + count <= 20'd1000000; + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_rst_re)) begin + ddrphy_rdly0 <= 1'd0; + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_inc_re)) begin + ddrphy_rdly0 <= (ddrphy_rdly0 + 1'd1); + end + ddrphy_burstdet_d0 <= ddrphy_burstdet0; + if (ddrphy_burstdet_clr_re) begin + ddrphy_burstdet_seen_status[0] <= 1'd0; + end + if ((ddrphy_burstdet0 & (~ddrphy_burstdet_d0))) begin + ddrphy_burstdet_seen_status[0] <= 1'd1; + end + ddrphy_dm_o_data_d0 <= ddrphy_dm_o_data0; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data0[3:0]; + end + 1'd1: begin + ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data_d0[7:4]; + end + endcase + ddrphy_dq_o_data_d0 <= ddrphy_dq_o_data0; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data0[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data_d0[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d0 <= ddrphy_bitslip0_o; + ddrphy_dq_o_data_d1 <= ddrphy_dq_o_data1; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data1[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data_d1[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d1 <= ddrphy_bitslip1_o; + ddrphy_dq_o_data_d2 <= ddrphy_dq_o_data2; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data2[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data_d2[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d2 <= ddrphy_bitslip2_o; + ddrphy_dq_o_data_d3 <= ddrphy_dq_o_data3; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data3[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data_d3[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d3 <= ddrphy_bitslip3_o; + ddrphy_dq_o_data_d4 <= ddrphy_dq_o_data4; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data4[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data_d4[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d4 <= ddrphy_bitslip4_o; + ddrphy_dq_o_data_d5 <= ddrphy_dq_o_data5; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data5[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data_d5[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d5 <= ddrphy_bitslip5_o; + ddrphy_dq_o_data_d6 <= ddrphy_dq_o_data6; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data6[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data_d6[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d6 <= ddrphy_bitslip6_o; + ddrphy_dq_o_data_d7 <= ddrphy_dq_o_data7; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data7[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data_d7[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d7 <= ddrphy_bitslip7_o; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_rst_re)) begin + ddrphy_rdly1 <= 1'd0; + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_inc_re)) begin + ddrphy_rdly1 <= (ddrphy_rdly1 + 1'd1); + end + ddrphy_burstdet_d1 <= ddrphy_burstdet1; + if (ddrphy_burstdet_clr_re) begin + ddrphy_burstdet_seen_status[1] <= 1'd0; + end + if ((ddrphy_burstdet1 & (~ddrphy_burstdet_d1))) begin + ddrphy_burstdet_seen_status[1] <= 1'd1; + end + ddrphy_dm_o_data_d1 <= ddrphy_dm_o_data1; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data1[3:0]; + end + 1'd1: begin + ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data_d1[7:4]; + end + endcase + ddrphy_dq_o_data_d8 <= ddrphy_dq_o_data8; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data8[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data_d8[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d8 <= ddrphy_bitslip8_o; + ddrphy_dq_o_data_d9 <= ddrphy_dq_o_data9; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data9[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data_d9[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d9 <= ddrphy_bitslip9_o; + ddrphy_dq_o_data_d10 <= ddrphy_dq_o_data10; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data10[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data_d10[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d10 <= ddrphy_bitslip10_o; + ddrphy_dq_o_data_d11 <= ddrphy_dq_o_data11; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data11[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data_d11[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d11 <= ddrphy_bitslip11_o; + ddrphy_dq_o_data_d12 <= ddrphy_dq_o_data12; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data12[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data_d12[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d12 <= ddrphy_bitslip12_o; + ddrphy_dq_o_data_d13 <= ddrphy_dq_o_data13; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data13[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data_d13[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d13 <= ddrphy_bitslip13_o; + ddrphy_dq_o_data_d14 <= ddrphy_dq_o_data14; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data14[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data_d14[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d14 <= ddrphy_bitslip14_o; + ddrphy_dq_o_data_d15 <= ddrphy_dq_o_data15; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data15[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data_d15[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d15 <= ddrphy_bitslip15_o; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip0_value <= (ddrphy_bitslip0_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip0_value <= 1'd0; + end + ddrphy_bitslip0_r <= {ddrphy_bitslip0_i, ddrphy_bitslip0_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip1_value <= (ddrphy_bitslip1_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip1_value <= 1'd0; + end + ddrphy_bitslip1_r <= {ddrphy_bitslip1_i, ddrphy_bitslip1_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip2_value <= (ddrphy_bitslip2_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip2_value <= 1'd0; + end + ddrphy_bitslip2_r <= {ddrphy_bitslip2_i, ddrphy_bitslip2_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip3_value <= (ddrphy_bitslip3_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip3_value <= 1'd0; + end + ddrphy_bitslip3_r <= {ddrphy_bitslip3_i, ddrphy_bitslip3_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip4_value <= (ddrphy_bitslip4_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip4_value <= 1'd0; + end + ddrphy_bitslip4_r <= {ddrphy_bitslip4_i, ddrphy_bitslip4_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip5_value <= (ddrphy_bitslip5_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip5_value <= 1'd0; + end + ddrphy_bitslip5_r <= {ddrphy_bitslip5_i, ddrphy_bitslip5_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip6_value <= (ddrphy_bitslip6_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip6_value <= 1'd0; + end + ddrphy_bitslip6_r <= {ddrphy_bitslip6_i, ddrphy_bitslip6_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip7_value <= (ddrphy_bitslip7_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip7_value <= 1'd0; + end + ddrphy_bitslip7_r <= {ddrphy_bitslip7_i, ddrphy_bitslip7_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip8_value <= (ddrphy_bitslip8_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip8_value <= 1'd0; + end + ddrphy_bitslip8_r <= {ddrphy_bitslip8_i, ddrphy_bitslip8_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip9_value <= (ddrphy_bitslip9_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip9_value <= 1'd0; + end + ddrphy_bitslip9_r <= {ddrphy_bitslip9_i, ddrphy_bitslip9_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip10_value <= (ddrphy_bitslip10_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip10_value <= 1'd0; + end + ddrphy_bitslip10_r <= {ddrphy_bitslip10_i, ddrphy_bitslip10_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip11_value <= (ddrphy_bitslip11_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip11_value <= 1'd0; + end + ddrphy_bitslip11_r <= {ddrphy_bitslip11_i, ddrphy_bitslip11_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip12_value <= (ddrphy_bitslip12_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip12_value <= 1'd0; + end + ddrphy_bitslip12_r <= {ddrphy_bitslip12_i, ddrphy_bitslip12_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip13_value <= (ddrphy_bitslip13_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip13_value <= 1'd0; + end + ddrphy_bitslip13_r <= {ddrphy_bitslip13_i, ddrphy_bitslip13_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip14_value <= (ddrphy_bitslip14_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip14_value <= 1'd0; + end + ddrphy_bitslip14_r <= {ddrphy_bitslip14_i, ddrphy_bitslip14_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip15_value <= (ddrphy_bitslip15_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip15_value <= 1'd0; + end + ddrphy_bitslip15_r <= {ddrphy_bitslip15_i, ddrphy_bitslip15_r[7:4]}; + ddrphy_rddata_en_tappeddelayline0 <= (ddrphy_dfi_p0_rddata_en | ddrphy_dfi_p1_rddata_en); + ddrphy_rddata_en_tappeddelayline1 <= ddrphy_rddata_en_tappeddelayline0; + ddrphy_rddata_en_tappeddelayline2 <= ddrphy_rddata_en_tappeddelayline1; + ddrphy_rddata_en_tappeddelayline3 <= ddrphy_rddata_en_tappeddelayline2; + ddrphy_rddata_en_tappeddelayline4 <= ddrphy_rddata_en_tappeddelayline3; + ddrphy_rddata_en_tappeddelayline5 <= ddrphy_rddata_en_tappeddelayline4; + ddrphy_rddata_en_tappeddelayline6 <= ddrphy_rddata_en_tappeddelayline5; + ddrphy_rddata_en_tappeddelayline7 <= ddrphy_rddata_en_tappeddelayline6; + ddrphy_rddata_en_tappeddelayline8 <= ddrphy_rddata_en_tappeddelayline7; + ddrphy_rddata_en_tappeddelayline9 <= ddrphy_rddata_en_tappeddelayline8; + ddrphy_rddata_en_tappeddelayline10 <= ddrphy_rddata_en_tappeddelayline9; + ddrphy_rddata_en_tappeddelayline11 <= ddrphy_rddata_en_tappeddelayline10; + ddrphy_rddata_en_tappeddelayline12 <= ddrphy_rddata_en_tappeddelayline11; + ddrphy_wrdata_en_tappeddelayline0 <= (ddrphy_dfi_p0_wrdata_en | ddrphy_dfi_p1_wrdata_en); + ddrphy_wrdata_en_tappeddelayline1 <= ddrphy_wrdata_en_tappeddelayline0; + ddrphy_wrdata_en_tappeddelayline2 <= ddrphy_wrdata_en_tappeddelayline1; + ddrphy_wrdata_en_tappeddelayline3 <= ddrphy_wrdata_en_tappeddelayline2; + ddrphy_wrdata_en_tappeddelayline4 <= ddrphy_wrdata_en_tappeddelayline3; + ddrphy_wrdata_en_tappeddelayline5 <= ddrphy_wrdata_en_tappeddelayline4; + ddrphy_wrdata_en_tappeddelayline6 <= ddrphy_wrdata_en_tappeddelayline5; + if (litedramcore_csr_dfi_p0_rddata_valid) begin + litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; + end + if (litedramcore_csr_dfi_p1_rddata_valid) begin + litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; + end + if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin + litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); + end else begin + litedramcore_timer_count1 <= 10'd585; + end + litedramcore_postponer_req_o <= 1'd0; + if (litedramcore_postponer_req_i) begin + litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); + if ((litedramcore_postponer_count == 1'd0)) begin + litedramcore_postponer_count <= 1'd0; + litedramcore_postponer_req_o <= 1'd1; + end + end + if (litedramcore_sequencer_start0) begin + litedramcore_sequencer_count <= 1'd0; + end else begin + if (litedramcore_sequencer_done1) begin + if ((litedramcore_sequencer_count != 1'd0)) begin + litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); + end + end + end + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_trigger == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'h400; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_sequencer_trigger == 2'd2)) begin + litedramcore_cmd_payload_a <= 11'h400; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd1; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd0; + end + if ((litedramcore_sequencer_trigger == 7'd106)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd1; + end + if ((litedramcore_sequencer_trigger == 7'd106)) begin + litedramcore_sequencer_trigger <= 1'd0; + end else begin + if ((litedramcore_sequencer_trigger != 1'd0)) begin + litedramcore_sequencer_trigger <= (litedramcore_sequencer_trigger + 1'd1); + end else begin + if (litedramcore_sequencer_start1) begin + litedramcore_sequencer_trigger <= 1'd1; + end + end + end + if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin + litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); + end else begin + litedramcore_zqcs_timer_count1 <= 27'd74999999; + end + litedramcore_zqcs_executer_done <= 1'd0; + if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_trigger == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'h400; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_trigger == 2'd2)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_trigger == 6'd34)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_zqcs_executer_done <= 1'd1; + end + if ((litedramcore_zqcs_executer_trigger == 6'd34)) begin + litedramcore_zqcs_executer_trigger <= 1'd0; + end else begin + if ((litedramcore_zqcs_executer_trigger != 1'd0)) begin + litedramcore_zqcs_executer_trigger <= (litedramcore_zqcs_executer_trigger + 1'd1); + end else begin + if (litedramcore_zqcs_executer_start) begin + litedramcore_zqcs_executer_trigger <= 1'd1; + end + end + end + refresher_state <= refresher_next_state; + if (litedramcore_bankmachine0_row_close) begin + litedramcore_bankmachine0_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine0_row_open) begin + litedramcore_bankmachine0_row_opened <= 1'd1; + litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin + litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1); + end + if (litedramcore_bankmachine0_do_read) begin + litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1); + end + if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin + if ((~litedramcore_bankmachine0_do_read)) begin + litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine0_do_read) begin + litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1); + end + end + if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin + litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid; + litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first; + litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last; + litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we; + litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine0_twtpcon_valid) begin + litedramcore_bankmachine0_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_twtpcon_ready)) begin + litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trccon_valid) begin + litedramcore_bankmachine0_trccon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trccon_ready)) begin + litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); + if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trascon_valid) begin + litedramcore_bankmachine0_trascon_count <= 2'd3; + if (1'd0) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); + if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end + end + end + bankmachine0_state <= bankmachine0_next_state; + if (litedramcore_bankmachine1_row_close) begin + litedramcore_bankmachine1_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine1_row_open) begin + litedramcore_bankmachine1_row_opened <= 1'd1; + litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin + litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1); + end + if (litedramcore_bankmachine1_do_read) begin + litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1); + end + if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin + if ((~litedramcore_bankmachine1_do_read)) begin + litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine1_do_read) begin + litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1); + end + end + if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin + litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid; + litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first; + litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last; + litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we; + litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine1_twtpcon_valid) begin + litedramcore_bankmachine1_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_twtpcon_ready)) begin + litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trccon_valid) begin + litedramcore_bankmachine1_trccon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trccon_ready)) begin + litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); + if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trascon_valid) begin + litedramcore_bankmachine1_trascon_count <= 2'd3; + if (1'd0) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); + if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end + end + end + bankmachine1_state <= bankmachine1_next_state; + if (litedramcore_bankmachine2_row_close) begin + litedramcore_bankmachine2_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine2_row_open) begin + litedramcore_bankmachine2_row_opened <= 1'd1; + litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin + litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1); + end + if (litedramcore_bankmachine2_do_read) begin + litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1); + end + if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin + if ((~litedramcore_bankmachine2_do_read)) begin + litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine2_do_read) begin + litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1); + end + end + if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin + litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid; + litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first; + litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last; + litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we; + litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine2_twtpcon_valid) begin + litedramcore_bankmachine2_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_twtpcon_ready)) begin + litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trccon_valid) begin + litedramcore_bankmachine2_trccon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trccon_ready)) begin + litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); + if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trascon_valid) begin + litedramcore_bankmachine2_trascon_count <= 2'd3; + if (1'd0) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); + if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end + end + end + bankmachine2_state <= bankmachine2_next_state; + if (litedramcore_bankmachine3_row_close) begin + litedramcore_bankmachine3_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine3_row_open) begin + litedramcore_bankmachine3_row_opened <= 1'd1; + litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin + litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1); + end + if (litedramcore_bankmachine3_do_read) begin + litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1); + end + if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin + if ((~litedramcore_bankmachine3_do_read)) begin + litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine3_do_read) begin + litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1); + end + end + if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin + litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid; + litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first; + litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last; + litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we; + litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine3_twtpcon_valid) begin + litedramcore_bankmachine3_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_twtpcon_ready)) begin + litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trccon_valid) begin + litedramcore_bankmachine3_trccon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trccon_ready)) begin + litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); + if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trascon_valid) begin + litedramcore_bankmachine3_trascon_count <= 2'd3; + if (1'd0) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); + if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end + end + end + bankmachine3_state <= bankmachine3_next_state; + if (litedramcore_bankmachine4_row_close) begin + litedramcore_bankmachine4_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine4_row_open) begin + litedramcore_bankmachine4_row_opened <= 1'd1; + litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin + litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1); + end + if (litedramcore_bankmachine4_do_read) begin + litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1); + end + if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin + if ((~litedramcore_bankmachine4_do_read)) begin + litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine4_do_read) begin + litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1); + end + end + if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin + litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid; + litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first; + litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last; + litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we; + litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine4_twtpcon_valid) begin + litedramcore_bankmachine4_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_twtpcon_ready)) begin + litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trccon_valid) begin + litedramcore_bankmachine4_trccon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trccon_ready)) begin + litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); + if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trascon_valid) begin + litedramcore_bankmachine4_trascon_count <= 2'd3; + if (1'd0) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); + if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end + end + end + bankmachine4_state <= bankmachine4_next_state; + if (litedramcore_bankmachine5_row_close) begin + litedramcore_bankmachine5_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine5_row_open) begin + litedramcore_bankmachine5_row_opened <= 1'd1; + litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin + litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1); + end + if (litedramcore_bankmachine5_do_read) begin + litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1); + end + if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin + if ((~litedramcore_bankmachine5_do_read)) begin + litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine5_do_read) begin + litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1); + end + end + if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin + litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid; + litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first; + litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last; + litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we; + litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine5_twtpcon_valid) begin + litedramcore_bankmachine5_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_twtpcon_ready)) begin + litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trccon_valid) begin + litedramcore_bankmachine5_trccon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trccon_ready)) begin + litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); + if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trascon_valid) begin + litedramcore_bankmachine5_trascon_count <= 2'd3; + if (1'd0) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); + if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end + end + end + bankmachine5_state <= bankmachine5_next_state; + if (litedramcore_bankmachine6_row_close) begin + litedramcore_bankmachine6_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine6_row_open) begin + litedramcore_bankmachine6_row_opened <= 1'd1; + litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin + litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1); + end + if (litedramcore_bankmachine6_do_read) begin + litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1); + end + if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin + if ((~litedramcore_bankmachine6_do_read)) begin + litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine6_do_read) begin + litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1); + end + end + if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin + litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid; + litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first; + litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last; + litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we; + litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine6_twtpcon_valid) begin + litedramcore_bankmachine6_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_twtpcon_ready)) begin + litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trccon_valid) begin + litedramcore_bankmachine6_trccon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trccon_ready)) begin + litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); + if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trascon_valid) begin + litedramcore_bankmachine6_trascon_count <= 2'd3; + if (1'd0) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); + if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end + end + end + bankmachine6_state <= bankmachine6_next_state; + if (litedramcore_bankmachine7_row_close) begin + litedramcore_bankmachine7_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine7_row_open) begin + litedramcore_bankmachine7_row_opened <= 1'd1; + litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin + litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1); + end + if (litedramcore_bankmachine7_do_read) begin + litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1); + end + if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin + if ((~litedramcore_bankmachine7_do_read)) begin + litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine7_do_read) begin + litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1); + end + end + if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin + litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid; + litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first; + litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last; + litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we; + litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine7_twtpcon_valid) begin + litedramcore_bankmachine7_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_twtpcon_ready)) begin + litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trccon_valid) begin + litedramcore_bankmachine7_trccon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trccon_ready)) begin + litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); + if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trascon_valid) begin + litedramcore_bankmachine7_trascon_count <= 2'd3; + if (1'd0) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); + if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end + end + end + bankmachine7_state <= bankmachine7_next_state; + if ((~litedramcore_en0)) begin + litedramcore_time0 <= 5'd31; + end else begin + if ((~litedramcore_max_time0)) begin + litedramcore_time0 <= (litedramcore_time0 - 1'd1); + end + end + if ((~litedramcore_en1)) begin + litedramcore_time1 <= 4'd15; + end else begin + if ((~litedramcore_max_time1)) begin + litedramcore_time1 <= (litedramcore_time1 - 1'd1); + end + end + if (litedramcore_choose_cmd_ce) begin + case (litedramcore_choose_cmd_grant) + 1'd0: begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (litedramcore_choose_req_ce) begin + case (litedramcore_choose_req_grant) + 1'd0: begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + litedramcore_dfi_p0_cs_n <= 1'd0; + litedramcore_dfi_p0_bank <= self0; + litedramcore_dfi_p0_address <= self1; + litedramcore_dfi_p0_cas_n <= (~self2); + litedramcore_dfi_p0_ras_n <= (~self3); + litedramcore_dfi_p0_we_n <= (~self4); + litedramcore_dfi_p0_rddata_en <= self5; + litedramcore_dfi_p0_wrdata_en <= self6; + litedramcore_dfi_p1_cs_n <= 1'd0; + litedramcore_dfi_p1_bank <= self7; + litedramcore_dfi_p1_address <= self8; + litedramcore_dfi_p1_cas_n <= (~self9); + litedramcore_dfi_p1_ras_n <= (~self10); + litedramcore_dfi_p1_we_n <= (~self11); + litedramcore_dfi_p1_rddata_en <= self12; + litedramcore_dfi_p1_wrdata_en <= self13; + if (litedramcore_trrdcon_valid) begin + litedramcore_trrdcon_count <= 2'd2; + if (1'd0) begin + litedramcore_trrdcon_ready <= 1'd1; + end else begin + litedramcore_trrdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_trrdcon_ready)) begin + litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); + if ((litedramcore_trrdcon_count == 1'd1)) begin + litedramcore_trrdcon_ready <= 1'd1; + end + end + end + litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; + if ((litedramcore_tfawcon_count < 3'd4)) begin + if ((litedramcore_tfawcon_count == 2'd3)) begin + litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); + end else begin + litedramcore_tfawcon_ready <= 1'd1; + end + end + if (litedramcore_tccdcon_valid) begin + litedramcore_tccdcon_count <= 1'd1; + if (1'd0) begin + litedramcore_tccdcon_ready <= 1'd1; + end else begin + litedramcore_tccdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_tccdcon_ready)) begin + litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); + if ((litedramcore_tccdcon_count == 1'd1)) begin + litedramcore_tccdcon_ready <= 1'd1; + end + end + end + if (litedramcore_twtrcon_valid) begin + litedramcore_twtrcon_count <= 3'd6; + if (1'd0) begin + litedramcore_twtrcon_ready <= 1'd1; + end else begin + litedramcore_twtrcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_twtrcon_ready)) begin + litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); + if ((litedramcore_twtrcon_count == 1'd1)) begin + litedramcore_twtrcon_ready <= 1'd1; + end + end + end + multiplexer_state <= multiplexer_next_state; + new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); + new_master_wdata_ready1 <= new_master_wdata_ready0; + new_master_wdata_ready2 <= new_master_wdata_ready1; + new_master_wdata_ready3 <= new_master_wdata_ready2; + new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); + new_master_rdata_valid1 <= new_master_rdata_valid0; + new_master_rdata_valid2 <= new_master_rdata_valid1; + new_master_rdata_valid3 <= new_master_rdata_valid2; + new_master_rdata_valid4 <= new_master_rdata_valid3; + new_master_rdata_valid5 <= new_master_rdata_valid4; + new_master_rdata_valid6 <= new_master_rdata_valid5; + new_master_rdata_valid7 <= new_master_rdata_valid6; + new_master_rdata_valid8 <= new_master_rdata_valid7; + new_master_rdata_valid9 <= new_master_rdata_valid8; + new_master_rdata_valid10 <= new_master_rdata_valid9; + new_master_rdata_valid11 <= new_master_rdata_valid10; + new_master_rdata_valid12 <= new_master_rdata_valid11; + new_master_rdata_valid13 <= new_master_rdata_valid12; + state <= next_state; + if (interface1_dat_w_next_value_ce0) begin + interface1_dat_w <= interface1_dat_w_next_value0; + end + if (selected_r_next_value_ce1) begin + selected_r <= selected_r_next_value1; + end + if (interface1_adr_next_value_ce2) begin + interface1_adr <= interface1_adr_next_value2; + end + if (interface1_re_next_value_ce3) begin + interface1_re <= interface1_re_next_value3; + end + if (interface1_we_next_value_ce4) begin + interface1_we <= interface1_we_next_value4; + end + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) + 1'd0: begin + interface0_bank_bus_dat_r <= csrbank0_init_done_w; + end + 1'd1: begin + interface0_bank_bus_dat_r <= csrbank0_init_error_w; + end + endcase + end + if (csrbank0_init_done_re) begin + init_done_storage <= csrbank0_init_done_r; + end + init_done_wr_stb <= csrbank0_init_done_re; + if (csrbank0_init_error_re) begin + init_error_storage <= csrbank0_init_error_r; + end + init_error_wr_stb <= csrbank0_init_error_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= csrbank1_dly_sel_w; + end + 1'd1: begin + interface1_bank_bus_dat_r <= ddrphy_rdly_dq_rst_w; + end + 2'd2: begin + interface1_bank_bus_dat_r <= ddrphy_rdly_dq_inc_w; + end + 2'd3: begin + interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_rst_w; + end + 3'd4: begin + interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_w; + end + 3'd5: begin + interface1_bank_bus_dat_r <= ddrphy_burstdet_clr_w; + end + 3'd6: begin + interface1_bank_bus_dat_r <= csrbank1_burstdet_seen_w; + end + endcase + end + if (csrbank1_dly_sel_re) begin + ddrphy_dly_sel_storage <= csrbank1_dly_sel_r; + end + ddrphy_dly_sel_wr_stb <= csrbank1_dly_sel_re; + ddrphy_burstdet_seen_wr_stb <= csrbank1_burstdet_seen_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) + 1'd0: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_control_w; + end + 1'd1: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command_w; + end + 2'd2: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; + end + 2'd3: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address_w; + end + 3'd4: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress_w; + end + 3'd5: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; + end + 3'd6: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + end + 3'd7: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; + end + 4'd8: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; + end + 4'd9: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command_w; + end + 4'd10: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + end + 4'd11: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address_w; + end + 4'd12: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress_w; + end + 4'd13: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w; + end + 4'd14: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; + end + 4'd15: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w; + end + 5'd16: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w; + end + endcase + end + if (csrbank2_dfii_control_re) begin + litedramcore_storage <= csrbank2_dfii_control_r; + end + litedramcore_wr_stb <= csrbank2_dfii_control_re; + if (csrbank2_dfii_pi0_command_re) begin + litedramcore_phaseinjector0_command_storage <= csrbank2_dfii_pi0_command_r; + end + litedramcore_phaseinjector0_command_wr_stb <= csrbank2_dfii_pi0_command_re; + if (csrbank2_dfii_pi0_address_re) begin + litedramcore_phaseinjector0_address_storage <= csrbank2_dfii_pi0_address_r; + end + litedramcore_phaseinjector0_address_wr_stb <= csrbank2_dfii_pi0_address_re; + if (csrbank2_dfii_pi0_baddress_re) begin + litedramcore_phaseinjector0_baddress_storage <= csrbank2_dfii_pi0_baddress_r; + end + litedramcore_phaseinjector0_baddress_wr_stb <= csrbank2_dfii_pi0_baddress_re; + if (csrbank2_dfii_pi0_wrdata1_re) begin + litedramcore_phaseinjector0_wrdata_storage[63:32] <= csrbank2_dfii_pi0_wrdata1_r; + end + if (csrbank2_dfii_pi0_wrdata0_re) begin + litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; + end + litedramcore_phaseinjector0_wrdata_wr_stb <= csrbank2_dfii_pi0_wrdata0_re; + litedramcore_phaseinjector0_rddata_wr_stb <= csrbank2_dfii_pi0_rddata0_re; + if (csrbank2_dfii_pi1_command_re) begin + litedramcore_phaseinjector1_command_storage <= csrbank2_dfii_pi1_command_r; + end + litedramcore_phaseinjector1_command_wr_stb <= csrbank2_dfii_pi1_command_re; + if (csrbank2_dfii_pi1_address_re) begin + litedramcore_phaseinjector1_address_storage <= csrbank2_dfii_pi1_address_r; + end + litedramcore_phaseinjector1_address_wr_stb <= csrbank2_dfii_pi1_address_re; + if (csrbank2_dfii_pi1_baddress_re) begin + litedramcore_phaseinjector1_baddress_storage <= csrbank2_dfii_pi1_baddress_r; + end + litedramcore_phaseinjector1_baddress_wr_stb <= csrbank2_dfii_pi1_baddress_re; + if (csrbank2_dfii_pi1_wrdata1_re) begin + litedramcore_phaseinjector1_wrdata_storage[63:32] <= csrbank2_dfii_pi1_wrdata1_r; + end + if (csrbank2_dfii_pi1_wrdata0_re) begin + litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; + end + litedramcore_phaseinjector1_wrdata_wr_stb <= csrbank2_dfii_pi1_wrdata0_re; + litedramcore_phaseinjector1_rddata_wr_stb <= csrbank2_dfii_pi1_rddata0_re; + if (sys_rst) begin + ddrphy_dly_sel_storage <= 2'd0; + ddrphy_dly_sel_wr_stb <= 1'd0; + ddrphy_burstdet_seen_status <= 2'd0; + ddrphy_burstdet_seen_wr_stb <= 1'd0; + ddrphy_rdly0 <= 3'd0; + ddrphy_burstdet_d0 <= 1'd0; + ddrphy_dm_o_data_d0 <= 8'd0; + ddrphy_dm_o_data_muxed0 <= 4'd0; + ddrphy_dq_o_data_d0 <= 8'd0; + ddrphy_dq_o_data_muxed0 <= 4'd0; + ddrphy_bitslip0_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d0 <= 4'd0; + ddrphy_dq_o_data_d1 <= 8'd0; + ddrphy_dq_o_data_muxed1 <= 4'd0; + ddrphy_bitslip1_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d1 <= 4'd0; + ddrphy_dq_o_data_d2 <= 8'd0; + ddrphy_dq_o_data_muxed2 <= 4'd0; + ddrphy_bitslip2_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d2 <= 4'd0; + ddrphy_dq_o_data_d3 <= 8'd0; + ddrphy_dq_o_data_muxed3 <= 4'd0; + ddrphy_bitslip3_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d3 <= 4'd0; + ddrphy_dq_o_data_d4 <= 8'd0; + ddrphy_dq_o_data_muxed4 <= 4'd0; + ddrphy_bitslip4_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d4 <= 4'd0; + ddrphy_dq_o_data_d5 <= 8'd0; + ddrphy_dq_o_data_muxed5 <= 4'd0; + ddrphy_bitslip5_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d5 <= 4'd0; + ddrphy_dq_o_data_d6 <= 8'd0; + ddrphy_dq_o_data_muxed6 <= 4'd0; + ddrphy_bitslip6_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d6 <= 4'd0; + ddrphy_dq_o_data_d7 <= 8'd0; + ddrphy_dq_o_data_muxed7 <= 4'd0; + ddrphy_bitslip7_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d7 <= 4'd0; + ddrphy_rdly1 <= 3'd0; + ddrphy_burstdet_d1 <= 1'd0; + ddrphy_dm_o_data_d1 <= 8'd0; + ddrphy_dm_o_data_muxed1 <= 4'd0; + ddrphy_dq_o_data_d8 <= 8'd0; + ddrphy_dq_o_data_muxed8 <= 4'd0; + ddrphy_bitslip8_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d8 <= 4'd0; + ddrphy_dq_o_data_d9 <= 8'd0; + ddrphy_dq_o_data_muxed9 <= 4'd0; + ddrphy_bitslip9_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d9 <= 4'd0; + ddrphy_dq_o_data_d10 <= 8'd0; + ddrphy_dq_o_data_muxed10 <= 4'd0; + ddrphy_bitslip10_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d10 <= 4'd0; + ddrphy_dq_o_data_d11 <= 8'd0; + ddrphy_dq_o_data_muxed11 <= 4'd0; + ddrphy_bitslip11_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d11 <= 4'd0; + ddrphy_dq_o_data_d12 <= 8'd0; + ddrphy_dq_o_data_muxed12 <= 4'd0; + ddrphy_bitslip12_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d12 <= 4'd0; + ddrphy_dq_o_data_d13 <= 8'd0; + ddrphy_dq_o_data_muxed13 <= 4'd0; + ddrphy_bitslip13_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d13 <= 4'd0; + ddrphy_dq_o_data_d14 <= 8'd0; + ddrphy_dq_o_data_muxed14 <= 4'd0; + ddrphy_bitslip14_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d14 <= 4'd0; + ddrphy_dq_o_data_d15 <= 8'd0; + ddrphy_dq_o_data_muxed15 <= 4'd0; + ddrphy_bitslip15_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d15 <= 4'd0; + ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + ddrphy_rddata_en_tappeddelayline8 <= 1'd0; + ddrphy_rddata_en_tappeddelayline9 <= 1'd0; + ddrphy_rddata_en_tappeddelayline10 <= 1'd0; + ddrphy_rddata_en_tappeddelayline11 <= 1'd0; + ddrphy_rddata_en_tappeddelayline12 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline3 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline4 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline5 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline6 <= 1'd0; + litedramcore_storage <= 4'd1; + litedramcore_wr_stb <= 1'd0; + litedramcore_phaseinjector0_command_storage <= 8'd0; + litedramcore_phaseinjector0_command_wr_stb <= 1'd0; + litedramcore_phaseinjector0_address_wr_stb <= 1'd0; + litedramcore_phaseinjector0_baddress_wr_stb <= 1'd0; + litedramcore_phaseinjector0_wrdata_wr_stb <= 1'd0; + litedramcore_phaseinjector0_rddata_status <= 64'd0; + litedramcore_phaseinjector0_rddata_wr_stb <= 1'd0; + litedramcore_phaseinjector1_command_storage <= 8'd0; + litedramcore_phaseinjector1_command_wr_stb <= 1'd0; + litedramcore_phaseinjector1_address_wr_stb <= 1'd0; + litedramcore_phaseinjector1_baddress_wr_stb <= 1'd0; + litedramcore_phaseinjector1_wrdata_wr_stb <= 1'd0; + litedramcore_phaseinjector1_rddata_status <= 64'd0; + litedramcore_phaseinjector1_rddata_wr_stb <= 1'd0; + litedramcore_dfi_p0_address <= 15'd0; + litedramcore_dfi_p0_bank <= 3'd0; + litedramcore_dfi_p0_cas_n <= 1'd1; + litedramcore_dfi_p0_cs_n <= 1'd1; + litedramcore_dfi_p0_ras_n <= 1'd1; + litedramcore_dfi_p0_we_n <= 1'd1; + litedramcore_dfi_p0_wrdata_en <= 1'd0; + litedramcore_dfi_p0_rddata_en <= 1'd0; + litedramcore_dfi_p1_address <= 15'd0; + litedramcore_dfi_p1_bank <= 3'd0; + litedramcore_dfi_p1_cas_n <= 1'd1; + litedramcore_dfi_p1_cs_n <= 1'd1; + litedramcore_dfi_p1_ras_n <= 1'd1; + litedramcore_dfi_p1_we_n <= 1'd1; + litedramcore_dfi_p1_wrdata_en <= 1'd0; + litedramcore_dfi_p1_rddata_en <= 1'd0; + litedramcore_timer_count1 <= 10'd585; + litedramcore_postponer_req_o <= 1'd0; + litedramcore_postponer_count <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + litedramcore_sequencer_trigger <= 7'd0; + litedramcore_sequencer_count <= 1'd0; + litedramcore_zqcs_timer_count1 <= 27'd74999999; + litedramcore_zqcs_executer_done <= 1'd0; + litedramcore_zqcs_executer_trigger <= 6'd0; + litedramcore_bankmachine0_level <= 4'd0; + litedramcore_bankmachine0_produce <= 3'd0; + litedramcore_bankmachine0_consume <= 3'd0; + litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine0_row <= 15'd0; + litedramcore_bankmachine0_row_opened <= 1'd0; + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + litedramcore_bankmachine0_twtpcon_count <= 3'd0; + litedramcore_bankmachine0_trccon_ready <= 1'd0; + litedramcore_bankmachine0_trccon_count <= 3'd0; + litedramcore_bankmachine0_trascon_ready <= 1'd0; + litedramcore_bankmachine0_trascon_count <= 2'd0; + litedramcore_bankmachine1_level <= 4'd0; + litedramcore_bankmachine1_produce <= 3'd0; + litedramcore_bankmachine1_consume <= 3'd0; + litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine1_row <= 15'd0; + litedramcore_bankmachine1_row_opened <= 1'd0; + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + litedramcore_bankmachine1_twtpcon_count <= 3'd0; + litedramcore_bankmachine1_trccon_ready <= 1'd0; + litedramcore_bankmachine1_trccon_count <= 3'd0; + litedramcore_bankmachine1_trascon_ready <= 1'd0; + litedramcore_bankmachine1_trascon_count <= 2'd0; + litedramcore_bankmachine2_level <= 4'd0; + litedramcore_bankmachine2_produce <= 3'd0; + litedramcore_bankmachine2_consume <= 3'd0; + litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine2_row <= 15'd0; + litedramcore_bankmachine2_row_opened <= 1'd0; + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + litedramcore_bankmachine2_twtpcon_count <= 3'd0; + litedramcore_bankmachine2_trccon_ready <= 1'd0; + litedramcore_bankmachine2_trccon_count <= 3'd0; + litedramcore_bankmachine2_trascon_ready <= 1'd0; + litedramcore_bankmachine2_trascon_count <= 2'd0; + litedramcore_bankmachine3_level <= 4'd0; + litedramcore_bankmachine3_produce <= 3'd0; + litedramcore_bankmachine3_consume <= 3'd0; + litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine3_row <= 15'd0; + litedramcore_bankmachine3_row_opened <= 1'd0; + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + litedramcore_bankmachine3_twtpcon_count <= 3'd0; + litedramcore_bankmachine3_trccon_ready <= 1'd0; + litedramcore_bankmachine3_trccon_count <= 3'd0; + litedramcore_bankmachine3_trascon_ready <= 1'd0; + litedramcore_bankmachine3_trascon_count <= 2'd0; + litedramcore_bankmachine4_level <= 4'd0; + litedramcore_bankmachine4_produce <= 3'd0; + litedramcore_bankmachine4_consume <= 3'd0; + litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine4_row <= 15'd0; + litedramcore_bankmachine4_row_opened <= 1'd0; + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + litedramcore_bankmachine4_twtpcon_count <= 3'd0; + litedramcore_bankmachine4_trccon_ready <= 1'd0; + litedramcore_bankmachine4_trccon_count <= 3'd0; + litedramcore_bankmachine4_trascon_ready <= 1'd0; + litedramcore_bankmachine4_trascon_count <= 2'd0; + litedramcore_bankmachine5_level <= 4'd0; + litedramcore_bankmachine5_produce <= 3'd0; + litedramcore_bankmachine5_consume <= 3'd0; + litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine5_row <= 15'd0; + litedramcore_bankmachine5_row_opened <= 1'd0; + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + litedramcore_bankmachine5_twtpcon_count <= 3'd0; + litedramcore_bankmachine5_trccon_ready <= 1'd0; + litedramcore_bankmachine5_trccon_count <= 3'd0; + litedramcore_bankmachine5_trascon_ready <= 1'd0; + litedramcore_bankmachine5_trascon_count <= 2'd0; + litedramcore_bankmachine6_level <= 4'd0; + litedramcore_bankmachine6_produce <= 3'd0; + litedramcore_bankmachine6_consume <= 3'd0; + litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine6_row <= 15'd0; + litedramcore_bankmachine6_row_opened <= 1'd0; + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + litedramcore_bankmachine6_twtpcon_count <= 3'd0; + litedramcore_bankmachine6_trccon_ready <= 1'd0; + litedramcore_bankmachine6_trccon_count <= 3'd0; + litedramcore_bankmachine6_trascon_ready <= 1'd0; + litedramcore_bankmachine6_trascon_count <= 2'd0; + litedramcore_bankmachine7_level <= 4'd0; + litedramcore_bankmachine7_produce <= 3'd0; + litedramcore_bankmachine7_consume <= 3'd0; + litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine7_row <= 15'd0; + litedramcore_bankmachine7_row_opened <= 1'd0; + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + litedramcore_bankmachine7_twtpcon_count <= 3'd0; + litedramcore_bankmachine7_trccon_ready <= 1'd0; + litedramcore_bankmachine7_trccon_count <= 3'd0; + litedramcore_bankmachine7_trascon_ready <= 1'd0; + litedramcore_bankmachine7_trascon_count <= 2'd0; + litedramcore_choose_cmd_grant <= 3'd0; + litedramcore_choose_req_grant <= 3'd0; + litedramcore_trrdcon_ready <= 1'd0; + litedramcore_trrdcon_count <= 2'd0; + litedramcore_tfawcon_ready <= 1'd1; + litedramcore_tfawcon_window <= 4'd0; + litedramcore_tccdcon_ready <= 1'd0; + litedramcore_tccdcon_count <= 1'd0; + litedramcore_twtrcon_ready <= 1'd0; + litedramcore_twtrcon_count <= 3'd0; + litedramcore_time0 <= 5'd0; + litedramcore_time1 <= 4'd0; + init_done_storage <= 1'd0; + init_done_wr_stb <= 1'd0; + init_error_storage <= 1'd0; + init_error_wr_stb <= 1'd0; + user_enable <= 1'd0; + interface1_re <= 1'd0; + interface1_we <= 1'd0; + selected_r <= 1'd0; + slaves <= 1'd0; + count <= 20'd1000000; + refresher_state <= 2'd0; + bankmachine0_state <= 3'd0; + bankmachine1_state <= 3'd0; + bankmachine2_state <= 3'd0; + bankmachine3_state <= 3'd0; + bankmachine4_state <= 3'd0; + bankmachine5_state <= 3'd0; + bankmachine6_state <= 3'd0; + bankmachine7_state <= 3'd0; + multiplexer_state <= 4'd0; + new_master_wdata_ready0 <= 1'd0; + new_master_wdata_ready1 <= 1'd0; + new_master_wdata_ready2 <= 1'd0; + new_master_wdata_ready3 <= 1'd0; + new_master_rdata_valid0 <= 1'd0; + new_master_rdata_valid1 <= 1'd0; + new_master_rdata_valid2 <= 1'd0; + new_master_rdata_valid3 <= 1'd0; + new_master_rdata_valid4 <= 1'd0; + new_master_rdata_valid5 <= 1'd0; + new_master_rdata_valid6 <= 1'd0; + new_master_rdata_valid7 <= 1'd0; + new_master_rdata_valid8 <= 1'd0; + new_master_rdata_valid9 <= 1'd0; + new_master_rdata_valid10 <= 1'd0; + new_master_rdata_valid11 <= 1'd0; + new_master_rdata_valid12 <= 1'd0; + new_master_rdata_valid13 <= 1'd0; + state <= 2'd0; + end +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Instance ECLKBRIDGECS of ECLKBRIDGECS Module. +//------------------------------------------------------------------------------ +ECLKBRIDGECS ECLKBRIDGECS( + // Inputs. + .CLK0 (sys2x_i_clk), + .SEL (1'd0), + + // Outputs. + .ECSOUT (crg_sys2x_clk_ecsout) +); + +//------------------------------------------------------------------------------ +// Instance ECLKSYNCB of ECLKSYNCB Module. +//------------------------------------------------------------------------------ +ECLKSYNCB ECLKSYNCB( + // Inputs. + .ECLKI (crg_sys2x_clk_ecsout), + .STOP (crg_stop), + + // Outputs. + .ECLKO (sys2x_clk) +); + +//------------------------------------------------------------------------------ +// Instance CLKDIVF of CLKDIVF Module. +//------------------------------------------------------------------------------ +CLKDIVF #( + // Parameters. + .DIV ("2.0") +) CLKDIVF ( + // Inputs. + .ALIGNWD (1'd0), + .CLKI (sys2x_clk), + .RST (crg_reset0), + + // Outputs. + .CDIVX (sys_clk) +); + +//------------------------------------------------------------------------------ +// Instance DDRDLLA of DDRDLLA Module. +//------------------------------------------------------------------------------ +DDRDLLA DDRDLLA( + // Inputs. + .CLK (sys2x_clk), + .FREEZE (ddrphy_freeze), + .RST (init_rst), + .UDDCNTLN ((~ddrphy_update)), + + // Outputs. + .DDRDEL (ddrphy_delay1), + .LOCK (ddrphy_lock0) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F( + // Inputs. + .D0 (1'd0), + .D1 (1'd1), + .D2 (1'd0), + .D3 (1'd1), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f0) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG ( + // Inputs. + .A (ddrphy_pad_oddrx2f0), + + // Outputs. + .Z (ddram_clk_p) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_1 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_1( + // Inputs. + .D0 (ddrphy_dfi_p0_reset_n), + .D1 (ddrphy_dfi_p0_reset_n), + .D2 (ddrphy_dfi_p1_reset_n), + .D3 (ddrphy_dfi_p1_reset_n), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f1) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_1 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_1 ( + // Inputs. + .A (ddrphy_pad_oddrx2f1), + + // Outputs. + .Z (ddram_reset_n) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_2 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_2( + // Inputs. + .D0 (ddrphy_dfi_p0_cs_n), + .D1 (ddrphy_dfi_p0_cs_n), + .D2 (ddrphy_dfi_p1_cs_n), + .D3 (ddrphy_dfi_p1_cs_n), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f2) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_2 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_2 ( + // Inputs. + .A (ddrphy_pad_oddrx2f2), + + // Outputs. + .Z (ddram_cs_n) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_3 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_3( + // Inputs. + .D0 (ddrphy_dfi_p0_address[0]), + .D1 (ddrphy_dfi_p0_address[0]), + .D2 (ddrphy_dfi_p1_address[0]), + .D3 (ddrphy_dfi_p1_address[0]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f3) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_3 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_3 ( + // Inputs. + .A (ddrphy_pad_oddrx2f3), + + // Outputs. + .Z (ddram_a[0]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_4 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_4( + // Inputs. + .D0 (ddrphy_dfi_p0_address[1]), + .D1 (ddrphy_dfi_p0_address[1]), + .D2 (ddrphy_dfi_p1_address[1]), + .D3 (ddrphy_dfi_p1_address[1]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f4) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_4 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_4 ( + // Inputs. + .A (ddrphy_pad_oddrx2f4), + + // Outputs. + .Z (ddram_a[1]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_5 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_5( + // Inputs. + .D0 (ddrphy_dfi_p0_address[2]), + .D1 (ddrphy_dfi_p0_address[2]), + .D2 (ddrphy_dfi_p1_address[2]), + .D3 (ddrphy_dfi_p1_address[2]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f5) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_5 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_5 ( + // Inputs. + .A (ddrphy_pad_oddrx2f5), + + // Outputs. + .Z (ddram_a[2]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_6 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_6( + // Inputs. + .D0 (ddrphy_dfi_p0_address[3]), + .D1 (ddrphy_dfi_p0_address[3]), + .D2 (ddrphy_dfi_p1_address[3]), + .D3 (ddrphy_dfi_p1_address[3]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f6) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_6 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_6 ( + // Inputs. + .A (ddrphy_pad_oddrx2f6), + + // Outputs. + .Z (ddram_a[3]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_7 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_7( + // Inputs. + .D0 (ddrphy_dfi_p0_address[4]), + .D1 (ddrphy_dfi_p0_address[4]), + .D2 (ddrphy_dfi_p1_address[4]), + .D3 (ddrphy_dfi_p1_address[4]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f7) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_7 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_7 ( + // Inputs. + .A (ddrphy_pad_oddrx2f7), + + // Outputs. + .Z (ddram_a[4]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_8 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_8( + // Inputs. + .D0 (ddrphy_dfi_p0_address[5]), + .D1 (ddrphy_dfi_p0_address[5]), + .D2 (ddrphy_dfi_p1_address[5]), + .D3 (ddrphy_dfi_p1_address[5]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f8) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_8 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_8 ( + // Inputs. + .A (ddrphy_pad_oddrx2f8), + + // Outputs. + .Z (ddram_a[5]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_9 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_9( + // Inputs. + .D0 (ddrphy_dfi_p0_address[6]), + .D1 (ddrphy_dfi_p0_address[6]), + .D2 (ddrphy_dfi_p1_address[6]), + .D3 (ddrphy_dfi_p1_address[6]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f9) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_9 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_9 ( + // Inputs. + .A (ddrphy_pad_oddrx2f9), + + // Outputs. + .Z (ddram_a[6]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_10 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_10( + // Inputs. + .D0 (ddrphy_dfi_p0_address[7]), + .D1 (ddrphy_dfi_p0_address[7]), + .D2 (ddrphy_dfi_p1_address[7]), + .D3 (ddrphy_dfi_p1_address[7]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f10) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_10 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_10 ( + // Inputs. + .A (ddrphy_pad_oddrx2f10), + + // Outputs. + .Z (ddram_a[7]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_11 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_11( + // Inputs. + .D0 (ddrphy_dfi_p0_address[8]), + .D1 (ddrphy_dfi_p0_address[8]), + .D2 (ddrphy_dfi_p1_address[8]), + .D3 (ddrphy_dfi_p1_address[8]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f11) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_11 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_11 ( + // Inputs. + .A (ddrphy_pad_oddrx2f11), + + // Outputs. + .Z (ddram_a[8]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_12 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_12( + // Inputs. + .D0 (ddrphy_dfi_p0_address[9]), + .D1 (ddrphy_dfi_p0_address[9]), + .D2 (ddrphy_dfi_p1_address[9]), + .D3 (ddrphy_dfi_p1_address[9]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f12) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_12 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_12 ( + // Inputs. + .A (ddrphy_pad_oddrx2f12), + + // Outputs. + .Z (ddram_a[9]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_13 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_13( + // Inputs. + .D0 (ddrphy_dfi_p0_address[10]), + .D1 (ddrphy_dfi_p0_address[10]), + .D2 (ddrphy_dfi_p1_address[10]), + .D3 (ddrphy_dfi_p1_address[10]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f13) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_13 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_13 ( + // Inputs. + .A (ddrphy_pad_oddrx2f13), + + // Outputs. + .Z (ddram_a[10]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_14 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_14( + // Inputs. + .D0 (ddrphy_dfi_p0_address[11]), + .D1 (ddrphy_dfi_p0_address[11]), + .D2 (ddrphy_dfi_p1_address[11]), + .D3 (ddrphy_dfi_p1_address[11]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f14) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_14 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_14 ( + // Inputs. + .A (ddrphy_pad_oddrx2f14), + + // Outputs. + .Z (ddram_a[11]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_15 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_15( + // Inputs. + .D0 (ddrphy_dfi_p0_address[12]), + .D1 (ddrphy_dfi_p0_address[12]), + .D2 (ddrphy_dfi_p1_address[12]), + .D3 (ddrphy_dfi_p1_address[12]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f15) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_15 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_15 ( + // Inputs. + .A (ddrphy_pad_oddrx2f15), + + // Outputs. + .Z (ddram_a[12]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_16 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_16( + // Inputs. + .D0 (ddrphy_dfi_p0_address[13]), + .D1 (ddrphy_dfi_p0_address[13]), + .D2 (ddrphy_dfi_p1_address[13]), + .D3 (ddrphy_dfi_p1_address[13]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f16) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_16 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_16 ( + // Inputs. + .A (ddrphy_pad_oddrx2f16), + + // Outputs. + .Z (ddram_a[13]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_17 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_17( + // Inputs. + .D0 (ddrphy_dfi_p0_address[14]), + .D1 (ddrphy_dfi_p0_address[14]), + .D2 (ddrphy_dfi_p1_address[14]), + .D3 (ddrphy_dfi_p1_address[14]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f17) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_17 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_17 ( + // Inputs. + .A (ddrphy_pad_oddrx2f17), + + // Outputs. + .Z (ddram_a[14]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_18 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_18( + // Inputs. + .D0 (ddrphy_dfi_p0_bank[0]), + .D1 (ddrphy_dfi_p0_bank[0]), + .D2 (ddrphy_dfi_p1_bank[0]), + .D3 (ddrphy_dfi_p1_bank[0]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f18) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_18 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_18 ( + // Inputs. + .A (ddrphy_pad_oddrx2f18), + + // Outputs. + .Z (ddram_ba[0]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_19 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_19( + // Inputs. + .D0 (ddrphy_dfi_p0_bank[1]), + .D1 (ddrphy_dfi_p0_bank[1]), + .D2 (ddrphy_dfi_p1_bank[1]), + .D3 (ddrphy_dfi_p1_bank[1]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f19) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_19 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_19 ( + // Inputs. + .A (ddrphy_pad_oddrx2f19), + + // Outputs. + .Z (ddram_ba[1]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_20 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_20( + // Inputs. + .D0 (ddrphy_dfi_p0_bank[2]), + .D1 (ddrphy_dfi_p0_bank[2]), + .D2 (ddrphy_dfi_p1_bank[2]), + .D3 (ddrphy_dfi_p1_bank[2]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f20) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_20 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_20 ( + // Inputs. + .A (ddrphy_pad_oddrx2f20), + + // Outputs. + .Z (ddram_ba[2]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_21 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_21( + // Inputs. + .D0 (ddrphy_dfi_p0_ras_n), + .D1 (ddrphy_dfi_p0_ras_n), + .D2 (ddrphy_dfi_p1_ras_n), + .D3 (ddrphy_dfi_p1_ras_n), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f21) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_21 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_21 ( + // Inputs. + .A (ddrphy_pad_oddrx2f21), + + // Outputs. + .Z (ddram_ras_n) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_22 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_22( + // Inputs. + .D0 (ddrphy_dfi_p0_cas_n), + .D1 (ddrphy_dfi_p0_cas_n), + .D2 (ddrphy_dfi_p1_cas_n), + .D3 (ddrphy_dfi_p1_cas_n), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f22) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_22 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_22 ( + // Inputs. + .A (ddrphy_pad_oddrx2f22), + + // Outputs. + .Z (ddram_cas_n) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_23 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_23( + // Inputs. + .D0 (ddrphy_dfi_p0_we_n), + .D1 (ddrphy_dfi_p0_we_n), + .D2 (ddrphy_dfi_p1_we_n), + .D3 (ddrphy_dfi_p1_we_n), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f23) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_23 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_23 ( + // Inputs. + .A (ddrphy_pad_oddrx2f23), + + // Outputs. + .Z (ddram_we_n) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_24 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_24( + // Inputs. + .D0 (ddrphy_dfi_p0_cke), + .D1 (ddrphy_dfi_p0_cke), + .D2 (ddrphy_dfi_p1_cke), + .D3 (ddrphy_dfi_p1_cke), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f24) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_24 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_24 ( + // Inputs. + .A (ddrphy_pad_oddrx2f24), + + // Outputs. + .Z (ddram_cke) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_25 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_25( + // Inputs. + .D0 (ddrphy_dfi_p0_odt), + .D1 (ddrphy_dfi_p0_odt), + .D2 (ddrphy_dfi_p1_odt), + .D3 (ddrphy_dfi_p1_odt), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f25) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_25 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_25 ( + // Inputs. + .A (ddrphy_pad_oddrx2f25), + + // Outputs. + .Z (ddram_odt) +); + +//------------------------------------------------------------------------------ +// Instance DQSBUFM of DQSBUFM Module. +//------------------------------------------------------------------------------ +DQSBUFM #( + // Parameters. + .DQS_LI_DEL_ADJ ("MINUS"), + .DQS_LI_DEL_VAL (1'd1), + .DQS_LO_DEL_ADJ ("MINUS"), + .DQS_LO_DEL_VAL (3'd4) +) DQSBUFM ( + // Inputs. + .DDRDEL (ddrphy_delay0), + .DQSI (ddrphy_dqs_i0), + .ECLK (sys2x_clk), + .PAUSE ((ddrphy_pause0 | ddrphy_dly_sel_storage[0])), + .RDDIRECTION (1'd1), + .RDLOADN (1'd0), + .RDMOVE (1'd0), + .READ0 (ddrphy_dqs_re), + .READ1 (ddrphy_dqs_re), + .READCLKSEL0 (ddrphy_rdly0[0]), + .READCLKSEL1 (ddrphy_rdly0[1]), + .READCLKSEL2 (ddrphy_rdly0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRDIRECTION (1'd1), + .WRLOADN (1'd0), + .WRMOVE (1'd0), + + // Outputs. + .BURSTDET (ddrphy_burstdet0), + .DATAVALID (ddrphy_datavalid[0]), + .DQSR90 (ddrphy_dqsr900), + .DQSW (ddrphy_dqsw0), + .DQSW270 (ddrphy_dqsw2700), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQSB of ODDRX2DQSB Module. +//------------------------------------------------------------------------------ +ODDRX2DQSB ODDRX2DQSB( + // Inputs. + .D0 (1'd0), + .D1 (1'd1), + .D2 (1'd0), + .D3 (1'd1), + .DQSW (ddrphy_dqsw0), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dqs0) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQSA of TSHX2DQSA Module. +//------------------------------------------------------------------------------ +TSHX2DQSA TSHX2DQSA( + // Inputs. + .DQSW (ddrphy_dqsw0), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))), + .T1 ((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))), + + // Outputs. + .Q (ddrphy_dqs_oe_n0) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA( + // Inputs. + .D0 (ddrphy_dm_o_data_muxed0[0]), + .D1 (ddrphy_dm_o_data_muxed0[1]), + .D2 (ddrphy_dm_o_data_muxed0[2]), + .D3 (ddrphy_dm_o_data_muxed0[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddram_dm[0]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_1 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_1( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed0[0]), + .D1 (ddrphy_dq_o_data_muxed0[1]), + .D2 (ddrphy_dq_o_data_muxed0[2]), + .D3 (ddrphy_dq_o_data_muxed0[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o0) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_26 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_26 ( + // Inputs. + .A (ddrphy_dq_i0), + + // Outputs. + .Z (ddrphy_dq_i_delayed0) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA( + // Inputs. + .D (ddrphy_dq_i_delayed0), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip0_i[0]), + .Q1 (ddrphy_bitslip0_i[1]), + .Q2 (ddrphy_bitslip0_i[2]), + .Q3 (ddrphy_bitslip0_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA( + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n0) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_2 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_2( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed1[0]), + .D1 (ddrphy_dq_o_data_muxed1[1]), + .D2 (ddrphy_dq_o_data_muxed1[2]), + .D3 (ddrphy_dq_o_data_muxed1[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o1) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_27 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_27 ( + // Inputs. + .A (ddrphy_dq_i1), + + // Outputs. + .Z (ddrphy_dq_i_delayed1) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_1 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_1( + // Inputs. + .D (ddrphy_dq_i_delayed1), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip1_i[0]), + .Q1 (ddrphy_bitslip1_i[1]), + .Q2 (ddrphy_bitslip1_i[2]), + .Q3 (ddrphy_bitslip1_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_1 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_1( + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n1) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_3 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_3( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed2[0]), + .D1 (ddrphy_dq_o_data_muxed2[1]), + .D2 (ddrphy_dq_o_data_muxed2[2]), + .D3 (ddrphy_dq_o_data_muxed2[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o2) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_28 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_28 ( + // Inputs. + .A (ddrphy_dq_i2), + + // Outputs. + .Z (ddrphy_dq_i_delayed2) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_2 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_2( + // Inputs. + .D (ddrphy_dq_i_delayed2), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip2_i[0]), + .Q1 (ddrphy_bitslip2_i[1]), + .Q2 (ddrphy_bitslip2_i[2]), + .Q3 (ddrphy_bitslip2_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_2 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_2( + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n2) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_4 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_4( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed3[0]), + .D1 (ddrphy_dq_o_data_muxed3[1]), + .D2 (ddrphy_dq_o_data_muxed3[2]), + .D3 (ddrphy_dq_o_data_muxed3[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o3) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_29 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_29 ( + // Inputs. + .A (ddrphy_dq_i3), + + // Outputs. + .Z (ddrphy_dq_i_delayed3) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_3 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_3( + // Inputs. + .D (ddrphy_dq_i_delayed3), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip3_i[0]), + .Q1 (ddrphy_bitslip3_i[1]), + .Q2 (ddrphy_bitslip3_i[2]), + .Q3 (ddrphy_bitslip3_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_3 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_3( + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n3) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_5 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_5( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed4[0]), + .D1 (ddrphy_dq_o_data_muxed4[1]), + .D2 (ddrphy_dq_o_data_muxed4[2]), + .D3 (ddrphy_dq_o_data_muxed4[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o4) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_30 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_30 ( + // Inputs. + .A (ddrphy_dq_i4), + + // Outputs. + .Z (ddrphy_dq_i_delayed4) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_4 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_4( + // Inputs. + .D (ddrphy_dq_i_delayed4), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip4_i[0]), + .Q1 (ddrphy_bitslip4_i[1]), + .Q2 (ddrphy_bitslip4_i[2]), + .Q3 (ddrphy_bitslip4_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_4 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_4( + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n4) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_6 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_6( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed5[0]), + .D1 (ddrphy_dq_o_data_muxed5[1]), + .D2 (ddrphy_dq_o_data_muxed5[2]), + .D3 (ddrphy_dq_o_data_muxed5[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o5) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_31 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_31 ( + // Inputs. + .A (ddrphy_dq_i5), + + // Outputs. + .Z (ddrphy_dq_i_delayed5) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_5 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_5( + // Inputs. + .D (ddrphy_dq_i_delayed5), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip5_i[0]), + .Q1 (ddrphy_bitslip5_i[1]), + .Q2 (ddrphy_bitslip5_i[2]), + .Q3 (ddrphy_bitslip5_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_5 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_5( + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n5) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_7 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_7( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed6[0]), + .D1 (ddrphy_dq_o_data_muxed6[1]), + .D2 (ddrphy_dq_o_data_muxed6[2]), + .D3 (ddrphy_dq_o_data_muxed6[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o6) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_32 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_32 ( + // Inputs. + .A (ddrphy_dq_i6), + + // Outputs. + .Z (ddrphy_dq_i_delayed6) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_6 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_6( + // Inputs. + .D (ddrphy_dq_i_delayed6), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip6_i[0]), + .Q1 (ddrphy_bitslip6_i[1]), + .Q2 (ddrphy_bitslip6_i[2]), + .Q3 (ddrphy_bitslip6_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_6 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_6( + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n6) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_8 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_8( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed7[0]), + .D1 (ddrphy_dq_o_data_muxed7[1]), + .D2 (ddrphy_dq_o_data_muxed7[2]), + .D3 (ddrphy_dq_o_data_muxed7[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o7) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_33 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_33 ( + // Inputs. + .A (ddrphy_dq_i7), + + // Outputs. + .Z (ddrphy_dq_i_delayed7) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_7 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_7( + // Inputs. + .D (ddrphy_dq_i_delayed7), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip7_i[0]), + .Q1 (ddrphy_bitslip7_i[1]), + .Q2 (ddrphy_bitslip7_i[2]), + .Q3 (ddrphy_bitslip7_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_7 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_7( + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n7) +); + +//------------------------------------------------------------------------------ +// Instance DQSBUFM_1 of DQSBUFM Module. +//------------------------------------------------------------------------------ +DQSBUFM #( + // Parameters. + .DQS_LI_DEL_ADJ ("MINUS"), + .DQS_LI_DEL_VAL (1'd1), + .DQS_LO_DEL_ADJ ("MINUS"), + .DQS_LO_DEL_VAL (3'd4) +) DQSBUFM_1 ( + // Inputs. + .DDRDEL (ddrphy_delay0), + .DQSI (ddrphy_dqs_i1), + .ECLK (sys2x_clk), + .PAUSE ((ddrphy_pause0 | ddrphy_dly_sel_storage[1])), + .RDDIRECTION (1'd1), + .RDLOADN (1'd0), + .RDMOVE (1'd0), + .READ0 (ddrphy_dqs_re), + .READ1 (ddrphy_dqs_re), + .READCLKSEL0 (ddrphy_rdly1[0]), + .READCLKSEL1 (ddrphy_rdly1[1]), + .READCLKSEL2 (ddrphy_rdly1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRDIRECTION (1'd1), + .WRLOADN (1'd0), + .WRMOVE (1'd0), + + // Outputs. + .BURSTDET (ddrphy_burstdet1), + .DATAVALID (ddrphy_datavalid[1]), + .DQSR90 (ddrphy_dqsr901), + .DQSW (ddrphy_dqsw1), + .DQSW270 (ddrphy_dqsw2701), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQSB_1 of ODDRX2DQSB Module. +//------------------------------------------------------------------------------ +ODDRX2DQSB ODDRX2DQSB_1( + // Inputs. + .D0 (1'd0), + .D1 (1'd1), + .D2 (1'd0), + .D3 (1'd1), + .DQSW (ddrphy_dqsw1), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dqs1) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQSA_1 of TSHX2DQSA Module. +//------------------------------------------------------------------------------ +TSHX2DQSA TSHX2DQSA_1( + // Inputs. + .DQSW (ddrphy_dqsw1), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))), + .T1 ((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))), + + // Outputs. + .Q (ddrphy_dqs_oe_n1) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_9 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_9( + // Inputs. + .D0 (ddrphy_dm_o_data_muxed1[0]), + .D1 (ddrphy_dm_o_data_muxed1[1]), + .D2 (ddrphy_dm_o_data_muxed1[2]), + .D3 (ddrphy_dm_o_data_muxed1[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddram_dm[1]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_10 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_10( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed8[0]), + .D1 (ddrphy_dq_o_data_muxed8[1]), + .D2 (ddrphy_dq_o_data_muxed8[2]), + .D3 (ddrphy_dq_o_data_muxed8[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o8) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_34 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_34 ( + // Inputs. + .A (ddrphy_dq_i8), + + // Outputs. + .Z (ddrphy_dq_i_delayed8) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_8 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_8( + // Inputs. + .D (ddrphy_dq_i_delayed8), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip8_i[0]), + .Q1 (ddrphy_bitslip8_i[1]), + .Q2 (ddrphy_bitslip8_i[2]), + .Q3 (ddrphy_bitslip8_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_8 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_8( + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n8) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_11 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_11( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed9[0]), + .D1 (ddrphy_dq_o_data_muxed9[1]), + .D2 (ddrphy_dq_o_data_muxed9[2]), + .D3 (ddrphy_dq_o_data_muxed9[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o9) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_35 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_35 ( + // Inputs. + .A (ddrphy_dq_i9), + + // Outputs. + .Z (ddrphy_dq_i_delayed9) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_9 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_9( + // Inputs. + .D (ddrphy_dq_i_delayed9), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip9_i[0]), + .Q1 (ddrphy_bitslip9_i[1]), + .Q2 (ddrphy_bitslip9_i[2]), + .Q3 (ddrphy_bitslip9_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_9 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_9( + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n9) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_12 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_12( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed10[0]), + .D1 (ddrphy_dq_o_data_muxed10[1]), + .D2 (ddrphy_dq_o_data_muxed10[2]), + .D3 (ddrphy_dq_o_data_muxed10[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o10) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_36 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_36 ( + // Inputs. + .A (ddrphy_dq_i10), + + // Outputs. + .Z (ddrphy_dq_i_delayed10) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_10 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_10( + // Inputs. + .D (ddrphy_dq_i_delayed10), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip10_i[0]), + .Q1 (ddrphy_bitslip10_i[1]), + .Q2 (ddrphy_bitslip10_i[2]), + .Q3 (ddrphy_bitslip10_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_10 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_10( + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n10) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_13 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_13( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed11[0]), + .D1 (ddrphy_dq_o_data_muxed11[1]), + .D2 (ddrphy_dq_o_data_muxed11[2]), + .D3 (ddrphy_dq_o_data_muxed11[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o11) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_37 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_37 ( + // Inputs. + .A (ddrphy_dq_i11), + + // Outputs. + .Z (ddrphy_dq_i_delayed11) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_11 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_11( + // Inputs. + .D (ddrphy_dq_i_delayed11), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip11_i[0]), + .Q1 (ddrphy_bitslip11_i[1]), + .Q2 (ddrphy_bitslip11_i[2]), + .Q3 (ddrphy_bitslip11_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_11 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_11( + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n11) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_14 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_14( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed12[0]), + .D1 (ddrphy_dq_o_data_muxed12[1]), + .D2 (ddrphy_dq_o_data_muxed12[2]), + .D3 (ddrphy_dq_o_data_muxed12[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o12) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_38 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_38 ( + // Inputs. + .A (ddrphy_dq_i12), + + // Outputs. + .Z (ddrphy_dq_i_delayed12) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_12 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_12( + // Inputs. + .D (ddrphy_dq_i_delayed12), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip12_i[0]), + .Q1 (ddrphy_bitslip12_i[1]), + .Q2 (ddrphy_bitslip12_i[2]), + .Q3 (ddrphy_bitslip12_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_12 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_12( + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n12) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_15 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_15( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed13[0]), + .D1 (ddrphy_dq_o_data_muxed13[1]), + .D2 (ddrphy_dq_o_data_muxed13[2]), + .D3 (ddrphy_dq_o_data_muxed13[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o13) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_39 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_39 ( + // Inputs. + .A (ddrphy_dq_i13), + + // Outputs. + .Z (ddrphy_dq_i_delayed13) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_13 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_13( + // Inputs. + .D (ddrphy_dq_i_delayed13), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip13_i[0]), + .Q1 (ddrphy_bitslip13_i[1]), + .Q2 (ddrphy_bitslip13_i[2]), + .Q3 (ddrphy_bitslip13_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_13 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_13( + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n13) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_16 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_16( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed14[0]), + .D1 (ddrphy_dq_o_data_muxed14[1]), + .D2 (ddrphy_dq_o_data_muxed14[2]), + .D3 (ddrphy_dq_o_data_muxed14[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o14) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_40 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_40 ( + // Inputs. + .A (ddrphy_dq_i14), + + // Outputs. + .Z (ddrphy_dq_i_delayed14) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_14 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_14( + // Inputs. + .D (ddrphy_dq_i_delayed14), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip14_i[0]), + .Q1 (ddrphy_bitslip14_i[1]), + .Q2 (ddrphy_bitslip14_i[2]), + .Q3 (ddrphy_bitslip14_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_14 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_14( + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n14) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_17 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_17( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed15[0]), + .D1 (ddrphy_dq_o_data_muxed15[1]), + .D2 (ddrphy_dq_o_data_muxed15[2]), + .D3 (ddrphy_dq_o_data_muxed15[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o15) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_41 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_41 ( + // Inputs. + .A (ddrphy_dq_i15), + + // Outputs. + .Z (ddrphy_dq_i_delayed15) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_15 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_15( + // Inputs. + .D (ddrphy_dq_i_delayed15), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip15_i[0]), + .Q1 (ddrphy_bitslip15_i[1]), + .Q2 (ddrphy_bitslip15_i[2]), + .Q3 (ddrphy_bitslip15_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_15 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_15( + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n15) +); + +//------------------------------------------------------------------------------ +// Memory storage: 8-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage[0:7]; +reg [24:0] storage_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine0_wrport_we) + storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w; + storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0; +assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 8-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_1[0:7]; +reg [24:0] storage_1_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine1_wrport_we) + storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w; + storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; +assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_2: 8-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_2[0:7]; +reg [24:0] storage_2_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine2_wrport_we) + storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w; + storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; +assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_3: 8-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_3[0:7]; +reg [24:0] storage_3_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine3_wrport_we) + storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w; + storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; +assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_4: 8-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_4[0:7]; +reg [24:0] storage_4_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine4_wrport_we) + storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w; + storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; +assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_5: 8-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_5[0:7]; +reg [24:0] storage_5_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine5_wrport_we) + storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w; + storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; +assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_6: 8-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_6[0:7]; +reg [24:0] storage_6_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine6_wrport_we) + storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w; + storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; +assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_7: 8-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_7[0:7]; +reg [24:0] storage_7_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine7_wrport_we) + storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w; + storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; +assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr]; + + +(* FREQUENCY_PIN_CLKI = "16.0", FREQUENCY_PIN_CLKOP = "150.0", FREQUENCY_PIN_CLKOS = "25.0", ICP_CURRENT = "6", LPF_RESISTOR = "16", MFG_ENABLE_FILTEROPAMP = "1", MFG_GMCREF_SEL = "2" *) +//------------------------------------------------------------------------------ +// Instance EHXPLLL of EHXPLLL Module. +//------------------------------------------------------------------------------ +EHXPLLL #( + // Parameters. + .CLKFB_DIV (6'd47), + .CLKI_DIV (1'd1), + .CLKOP_CPHASE (3'd4), + .CLKOP_DIV (3'd5), + .CLKOP_ENABLE ("ENABLED"), + .CLKOP_FPHASE (1'd0), + .CLKOS2_CPHASE (1'd0), + .CLKOS2_DIV (1'd1), + .CLKOS2_ENABLE ("ENABLED"), + .CLKOS2_FPHASE (1'd0), + .CLKOS_CPHASE (5'd29), + .CLKOS_DIV (5'd30), + .CLKOS_ENABLE ("ENABLED"), + .CLKOS_FPHASE (1'd0), + .FEEDBK_PATH ("INT_OS2") +) EHXPLLL ( + // Inputs. + .CLKI (crg_clkin_signal), + .RST (crg_reset1), + .STDBY (crg_stdby), + + // Outputs. + .CLKOP (crg_clkout0), + .CLKOS (crg_clkout1), + .CLKOS2 (ecp5pll), + .LOCK (ecp5pll_locked) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX( + // Inputs. + .CK (sys2x_i_clk), + .D (1'd0), + .PD ((~crg_locked)), + + // Outputs. + .Q (latticeecp5asyncresetsynchronizerimpl0_rst1) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_1 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_1( + // Inputs. + .CK (sys2x_i_clk), + .D (latticeecp5asyncresetsynchronizerimpl0_rst1), + .PD ((~crg_locked)), + + // Outputs. + .Q (latticeecp5asyncresetsynchronizerimpl0_expr) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_2 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_2( + // Inputs. + .CK (init_clk), + .D (1'd0), + .PD ((~crg_locked)), + + // Outputs. + .Q (latticeecp5asyncresetsynchronizerimpl1_rst1) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_3 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_3( + // Inputs. + .CK (init_clk), + .D (latticeecp5asyncresetsynchronizerimpl1_rst1), + .PD ((~crg_locked)), + + // Outputs. + .Q (init_rst) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_4 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_4( + // Inputs. + .CK (sys_clk), + .D (1'd0), + .PD (((~crg_locked) | crg_reset0)), + + // Outputs. + .Q (latticeecp5asyncresetsynchronizerimpl2_rst1) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_5 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_5( + // Inputs. + .CK (sys_clk), + .D (latticeecp5asyncresetsynchronizerimpl2_rst1), + .PD (((~crg_locked) | crg_reset0)), + + // Outputs. + .Q (sys_rst) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_6 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_6( + // Inputs. + .CK (sys2x_clk), + .D (1'd0), + .PD (((~crg_locked) | crg_reset0)), + + // Outputs. + .Q (latticeecp5asyncresetsynchronizerimpl3_rst1) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_7 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_7( + // Inputs. + .CK (sys2x_clk), + .D (latticeecp5asyncresetsynchronizerimpl3_rst1), + .PD (((~crg_locked) | crg_reset0)), + + // Outputs. + .Q (sys2x_rst) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO ( + // Inputs. + .B (ddram_dqs_p[0]), + .I (ddrphy_dqs0), + .T ((~(~ddrphy_dqs_oe_n0))), + + // Outputs. + .O (ddrphy_dqs_i0) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_1 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_1 ( + // Inputs. + .B (ddram_dq[0]), + .I (ddrphy_dq_o0), + .T ((~(~ddrphy_dq_oe_n0))), + + // Outputs. + .O (ddrphy_dq_i0) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_2 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_2 ( + // Inputs. + .B (ddram_dq[1]), + .I (ddrphy_dq_o1), + .T ((~(~ddrphy_dq_oe_n1))), + + // Outputs. + .O (ddrphy_dq_i1) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_3 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_3 ( + // Inputs. + .B (ddram_dq[2]), + .I (ddrphy_dq_o2), + .T ((~(~ddrphy_dq_oe_n2))), + + // Outputs. + .O (ddrphy_dq_i2) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_4 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_4 ( + // Inputs. + .B (ddram_dq[3]), + .I (ddrphy_dq_o3), + .T ((~(~ddrphy_dq_oe_n3))), + + // Outputs. + .O (ddrphy_dq_i3) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_5 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_5 ( + // Inputs. + .B (ddram_dq[4]), + .I (ddrphy_dq_o4), + .T ((~(~ddrphy_dq_oe_n4))), + + // Outputs. + .O (ddrphy_dq_i4) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_6 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_6 ( + // Inputs. + .B (ddram_dq[5]), + .I (ddrphy_dq_o5), + .T ((~(~ddrphy_dq_oe_n5))), + + // Outputs. + .O (ddrphy_dq_i5) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_7 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_7 ( + // Inputs. + .B (ddram_dq[6]), + .I (ddrphy_dq_o6), + .T ((~(~ddrphy_dq_oe_n6))), + + // Outputs. + .O (ddrphy_dq_i6) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_8 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_8 ( + // Inputs. + .B (ddram_dq[7]), + .I (ddrphy_dq_o7), + .T ((~(~ddrphy_dq_oe_n7))), + + // Outputs. + .O (ddrphy_dq_i7) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_9 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_9 ( + // Inputs. + .B (ddram_dqs_p[1]), + .I (ddrphy_dqs1), + .T ((~(~ddrphy_dqs_oe_n1))), + + // Outputs. + .O (ddrphy_dqs_i1) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_10 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_10 ( + // Inputs. + .B (ddram_dq[8]), + .I (ddrphy_dq_o8), + .T ((~(~ddrphy_dq_oe_n8))), + + // Outputs. + .O (ddrphy_dq_i8) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_11 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_11 ( + // Inputs. + .B (ddram_dq[9]), + .I (ddrphy_dq_o9), + .T ((~(~ddrphy_dq_oe_n9))), + + // Outputs. + .O (ddrphy_dq_i9) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_12 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_12 ( + // Inputs. + .B (ddram_dq[10]), + .I (ddrphy_dq_o10), + .T ((~(~ddrphy_dq_oe_n10))), + + // Outputs. + .O (ddrphy_dq_i10) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_13 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_13 ( + // Inputs. + .B (ddram_dq[11]), + .I (ddrphy_dq_o11), + .T ((~(~ddrphy_dq_oe_n11))), + + // Outputs. + .O (ddrphy_dq_i11) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_14 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_14 ( + // Inputs. + .B (ddram_dq[12]), + .I (ddrphy_dq_o12), + .T ((~(~ddrphy_dq_oe_n12))), + + // Outputs. + .O (ddrphy_dq_i12) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_15 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_15 ( + // Inputs. + .B (ddram_dq[13]), + .I (ddrphy_dq_o13), + .T ((~(~ddrphy_dq_oe_n13))), + + // Outputs. + .O (ddrphy_dq_i13) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_16 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_16 ( + // Inputs. + .B (ddram_dq[14]), + .I (ddrphy_dq_o14), + .T ((~(~ddrphy_dq_oe_n14))), + + // Outputs. + .O (ddrphy_dq_i14) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_17 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_17 ( + // Inputs. + .B (ddram_dq[15]), + .I (ddrphy_dq_o15), + .T ((~(~ddrphy_dq_oe_n15))), + + // Outputs. + .O (ddrphy_dq_i15) +); + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2026-09-16 08:16:19. +//------------------------------------------------------------------------------ diff --git a/hardware/v2/ddr3/litedram_gen/litedram_core_sim.v b/hardware/v2/ddr3/litedram_gen/litedram_core_sim.v new file mode 100644 index 0000000..777eeef --- /dev/null +++ b/hardware/v2/ddr3/litedram_gen/litedram_core_sim.v @@ -0,0 +1,9781 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : litedram_core_sim.v +// Top : LiteDRAMCore +// Device : +// Hierarchy : disabled +// LiteX sha1 : 9ad3ecf74 +// Date : 2026-09-16 08:16:25 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module litedram_core_sim ( + input wire clk, + output wire init_done, + output wire init_error, + input wire sim_trace, + output wire user_clk, + input wire [24:0] user_port_native_0_cmd_addr, + output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_valid, + input wire user_port_native_0_cmd_we, + output wire [127:0] user_port_native_0_rdata_data, + input wire user_port_native_0_rdata_ready, + output wire user_port_native_0_rdata_valid, + input wire [127:0] user_port_native_0_wdata_data, + output wire user_port_native_0_wdata_ready, + input wire user_port_native_0_wdata_valid, + input wire [15:0] user_port_native_0_wdata_we, + output wire user_rst, + output wire wb_ctrl_ack, + input wire [29:0] wb_ctrl_adr, + input wire [1:0] wb_ctrl_bte, + input wire [2:0] wb_ctrl_cti, + input wire wb_ctrl_cyc, + output wire [31:0] wb_ctrl_dat_r, + input wire [31:0] wb_ctrl_dat_w, + output wire wb_ctrl_err, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_stb, + input wire wb_ctrl_we +); + + +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +LiteDRAMCore +├── bus (SoCBusHandler) +│ └── _interconnect (InterconnectShared) +│ ├── arbiter (Arbiter) +│ │ └── rr (RoundRobin) +│ ├── decoder (Decoder) +│ └── timeout (Timeout) +│ └── waittimer_0 (WaitTimer) [Gen] +├── csr (SoCCSRHandler) +├── irq (SoCIRQHandler) +├── cpu (CPUNone) +├── crg (CRG) +├── ddrphy (LiteDRAMCoreSimPHY) +│ ├── dfiphasemodel_0 (DFIPhaseModel) [Gen] +│ ├── dfiphasemodel_1 (DFIPhaseModel) [Gen] +│ ├── dfiphasemodel_2 (DFIPhaseModel) [Gen] +│ ├── dfiphasemodel_3 (DFIPhaseModel) [Gen] +│ ├── bankmodel_0 (BankModel) [Gen] +│ ├── bankmodel_1 (BankModel) [Gen] +│ ├── bankmodel_2 (BankModel) [Gen] +│ ├── bankmodel_3 (BankModel) [Gen] +│ ├── bankmodel_4 (BankModel) [Gen] +│ ├── bankmodel_5 (BankModel) [Gen] +│ ├── bankmodel_6 (BankModel) [Gen] +│ └── bankmodel_7 (BankModel) [Gen] +├── sdram (LiteDRAMCore) +│ ├── dfii (DFIInjector) +│ │ ├── pi0 (PhaseInjector) +│ │ ├── pi1 (PhaseInjector) +│ │ ├── pi2 (PhaseInjector) +│ │ └── pi3 (PhaseInjector) +│ ├── controller (LiteDRAMController) +│ │ ├── refresher (Refresher) +│ │ │ ├── timer (RefreshTimer) +│ │ │ ├── postponer (RefreshPostponer) +│ │ │ ├── sequencer (RefreshSequencer) +│ │ │ │ └── refreshexecuter_0 (RefreshExecuter) [Gen] +│ │ │ ├── zqcs_timer (RefreshTimer) +│ │ │ ├── zqs_executer (ZQCSExecuter) +│ │ │ └── fsm (FSM) +│ │ ├── bankmachine_0 (BankMachine) [Gen] +│ │ │ ├── syncfifo_0 (SyncFIFO) [Gen] +│ │ │ │ └── fifo (SyncFIFO) +│ │ │ ├── buffer_0 (Buffer) [Gen] +│ │ │ │ ├── pipe_valid (PipeValid) +│ │ │ │ └── pipeline (Pipeline) +│ │ │ ├── twtpcon (tXXDController) +│ │ │ ├── trccon (tXXDController) +│ │ │ ├── trascon (tXXDController) +│ │ │ └── fsm (FSM) +│ │ ├── bankmachine_1 (BankMachine) [Gen] +│ │ │ ├── syncfifo_0 (SyncFIFO) [Gen] +│ │ │ │ └── fifo (SyncFIFO) +│ │ │ ├── buffer_0 (Buffer) [Gen] +│ │ │ │ ├── pipe_valid (PipeValid) +│ │ │ │ └── pipeline (Pipeline) +│ │ │ ├── twtpcon (tXXDController) +│ │ │ ├── trccon (tXXDController) +│ │ │ ├── trascon (tXXDController) +│ │ │ └── fsm (FSM) +│ │ ├── bankmachine_2 (BankMachine) [Gen] +│ │ │ ├── syncfifo_0 (SyncFIFO) [Gen] +│ │ │ │ └── fifo (SyncFIFO) +│ │ │ ├── buffer_0 (Buffer) [Gen] +│ │ │ │ ├── pipe_valid (PipeValid) +│ │ │ │ └── pipeline (Pipeline) +│ │ │ ├── twtpcon (tXXDController) +│ │ │ ├── trccon (tXXDController) +│ │ │ ├── trascon (tXXDController) +│ │ │ └── fsm (FSM) +│ │ ├── bankmachine_3 (BankMachine) [Gen] +│ │ │ ├── syncfifo_0 (SyncFIFO) [Gen] +│ │ │ │ └── fifo (SyncFIFO) +│ │ │ ├── buffer_0 (Buffer) [Gen] +│ │ │ │ ├── pipe_valid (PipeValid) +│ │ │ │ └── pipeline (Pipeline) +│ │ │ ├── twtpcon (tXXDController) +│ │ │ ├── trccon (tXXDController) +│ │ │ ├── trascon (tXXDController) +│ │ │ └── fsm (FSM) +│ │ ├── bankmachine_4 (BankMachine) [Gen] +│ │ │ ├── syncfifo_0 (SyncFIFO) [Gen] +│ │ │ │ └── fifo (SyncFIFO) +│ │ │ ├── buffer_0 (Buffer) [Gen] +│ │ │ │ ├── pipe_valid (PipeValid) +│ │ │ │ └── pipeline (Pipeline) +│ │ │ ├── twtpcon (tXXDController) +│ │ │ ├── trccon (tXXDController) +│ │ │ ├── trascon (tXXDController) +│ │ │ └── fsm (FSM) +│ │ ├── bankmachine_5 (BankMachine) [Gen] +│ │ │ ├── syncfifo_0 (SyncFIFO) [Gen] +│ │ │ │ └── fifo (SyncFIFO) +│ │ │ ├── buffer_0 (Buffer) [Gen] +│ │ │ │ ├── pipe_valid (PipeValid) +│ │ │ │ └── pipeline (Pipeline) +│ │ │ ├── twtpcon (tXXDController) +│ │ │ ├── trccon (tXXDController) +│ │ │ ├── trascon (tXXDController) +│ │ │ └── fsm (FSM) +│ │ ├── bankmachine_6 (BankMachine) [Gen] +│ │ │ ├── syncfifo_0 (SyncFIFO) [Gen] +│ │ │ │ └── fifo (SyncFIFO) +│ │ │ ├── buffer_0 (Buffer) [Gen] +│ │ │ │ ├── pipe_valid (PipeValid) +│ │ │ │ └── pipeline (Pipeline) +│ │ │ ├── twtpcon (tXXDController) +│ │ │ ├── trccon (tXXDController) +│ │ │ ├── trascon (tXXDController) +│ │ │ └── fsm (FSM) +│ │ ├── bankmachine_7 (BankMachine) [Gen] +│ │ │ ├── syncfifo_0 (SyncFIFO) [Gen] +│ │ │ │ └── fifo (SyncFIFO) +│ │ │ ├── buffer_0 (Buffer) [Gen] +│ │ │ │ ├── pipe_valid (PipeValid) +│ │ │ │ └── pipeline (Pipeline) +│ │ │ ├── twtpcon (tXXDController) +│ │ │ ├── trccon (tXXDController) +│ │ │ ├── trascon (tXXDController) +│ │ │ └── fsm (FSM) +│ │ └── multiplexer (Multiplexer) +│ │ ├── choose_cmd (_CommandChooser) +│ │ │ └── roundrobin_0 (RoundRobin) [Gen] +│ │ ├── choose_req (_CommandChooser) +│ │ │ └── roundrobin_0 (RoundRobin) [Gen] +│ │ ├── _steerer_0 (_Steerer) [Gen] +│ │ ├── trrdcon (tXXDController) +│ │ ├── tfawcon (tFAWController) +│ │ ├── tccdcon (tXXDController) +│ │ ├── twtrcon (tXXDController) +│ │ └── fsm (FSM) +│ └── crossbar (LiteDRAMCrossbar) +│ ├── roundrobin_0 (RoundRobin) [Gen] +│ ├── roundrobin_1 (RoundRobin) [Gen] +│ ├── roundrobin_2 (RoundRobin) [Gen] +│ ├── roundrobin_3 (RoundRobin) [Gen] +│ ├── roundrobin_4 (RoundRobin) [Gen] +│ ├── roundrobin_5 (RoundRobin) [Gen] +│ ├── roundrobin_6 (RoundRobin) [Gen] +│ └── roundrobin_7 (RoundRobin) [Gen] +├── ddrctrl (LiteDRAMCoreControl) +├── csr_bridge (Wishbone2CSR) +│ └── fsm (FSM) +├── csr_bankarray (CSRBankArray) +│ ├── csrbank_0 (CSRBank) [Gen] +│ │ ├── csrstorage_0 (CSRStorage) [Gen] +│ │ └── csrstorage_1 (CSRStorage) [Gen] +│ ├── csrbank_1 (CSRBank) [Gen] +│ └── csrbank_2 (CSRBank) [Gen] +│ ├── csrstorage_0 (CSRStorage) [Gen] +│ ├── csrstorage_1 (CSRStorage) [Gen] +│ ├── csrstorage_2 (CSRStorage) [Gen] +│ ├── csrstorage_3 (CSRStorage) [Gen] +│ ├── csrstorage_4 (CSRStorage) [Gen] +│ ├── csrstatus_0 (CSRStatus) [Gen] +│ ├── csrstorage_5 (CSRStorage) [Gen] +│ ├── csrstorage_6 (CSRStorage) [Gen] +│ ├── csrstorage_7 (CSRStorage) [Gen] +│ ├── csrstorage_8 (CSRStorage) [Gen] +│ ├── csrstatus_1 (CSRStatus) [Gen] +│ ├── csrstorage_9 (CSRStorage) [Gen] +│ ├── csrstorage_10 (CSRStorage) [Gen] +│ ├── csrstorage_11 (CSRStorage) [Gen] +│ ├── csrstorage_12 (CSRStorage) [Gen] +│ ├── csrstatus_2 (CSRStatus) [Gen] +│ ├── csrstorage_13 (CSRStorage) [Gen] +│ ├── csrstorage_14 (CSRStorage) [Gen] +│ ├── csrstorage_15 (CSRStorage) [Gen] +│ ├── csrstorage_16 (CSRStorage) [Gen] +│ └── csrstatus_3 (CSRStatus) [Gen] +└── csr_interconnect (InterconnectShared) +Legend: + [Gen]: Auto-generated instance name. + [BB:NAME]: Blackbox instance (verilog Instance). + +*/ + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire [13:0] adr; +reg [2:0] bankmachine0_next_state = 3'd0; +reg [2:0] bankmachine0_state = 3'd0; +reg [2:0] bankmachine1_next_state = 3'd0; +reg [2:0] bankmachine1_state = 3'd0; +reg [2:0] bankmachine2_next_state = 3'd0; +reg [2:0] bankmachine2_state = 3'd0; +reg [2:0] bankmachine3_next_state = 3'd0; +reg [2:0] bankmachine3_state = 3'd0; +reg [2:0] bankmachine4_next_state = 3'd0; +reg [2:0] bankmachine4_state = 3'd0; +reg [2:0] bankmachine5_next_state = 3'd0; +reg [2:0] bankmachine5_state = 3'd0; +reg [2:0] bankmachine6_next_state = 3'd0; +reg [2:0] bankmachine6_state = 3'd0; +reg [2:0] bankmachine7_next_state = 3'd0; +reg [2:0] bankmachine7_state = 3'd0; +reg [31:0] cases_self = 32'd0; +reg [19:0] count = 20'd1000000; +reg csr_data_width = 1'd0; +wire csrbank0_init_done_r; +reg csrbank0_init_done_re = 1'd0; +wire csrbank0_init_done_w; +reg csrbank0_init_done_we = 1'd0; +wire csrbank0_init_error_r; +reg csrbank0_init_error_re = 1'd0; +wire csrbank0_init_error_w; +reg csrbank0_init_error_we = 1'd0; +wire csrbank0_sel; +wire csrbank1_sel; +wire [3:0] csrbank2_dfii_control_r; +reg csrbank2_dfii_control_re = 1'd0; +wire [3:0] csrbank2_dfii_control_w; +reg csrbank2_dfii_control_we = 1'd0; +wire [14:0] csrbank2_dfii_pi0_address_r; +reg csrbank2_dfii_pi0_address_re = 1'd0; +wire [14:0] csrbank2_dfii_pi0_address_w; +reg csrbank2_dfii_pi0_address_we = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress_r; +reg csrbank2_dfii_pi0_baddress_re = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress_w; +reg csrbank2_dfii_pi0_baddress_we = 1'd0; +wire [7:0] csrbank2_dfii_pi0_command_r; +reg csrbank2_dfii_pi0_command_re = 1'd0; +wire [7:0] csrbank2_dfii_pi0_command_w; +reg csrbank2_dfii_pi0_command_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata_r; +reg csrbank2_dfii_pi0_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata_w; +reg csrbank2_dfii_pi0_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata_r; +reg csrbank2_dfii_pi0_wrdata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata_w; +reg csrbank2_dfii_pi0_wrdata_we = 1'd0; +wire [14:0] csrbank2_dfii_pi1_address_r; +reg csrbank2_dfii_pi1_address_re = 1'd0; +wire [14:0] csrbank2_dfii_pi1_address_w; +reg csrbank2_dfii_pi1_address_we = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress_r; +reg csrbank2_dfii_pi1_baddress_re = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress_w; +reg csrbank2_dfii_pi1_baddress_we = 1'd0; +wire [7:0] csrbank2_dfii_pi1_command_r; +reg csrbank2_dfii_pi1_command_re = 1'd0; +wire [7:0] csrbank2_dfii_pi1_command_w; +reg csrbank2_dfii_pi1_command_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata_r; +reg csrbank2_dfii_pi1_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata_w; +reg csrbank2_dfii_pi1_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata_r; +reg csrbank2_dfii_pi1_wrdata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata_w; +reg csrbank2_dfii_pi1_wrdata_we = 1'd0; +wire [14:0] csrbank2_dfii_pi2_address_r; +reg csrbank2_dfii_pi2_address_re = 1'd0; +wire [14:0] csrbank2_dfii_pi2_address_w; +reg csrbank2_dfii_pi2_address_we = 1'd0; +wire [2:0] csrbank2_dfii_pi2_baddress_r; +reg csrbank2_dfii_pi2_baddress_re = 1'd0; +wire [2:0] csrbank2_dfii_pi2_baddress_w; +reg csrbank2_dfii_pi2_baddress_we = 1'd0; +wire [7:0] csrbank2_dfii_pi2_command_r; +reg csrbank2_dfii_pi2_command_re = 1'd0; +wire [7:0] csrbank2_dfii_pi2_command_w; +reg csrbank2_dfii_pi2_command_we = 1'd0; +wire [31:0] csrbank2_dfii_pi2_rddata_r; +reg csrbank2_dfii_pi2_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi2_rddata_w; +reg csrbank2_dfii_pi2_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi2_wrdata_r; +reg csrbank2_dfii_pi2_wrdata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi2_wrdata_w; +reg csrbank2_dfii_pi2_wrdata_we = 1'd0; +wire [14:0] csrbank2_dfii_pi3_address_r; +reg csrbank2_dfii_pi3_address_re = 1'd0; +wire [14:0] csrbank2_dfii_pi3_address_w; +reg csrbank2_dfii_pi3_address_we = 1'd0; +wire [2:0] csrbank2_dfii_pi3_baddress_r; +reg csrbank2_dfii_pi3_baddress_re = 1'd0; +wire [2:0] csrbank2_dfii_pi3_baddress_w; +reg csrbank2_dfii_pi3_baddress_we = 1'd0; +wire [7:0] csrbank2_dfii_pi3_command_r; +reg csrbank2_dfii_pi3_command_re = 1'd0; +wire [7:0] csrbank2_dfii_pi3_command_w; +reg csrbank2_dfii_pi3_command_we = 1'd0; +wire [31:0] csrbank2_dfii_pi3_rddata_r; +reg csrbank2_dfii_pi3_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi3_rddata_w; +reg csrbank2_dfii_pi3_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi3_wrdata_r; +reg csrbank2_dfii_pi3_wrdata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi3_wrdata_w; +reg csrbank2_dfii_pi3_wrdata_we = 1'd0; +wire csrbank2_sel; +wire [31:0] dat_r; +wire [31:0] dat_w; +wire done; +reg error = 1'd0; +wire grant; +reg interface0_ack = 1'd0; +wire [29:0] interface0_adr; +wire [13:0] interface0_bank_bus_adr; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_re; +wire interface0_bank_bus_we; +wire [1:0] interface0_bte; +wire [2:0] interface0_cti; +wire interface0_cyc; +reg [31:0] interface0_dat_r = 32'd0; +wire [31:0] interface0_dat_w; +reg interface0_err = 1'd0; +wire [3:0] interface0_sel; +wire interface0_stb; +wire interface0_we; +reg [13:0] interface1_adr = 14'd0; +reg [13:0] interface1_adr_next_value2 = 14'd0; +reg interface1_adr_next_value_ce2 = 1'd0; +wire [13:0] interface1_bank_bus_adr; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_re; +wire interface1_bank_bus_we; +wire [31:0] interface1_dat_r; +reg [31:0] interface1_dat_w = 32'd0; +reg [31:0] interface1_dat_w_next_value0 = 32'd0; +reg interface1_dat_w_next_value_ce0 = 1'd0; +reg interface1_re = 1'd0; +reg interface1_re_next_value3 = 1'd0; +reg interface1_re_next_value_ce3 = 1'd0; +reg interface1_we = 1'd0; +reg interface1_we_next_value4 = 1'd0; +reg interface1_we_next_value_ce4 = 1'd0; +wire [13:0] interface2_bank_bus_adr; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_re; +wire interface2_bank_bus_we; +reg locked0 = 1'd0; +reg locked1 = 1'd0; +reg locked2 = 1'd0; +reg locked3 = 1'd0; +reg locked4 = 1'd0; +reg locked5 = 1'd0; +reg locked6 = 1'd0; +reg locked7 = 1'd0; +wire master; +reg [3:0] multiplexer_next_state = 4'd0; +reg [3:0] multiplexer_state = 4'd0; +reg new_master_rdata_valid0 = 1'd0; +reg new_master_rdata_valid1 = 1'd0; +reg new_master_rdata_valid2 = 1'd0; +reg new_master_rdata_valid3 = 1'd0; +reg new_master_rdata_valid4 = 1'd0; +reg new_master_rdata_valid5 = 1'd0; +reg new_master_rdata_valid6 = 1'd0; +reg new_master_rdata_valid7 = 1'd0; +reg new_master_rdata_valid8 = 1'd0; +reg new_master_wdata_ready0 = 1'd0; +reg new_master_wdata_ready1 = 1'd0; +reg [1:0] next_state = 2'd0; +wire por_clk; +wire re; +reg [1:0] refresher_next_state = 2'd0; +reg [1:0] refresher_state = 2'd0; +wire request; +wire reserved_r; +reg reserved_re = 1'd0; +reg reserved_w = 1'd0; +reg reserved_we = 1'd0; +reg [29:0] rhs_self0 = 30'd0; +reg [31:0] rhs_self1 = 32'd0; +reg [2:0] rhs_self10 = 3'd0; +reg rhs_self11 = 1'd0; +reg rhs_self12 = 1'd0; +reg rhs_self13 = 1'd0; +reg rhs_self14 = 1'd0; +reg [14:0] rhs_self15 = 15'd0; +reg [2:0] rhs_self16 = 3'd0; +reg rhs_self17 = 1'd0; +reg rhs_self18 = 1'd0; +reg rhs_self19 = 1'd0; +reg [3:0] rhs_self2 = 4'd0; +reg [21:0] rhs_self20 = 22'd0; +reg rhs_self21 = 1'd0; +reg rhs_self22 = 1'd0; +reg [21:0] rhs_self23 = 22'd0; +reg rhs_self24 = 1'd0; +reg rhs_self25 = 1'd0; +reg [21:0] rhs_self26 = 22'd0; +reg rhs_self27 = 1'd0; +reg rhs_self28 = 1'd0; +reg [21:0] rhs_self29 = 22'd0; +reg rhs_self3 = 1'd0; +reg rhs_self30 = 1'd0; +reg rhs_self31 = 1'd0; +reg [21:0] rhs_self32 = 22'd0; +reg rhs_self33 = 1'd0; +reg rhs_self34 = 1'd0; +reg [21:0] rhs_self35 = 22'd0; +reg rhs_self36 = 1'd0; +reg rhs_self37 = 1'd0; +reg [21:0] rhs_self38 = 22'd0; +reg rhs_self39 = 1'd0; +reg rhs_self4 = 1'd0; +reg rhs_self40 = 1'd0; +reg [21:0] rhs_self41 = 22'd0; +reg rhs_self42 = 1'd0; +reg rhs_self43 = 1'd0; +reg rhs_self5 = 1'd0; +reg [2:0] rhs_self6 = 3'd0; +reg [1:0] rhs_self7 = 2'd0; +reg rhs_self8 = 1'd0; +reg [14:0] rhs_self9 = 15'd0; +wire roundrobin0_ce; +wire roundrobin0_grant; +wire roundrobin0_request; +wire roundrobin1_ce; +wire roundrobin1_grant; +wire roundrobin1_request; +wire roundrobin2_ce; +wire roundrobin2_grant; +wire roundrobin2_request; +wire roundrobin3_ce; +wire roundrobin3_grant; +wire roundrobin3_request; +wire roundrobin4_ce; +wire roundrobin4_grant; +wire roundrobin4_request; +wire roundrobin5_ce; +wire roundrobin5_grant; +wire roundrobin5_request; +wire roundrobin6_ce; +wire roundrobin6_grant; +wire roundrobin6_request; +wire roundrobin7_ce; +wire roundrobin7_grant; +wire roundrobin7_request; +reg selected_r = 1'd0; +reg selected_r_next_value1 = 1'd0; +reg selected_r_next_value_ce1 = 1'd0; +reg [2:0] self0 = 3'd0; +reg [14:0] self1 = 15'd0; +reg self10 = 1'd0; +reg self11 = 1'd0; +reg self12 = 1'd0; +reg self13 = 1'd0; +reg [2:0] self14 = 3'd0; +reg [14:0] self15 = 15'd0; +reg self16 = 1'd0; +reg self17 = 1'd0; +reg self18 = 1'd0; +reg self19 = 1'd0; +reg self2 = 1'd0; +reg self20 = 1'd0; +reg [2:0] self21 = 3'd0; +reg [14:0] self22 = 15'd0; +reg self23 = 1'd0; +reg self24 = 1'd0; +reg self25 = 1'd0; +reg self26 = 1'd0; +reg self27 = 1'd0; +reg self3 = 1'd0; +reg self4 = 1'd0; +reg self5 = 1'd0; +reg self6 = 1'd0; +reg [2:0] self7 = 3'd0; +reg [14:0] self8 = 15'd0; +reg self9 = 1'd0; +reg shared_ack = 1'd0; +wire [29:0] shared_adr; +wire [1:0] shared_bte; +wire [2:0] shared_cti; +wire shared_cyc; +reg [31:0] shared_dat_r = 32'd0; +wire [31:0] shared_dat_w; +wire shared_err; +wire [3:0] shared_sel; +wire shared_stb; +wire shared_we; +reg slaves = 1'd0; +wire [25:0] slice_proxy0; +wire [25:0] slice_proxy1; +wire [25:0] slice_proxy10; +wire [25:0] slice_proxy11; +wire [25:0] slice_proxy12; +wire [25:0] slice_proxy13; +wire [25:0] slice_proxy14; +wire [25:0] slice_proxy15; +wire [25:0] slice_proxy2; +wire [25:0] slice_proxy3; +wire [25:0] slice_proxy4; +wire [25:0] slice_proxy5; +wire [25:0] slice_proxy6; +wire [25:0] slice_proxy7; +wire [25:0] slice_proxy8; +wire [25:0] slice_proxy9; +reg [3:0] soc_ddrphy_activates0 = 4'd0; +reg [3:0] soc_ddrphy_activates1 = 4'd0; +reg [3:0] soc_ddrphy_activates2 = 4'd0; +reg [3:0] soc_ddrphy_activates3 = 4'd0; +reg [3:0] soc_ddrphy_activates4 = 4'd0; +reg [3:0] soc_ddrphy_activates5 = 4'd0; +reg [3:0] soc_ddrphy_activates6 = 4'd0; +reg [3:0] soc_ddrphy_activates7 = 4'd0; +reg soc_ddrphy_bank_write0 = 1'd0; +reg soc_ddrphy_bank_write1 = 1'd0; +reg soc_ddrphy_bank_write2 = 1'd0; +reg soc_ddrphy_bank_write3 = 1'd0; +reg soc_ddrphy_bank_write4 = 1'd0; +reg soc_ddrphy_bank_write5 = 1'd0; +reg soc_ddrphy_bank_write6 = 1'd0; +reg soc_ddrphy_bank_write7 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col0 = 10'd0; +reg [9:0] soc_ddrphy_bank_write_col1 = 10'd0; +reg [9:0] soc_ddrphy_bank_write_col2 = 10'd0; +reg [9:0] soc_ddrphy_bank_write_col3 = 10'd0; +reg [9:0] soc_ddrphy_bank_write_col4 = 10'd0; +reg [9:0] soc_ddrphy_bank_write_col5 = 10'd0; +reg [9:0] soc_ddrphy_bank_write_col6 = 10'd0; +reg [9:0] soc_ddrphy_bank_write_col7 = 10'd0; +reg soc_ddrphy_bankmodel0_activate = 1'd0; +reg [14:0] soc_ddrphy_bankmodel0_activate_row = 15'd0; +reg soc_ddrphy_bankmodel0_active = 1'd0; +reg soc_ddrphy_bankmodel0_precharge = 1'd0; +wire [21:0] soc_ddrphy_bankmodel0_rdaddr; +reg soc_ddrphy_bankmodel0_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel0_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel0_read_data = 128'd0; +reg [21:0] soc_ddrphy_bankmodel0_read_port_adr = 22'd0; +wire [127:0] soc_ddrphy_bankmodel0_read_port_dat_r; +reg [14:0] soc_ddrphy_bankmodel0_row = 15'd0; +wire [21:0] soc_ddrphy_bankmodel0_wraddr; +wire soc_ddrphy_bankmodel0_write; +wire [9:0] soc_ddrphy_bankmodel0_write_col; +wire [127:0] soc_ddrphy_bankmodel0_write_data; +wire [15:0] soc_ddrphy_bankmodel0_write_mask; +reg [21:0] soc_ddrphy_bankmodel0_write_port_adr = 22'd0; +wire [127:0] soc_ddrphy_bankmodel0_write_port_dat_r; +reg [127:0] soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0; +reg [15:0] soc_ddrphy_bankmodel0_write_port_we = 16'd0; +reg soc_ddrphy_bankmodel1_activate = 1'd0; +reg [14:0] soc_ddrphy_bankmodel1_activate_row = 15'd0; +reg soc_ddrphy_bankmodel1_active = 1'd0; +reg soc_ddrphy_bankmodel1_precharge = 1'd0; +wire [21:0] soc_ddrphy_bankmodel1_rdaddr; +reg soc_ddrphy_bankmodel1_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel1_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel1_read_data = 128'd0; +reg [21:0] soc_ddrphy_bankmodel1_read_port_adr = 22'd0; +wire [127:0] soc_ddrphy_bankmodel1_read_port_dat_r; +reg [14:0] soc_ddrphy_bankmodel1_row = 15'd0; +wire [21:0] soc_ddrphy_bankmodel1_wraddr; +wire soc_ddrphy_bankmodel1_write; +wire [9:0] soc_ddrphy_bankmodel1_write_col; +wire [127:0] soc_ddrphy_bankmodel1_write_data; +wire [15:0] soc_ddrphy_bankmodel1_write_mask; +reg [21:0] soc_ddrphy_bankmodel1_write_port_adr = 22'd0; +wire [127:0] soc_ddrphy_bankmodel1_write_port_dat_r; +reg [127:0] soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0; +reg [15:0] soc_ddrphy_bankmodel1_write_port_we = 16'd0; +reg soc_ddrphy_bankmodel2_activate = 1'd0; +reg [14:0] soc_ddrphy_bankmodel2_activate_row = 15'd0; +reg soc_ddrphy_bankmodel2_active = 1'd0; +reg soc_ddrphy_bankmodel2_precharge = 1'd0; +wire [21:0] soc_ddrphy_bankmodel2_rdaddr; +reg soc_ddrphy_bankmodel2_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel2_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel2_read_data = 128'd0; +reg [21:0] soc_ddrphy_bankmodel2_read_port_adr = 22'd0; +wire [127:0] soc_ddrphy_bankmodel2_read_port_dat_r; +reg [14:0] soc_ddrphy_bankmodel2_row = 15'd0; +wire [21:0] soc_ddrphy_bankmodel2_wraddr; +wire soc_ddrphy_bankmodel2_write; +wire [9:0] soc_ddrphy_bankmodel2_write_col; +wire [127:0] soc_ddrphy_bankmodel2_write_data; +wire [15:0] soc_ddrphy_bankmodel2_write_mask; +reg [21:0] soc_ddrphy_bankmodel2_write_port_adr = 22'd0; +wire [127:0] soc_ddrphy_bankmodel2_write_port_dat_r; +reg [127:0] soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0; +reg [15:0] soc_ddrphy_bankmodel2_write_port_we = 16'd0; +reg soc_ddrphy_bankmodel3_activate = 1'd0; +reg [14:0] soc_ddrphy_bankmodel3_activate_row = 15'd0; +reg soc_ddrphy_bankmodel3_active = 1'd0; +reg soc_ddrphy_bankmodel3_precharge = 1'd0; +wire [21:0] soc_ddrphy_bankmodel3_rdaddr; +reg soc_ddrphy_bankmodel3_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel3_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel3_read_data = 128'd0; +reg [21:0] soc_ddrphy_bankmodel3_read_port_adr = 22'd0; +wire [127:0] soc_ddrphy_bankmodel3_read_port_dat_r; +reg [14:0] soc_ddrphy_bankmodel3_row = 15'd0; +wire [21:0] soc_ddrphy_bankmodel3_wraddr; +wire soc_ddrphy_bankmodel3_write; +wire [9:0] soc_ddrphy_bankmodel3_write_col; +wire [127:0] soc_ddrphy_bankmodel3_write_data; +wire [15:0] soc_ddrphy_bankmodel3_write_mask; +reg [21:0] soc_ddrphy_bankmodel3_write_port_adr = 22'd0; +wire [127:0] soc_ddrphy_bankmodel3_write_port_dat_r; +reg [127:0] soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0; +reg [15:0] soc_ddrphy_bankmodel3_write_port_we = 16'd0; +reg soc_ddrphy_bankmodel4_activate = 1'd0; +reg [14:0] soc_ddrphy_bankmodel4_activate_row = 15'd0; +reg soc_ddrphy_bankmodel4_active = 1'd0; +reg soc_ddrphy_bankmodel4_precharge = 1'd0; +wire [21:0] soc_ddrphy_bankmodel4_rdaddr; +reg soc_ddrphy_bankmodel4_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel4_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel4_read_data = 128'd0; +reg [21:0] soc_ddrphy_bankmodel4_read_port_adr = 22'd0; +wire [127:0] soc_ddrphy_bankmodel4_read_port_dat_r; +reg [14:0] soc_ddrphy_bankmodel4_row = 15'd0; +wire [21:0] soc_ddrphy_bankmodel4_wraddr; +wire soc_ddrphy_bankmodel4_write; +wire [9:0] soc_ddrphy_bankmodel4_write_col; +wire [127:0] soc_ddrphy_bankmodel4_write_data; +wire [15:0] soc_ddrphy_bankmodel4_write_mask; +reg [21:0] soc_ddrphy_bankmodel4_write_port_adr = 22'd0; +wire [127:0] soc_ddrphy_bankmodel4_write_port_dat_r; +reg [127:0] soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0; +reg [15:0] soc_ddrphy_bankmodel4_write_port_we = 16'd0; +reg soc_ddrphy_bankmodel5_activate = 1'd0; +reg [14:0] soc_ddrphy_bankmodel5_activate_row = 15'd0; +reg soc_ddrphy_bankmodel5_active = 1'd0; +reg soc_ddrphy_bankmodel5_precharge = 1'd0; +wire [21:0] soc_ddrphy_bankmodel5_rdaddr; +reg soc_ddrphy_bankmodel5_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel5_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel5_read_data = 128'd0; +reg [21:0] soc_ddrphy_bankmodel5_read_port_adr = 22'd0; +wire [127:0] soc_ddrphy_bankmodel5_read_port_dat_r; +reg [14:0] soc_ddrphy_bankmodel5_row = 15'd0; +wire [21:0] soc_ddrphy_bankmodel5_wraddr; +wire soc_ddrphy_bankmodel5_write; +wire [9:0] soc_ddrphy_bankmodel5_write_col; +wire [127:0] soc_ddrphy_bankmodel5_write_data; +wire [15:0] soc_ddrphy_bankmodel5_write_mask; +reg [21:0] soc_ddrphy_bankmodel5_write_port_adr = 22'd0; +wire [127:0] soc_ddrphy_bankmodel5_write_port_dat_r; +reg [127:0] soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0; +reg [15:0] soc_ddrphy_bankmodel5_write_port_we = 16'd0; +reg soc_ddrphy_bankmodel6_activate = 1'd0; +reg [14:0] soc_ddrphy_bankmodel6_activate_row = 15'd0; +reg soc_ddrphy_bankmodel6_active = 1'd0; +reg soc_ddrphy_bankmodel6_precharge = 1'd0; +wire [21:0] soc_ddrphy_bankmodel6_rdaddr; +reg soc_ddrphy_bankmodel6_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel6_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel6_read_data = 128'd0; +reg [21:0] soc_ddrphy_bankmodel6_read_port_adr = 22'd0; +wire [127:0] soc_ddrphy_bankmodel6_read_port_dat_r; +reg [14:0] soc_ddrphy_bankmodel6_row = 15'd0; +wire [21:0] soc_ddrphy_bankmodel6_wraddr; +wire soc_ddrphy_bankmodel6_write; +wire [9:0] soc_ddrphy_bankmodel6_write_col; +wire [127:0] soc_ddrphy_bankmodel6_write_data; +wire [15:0] soc_ddrphy_bankmodel6_write_mask; +reg [21:0] soc_ddrphy_bankmodel6_write_port_adr = 22'd0; +wire [127:0] soc_ddrphy_bankmodel6_write_port_dat_r; +reg [127:0] soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0; +reg [15:0] soc_ddrphy_bankmodel6_write_port_we = 16'd0; +reg soc_ddrphy_bankmodel7_activate = 1'd0; +reg [14:0] soc_ddrphy_bankmodel7_activate_row = 15'd0; +reg soc_ddrphy_bankmodel7_active = 1'd0; +reg soc_ddrphy_bankmodel7_precharge = 1'd0; +wire [21:0] soc_ddrphy_bankmodel7_rdaddr; +reg soc_ddrphy_bankmodel7_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel7_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel7_read_data = 128'd0; +reg [21:0] soc_ddrphy_bankmodel7_read_port_adr = 22'd0; +wire [127:0] soc_ddrphy_bankmodel7_read_port_dat_r; +reg [14:0] soc_ddrphy_bankmodel7_row = 15'd0; +wire [21:0] soc_ddrphy_bankmodel7_wraddr; +wire soc_ddrphy_bankmodel7_write; +wire [9:0] soc_ddrphy_bankmodel7_write_col; +wire [127:0] soc_ddrphy_bankmodel7_write_data; +wire [15:0] soc_ddrphy_bankmodel7_write_mask; +reg [21:0] soc_ddrphy_bankmodel7_write_port_adr = 22'd0; +wire [127:0] soc_ddrphy_bankmodel7_write_port_dat_r; +reg [127:0] soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0; +reg [15:0] soc_ddrphy_bankmodel7_write_port_we = 16'd0; +wire soc_ddrphy_banks_read; +wire [127:0] soc_ddrphy_banks_read_data; +wire soc_ddrphy_dfi_p0_act_n; +wire [14:0] soc_ddrphy_dfi_p0_address; +wire [2:0] soc_ddrphy_dfi_p0_bank; +wire soc_ddrphy_dfi_p0_cas_n; +wire soc_ddrphy_dfi_p0_cke; +wire soc_ddrphy_dfi_p0_cs_n; +wire soc_ddrphy_dfi_p0_odt; +wire soc_ddrphy_dfi_p0_ras_n; +wire [31:0] soc_ddrphy_dfi_p0_rddata; +wire soc_ddrphy_dfi_p0_rddata_en; +wire soc_ddrphy_dfi_p0_rddata_valid; +wire soc_ddrphy_dfi_p0_reset_n; +wire soc_ddrphy_dfi_p0_we_n; +wire [31:0] soc_ddrphy_dfi_p0_wrdata; +wire soc_ddrphy_dfi_p0_wrdata_en; +wire [3:0] soc_ddrphy_dfi_p0_wrdata_mask; +wire soc_ddrphy_dfi_p1_act_n; +wire [14:0] soc_ddrphy_dfi_p1_address; +wire [2:0] soc_ddrphy_dfi_p1_bank; +wire soc_ddrphy_dfi_p1_cas_n; +wire soc_ddrphy_dfi_p1_cke; +wire soc_ddrphy_dfi_p1_cs_n; +wire soc_ddrphy_dfi_p1_odt; +wire soc_ddrphy_dfi_p1_ras_n; +wire [31:0] soc_ddrphy_dfi_p1_rddata; +wire soc_ddrphy_dfi_p1_rddata_en; +wire soc_ddrphy_dfi_p1_rddata_valid; +wire soc_ddrphy_dfi_p1_reset_n; +wire soc_ddrphy_dfi_p1_we_n; +wire [31:0] soc_ddrphy_dfi_p1_wrdata; +wire soc_ddrphy_dfi_p1_wrdata_en; +wire [3:0] soc_ddrphy_dfi_p1_wrdata_mask; +wire soc_ddrphy_dfi_p2_act_n; +wire [14:0] soc_ddrphy_dfi_p2_address; +wire [2:0] soc_ddrphy_dfi_p2_bank; +wire soc_ddrphy_dfi_p2_cas_n; +wire soc_ddrphy_dfi_p2_cke; +wire soc_ddrphy_dfi_p2_cs_n; +wire soc_ddrphy_dfi_p2_odt; +wire soc_ddrphy_dfi_p2_ras_n; +wire [31:0] soc_ddrphy_dfi_p2_rddata; +wire soc_ddrphy_dfi_p2_rddata_en; +wire soc_ddrphy_dfi_p2_rddata_valid; +wire soc_ddrphy_dfi_p2_reset_n; +wire soc_ddrphy_dfi_p2_we_n; +wire [31:0] soc_ddrphy_dfi_p2_wrdata; +wire soc_ddrphy_dfi_p2_wrdata_en; +wire [3:0] soc_ddrphy_dfi_p2_wrdata_mask; +wire soc_ddrphy_dfi_p3_act_n; +wire [14:0] soc_ddrphy_dfi_p3_address; +wire [2:0] soc_ddrphy_dfi_p3_bank; +wire soc_ddrphy_dfi_p3_cas_n; +wire soc_ddrphy_dfi_p3_cke; +wire soc_ddrphy_dfi_p3_cs_n; +wire soc_ddrphy_dfi_p3_odt; +wire soc_ddrphy_dfi_p3_ras_n; +wire [31:0] soc_ddrphy_dfi_p3_rddata; +wire soc_ddrphy_dfi_p3_rddata_en; +wire soc_ddrphy_dfi_p3_rddata_valid; +wire soc_ddrphy_dfi_p3_reset_n; +wire soc_ddrphy_dfi_p3_we_n; +wire [31:0] soc_ddrphy_dfi_p3_wrdata; +wire soc_ddrphy_dfi_p3_wrdata_en; +wire [3:0] soc_ddrphy_dfi_p3_wrdata_mask; +reg soc_ddrphy_dfiphasemodel0_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel0_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel0_read = 1'd0; +reg soc_ddrphy_dfiphasemodel0_write = 1'd0; +reg soc_ddrphy_dfiphasemodel1_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel1_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel1_read = 1'd0; +reg soc_ddrphy_dfiphasemodel1_write = 1'd0; +reg soc_ddrphy_dfiphasemodel2_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel2_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel2_read = 1'd0; +reg soc_ddrphy_dfiphasemodel2_write = 1'd0; +reg soc_ddrphy_dfiphasemodel3_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel3_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel3_read = 1'd0; +reg soc_ddrphy_dfiphasemodel3_write = 1'd0; +reg soc_ddrphy_new_bank_write0 = 1'd0; +reg soc_ddrphy_new_bank_write1 = 1'd0; +reg soc_ddrphy_new_bank_write2 = 1'd0; +reg soc_ddrphy_new_bank_write3 = 1'd0; +reg soc_ddrphy_new_bank_write4 = 1'd0; +reg soc_ddrphy_new_bank_write5 = 1'd0; +reg soc_ddrphy_new_bank_write6 = 1'd0; +reg soc_ddrphy_new_bank_write7 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col0 = 10'd0; +reg [9:0] soc_ddrphy_new_bank_write_col1 = 10'd0; +reg [9:0] soc_ddrphy_new_bank_write_col2 = 10'd0; +reg [9:0] soc_ddrphy_new_bank_write_col3 = 10'd0; +reg [9:0] soc_ddrphy_new_bank_write_col4 = 10'd0; +reg [9:0] soc_ddrphy_new_bank_write_col5 = 10'd0; +reg [9:0] soc_ddrphy_new_bank_write_col6 = 10'd0; +reg [9:0] soc_ddrphy_new_bank_write_col7 = 10'd0; +reg soc_ddrphy_new_banks_read0 = 1'd0; +reg soc_ddrphy_new_banks_read1 = 1'd0; +reg soc_ddrphy_new_banks_read2 = 1'd0; +reg soc_ddrphy_new_banks_read3 = 1'd0; +reg soc_ddrphy_new_banks_read4 = 1'd0; +reg soc_ddrphy_new_banks_read5 = 1'd0; +reg soc_ddrphy_new_banks_read6 = 1'd0; +reg soc_ddrphy_new_banks_read7 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data0 = 128'd0; +reg [127:0] soc_ddrphy_new_banks_read_data1 = 128'd0; +reg [127:0] soc_ddrphy_new_banks_read_data2 = 128'd0; +reg [127:0] soc_ddrphy_new_banks_read_data3 = 128'd0; +reg [127:0] soc_ddrphy_new_banks_read_data4 = 128'd0; +reg [127:0] soc_ddrphy_new_banks_read_data5 = 128'd0; +reg [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0; +reg [127:0] soc_ddrphy_new_banks_read_data7 = 128'd0; +reg [3:0] soc_ddrphy_precharges0 = 4'd0; +reg [3:0] soc_ddrphy_precharges1 = 4'd0; +reg [3:0] soc_ddrphy_precharges2 = 4'd0; +reg [3:0] soc_ddrphy_precharges3 = 4'd0; +reg [3:0] soc_ddrphy_precharges4 = 4'd0; +reg [3:0] soc_ddrphy_precharges5 = 4'd0; +reg [3:0] soc_ddrphy_precharges6 = 4'd0; +reg [3:0] soc_ddrphy_precharges7 = 4'd0; +reg [3:0] soc_ddrphy_reads0 = 4'd0; +reg [3:0] soc_ddrphy_reads1 = 4'd0; +reg [3:0] soc_ddrphy_reads2 = 4'd0; +reg [3:0] soc_ddrphy_reads3 = 4'd0; +reg [3:0] soc_ddrphy_reads4 = 4'd0; +reg [3:0] soc_ddrphy_reads5 = 4'd0; +reg [3:0] soc_ddrphy_reads6 = 4'd0; +reg [3:0] soc_ddrphy_reads7 = 4'd0; +reg [3:0] soc_ddrphy_writes0 = 4'd0; +reg [3:0] soc_ddrphy_writes1 = 4'd0; +reg [3:0] soc_ddrphy_writes2 = 4'd0; +reg [3:0] soc_ddrphy_writes3 = 4'd0; +reg [3:0] soc_ddrphy_writes4 = 4'd0; +reg [3:0] soc_ddrphy_writes5 = 4'd0; +reg [3:0] soc_ddrphy_writes6 = 4'd0; +reg [3:0] soc_ddrphy_writes7 = 4'd0; +reg soc_init_done_storage = 1'd0; +reg soc_init_done_wr_stb = 1'd0; +reg soc_init_error_storage = 1'd0; +reg soc_init_error_wr_stb = 1'd0; +reg soc_int_rst = 1'd1; +reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0; +reg [14:0] soc_litedramcore_bankmachine0_cmd_payload_a = 15'd0; +wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba; +reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_consume = 3'd0; +wire soc_litedramcore_bankmachine0_do_read; +wire soc_litedramcore_bankmachine0_fifo_in_first; +wire soc_litedramcore_bankmachine0_fifo_in_last; +wire [21:0] soc_litedramcore_bankmachine0_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine0_fifo_in_payload_we; +wire soc_litedramcore_bankmachine0_fifo_out_first; +wire soc_litedramcore_bankmachine0_fifo_out_last; +wire [21:0] soc_litedramcore_bankmachine0_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine0_fifo_out_payload_we; +reg [3:0] soc_litedramcore_bankmachine0_level = 4'd0; +wire soc_litedramcore_bankmachine0_pipe_valid_sink_first; +wire soc_litedramcore_bankmachine0_pipe_valid_sink_last; +wire [21:0] soc_litedramcore_bankmachine0_pipe_valid_sink_payload_addr; +wire soc_litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire soc_litedramcore_bankmachine0_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine0_pipe_valid_sink_valid; +reg soc_litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; +reg soc_litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; +reg [21:0] soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0; +reg soc_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +wire soc_litedramcore_bankmachine0_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_produce = 3'd0; +wire [2:0] soc_litedramcore_bankmachine0_rdport_adr; +wire [24:0] soc_litedramcore_bankmachine0_rdport_dat_r; +reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; +wire soc_litedramcore_bankmachine0_refresh_req; +reg soc_litedramcore_bankmachine0_replace = 1'd0; +wire [21:0] soc_litedramcore_bankmachine0_req_addr; +wire soc_litedramcore_bankmachine0_req_lock; +reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine0_req_ready; +wire soc_litedramcore_bankmachine0_req_valid; +reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +wire soc_litedramcore_bankmachine0_req_we; +reg [14:0] soc_litedramcore_bankmachine0_row = 15'd0; +reg soc_litedramcore_bankmachine0_row_close = 1'd0; +reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine0_row_hit; +reg soc_litedramcore_bankmachine0_row_open = 1'd0; +reg soc_litedramcore_bankmachine0_row_opened = 1'd0; +reg soc_litedramcore_bankmachine0_sink_first = 1'd0; +reg soc_litedramcore_bankmachine0_sink_last = 1'd0; +wire [21:0] soc_litedramcore_bankmachine0_sink_payload_addr; +wire soc_litedramcore_bankmachine0_sink_payload_we; +wire soc_litedramcore_bankmachine0_sink_ready; +wire soc_litedramcore_bankmachine0_sink_sink_first; +wire soc_litedramcore_bankmachine0_sink_sink_last; +wire [21:0] soc_litedramcore_bankmachine0_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine0_sink_sink_payload_we; +wire soc_litedramcore_bankmachine0_sink_sink_ready; +wire soc_litedramcore_bankmachine0_sink_sink_valid; +wire soc_litedramcore_bankmachine0_sink_valid; +wire soc_litedramcore_bankmachine0_source_first; +wire soc_litedramcore_bankmachine0_source_last; +wire [21:0] soc_litedramcore_bankmachine0_source_payload_addr; +wire soc_litedramcore_bankmachine0_source_payload_we; +wire soc_litedramcore_bankmachine0_source_ready; +wire soc_litedramcore_bankmachine0_source_source_first; +wire soc_litedramcore_bankmachine0_source_source_last; +wire [21:0] soc_litedramcore_bankmachine0_source_source_payload_addr; +wire soc_litedramcore_bankmachine0_source_source_payload_we; +wire soc_litedramcore_bankmachine0_source_source_ready; +wire soc_litedramcore_bankmachine0_source_source_valid; +wire soc_litedramcore_bankmachine0_source_valid; +wire [24:0] soc_litedramcore_bankmachine0_syncfifo0_din; +wire [24:0] soc_litedramcore_bankmachine0_syncfifo0_dout; +wire soc_litedramcore_bankmachine0_syncfifo0_re; +wire soc_litedramcore_bankmachine0_syncfifo0_readable; +wire soc_litedramcore_bankmachine0_syncfifo0_we; +wire soc_litedramcore_bankmachine0_syncfifo0_writable; +reg [1:0] soc_litedramcore_bankmachine0_trascon_count = 2'd0; +reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine0_trascon_valid; +reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0; +wire soc_litedramcore_bankmachine0_trccon_valid; +reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +wire soc_litedramcore_bankmachine0_twtpcon_valid; +reg [2:0] soc_litedramcore_bankmachine0_wrport_adr = 3'd0; +wire [24:0] soc_litedramcore_bankmachine0_wrport_dat_r; +wire [24:0] soc_litedramcore_bankmachine0_wrport_dat_w; +wire soc_litedramcore_bankmachine0_wrport_we; +reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0; +reg [14:0] soc_litedramcore_bankmachine1_cmd_payload_a = 15'd0; +wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba; +reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_consume = 3'd0; +wire soc_litedramcore_bankmachine1_do_read; +wire soc_litedramcore_bankmachine1_fifo_in_first; +wire soc_litedramcore_bankmachine1_fifo_in_last; +wire [21:0] soc_litedramcore_bankmachine1_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine1_fifo_in_payload_we; +wire soc_litedramcore_bankmachine1_fifo_out_first; +wire soc_litedramcore_bankmachine1_fifo_out_last; +wire [21:0] soc_litedramcore_bankmachine1_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine1_fifo_out_payload_we; +reg [3:0] soc_litedramcore_bankmachine1_level = 4'd0; +wire soc_litedramcore_bankmachine1_pipe_valid_sink_first; +wire soc_litedramcore_bankmachine1_pipe_valid_sink_last; +wire [21:0] soc_litedramcore_bankmachine1_pipe_valid_sink_payload_addr; +wire soc_litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire soc_litedramcore_bankmachine1_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine1_pipe_valid_sink_valid; +reg soc_litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; +reg soc_litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; +reg [21:0] soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0; +reg soc_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +wire soc_litedramcore_bankmachine1_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_produce = 3'd0; +wire [2:0] soc_litedramcore_bankmachine1_rdport_adr; +wire [24:0] soc_litedramcore_bankmachine1_rdport_dat_r; +reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; +wire soc_litedramcore_bankmachine1_refresh_req; +reg soc_litedramcore_bankmachine1_replace = 1'd0; +wire [21:0] soc_litedramcore_bankmachine1_req_addr; +wire soc_litedramcore_bankmachine1_req_lock; +reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine1_req_ready; +wire soc_litedramcore_bankmachine1_req_valid; +reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +wire soc_litedramcore_bankmachine1_req_we; +reg [14:0] soc_litedramcore_bankmachine1_row = 15'd0; +reg soc_litedramcore_bankmachine1_row_close = 1'd0; +reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine1_row_hit; +reg soc_litedramcore_bankmachine1_row_open = 1'd0; +reg soc_litedramcore_bankmachine1_row_opened = 1'd0; +reg soc_litedramcore_bankmachine1_sink_first = 1'd0; +reg soc_litedramcore_bankmachine1_sink_last = 1'd0; +wire [21:0] soc_litedramcore_bankmachine1_sink_payload_addr; +wire soc_litedramcore_bankmachine1_sink_payload_we; +wire soc_litedramcore_bankmachine1_sink_ready; +wire soc_litedramcore_bankmachine1_sink_sink_first; +wire soc_litedramcore_bankmachine1_sink_sink_last; +wire [21:0] soc_litedramcore_bankmachine1_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine1_sink_sink_payload_we; +wire soc_litedramcore_bankmachine1_sink_sink_ready; +wire soc_litedramcore_bankmachine1_sink_sink_valid; +wire soc_litedramcore_bankmachine1_sink_valid; +wire soc_litedramcore_bankmachine1_source_first; +wire soc_litedramcore_bankmachine1_source_last; +wire [21:0] soc_litedramcore_bankmachine1_source_payload_addr; +wire soc_litedramcore_bankmachine1_source_payload_we; +wire soc_litedramcore_bankmachine1_source_ready; +wire soc_litedramcore_bankmachine1_source_source_first; +wire soc_litedramcore_bankmachine1_source_source_last; +wire [21:0] soc_litedramcore_bankmachine1_source_source_payload_addr; +wire soc_litedramcore_bankmachine1_source_source_payload_we; +wire soc_litedramcore_bankmachine1_source_source_ready; +wire soc_litedramcore_bankmachine1_source_source_valid; +wire soc_litedramcore_bankmachine1_source_valid; +wire [24:0] soc_litedramcore_bankmachine1_syncfifo1_din; +wire [24:0] soc_litedramcore_bankmachine1_syncfifo1_dout; +wire soc_litedramcore_bankmachine1_syncfifo1_re; +wire soc_litedramcore_bankmachine1_syncfifo1_readable; +wire soc_litedramcore_bankmachine1_syncfifo1_we; +wire soc_litedramcore_bankmachine1_syncfifo1_writable; +reg [1:0] soc_litedramcore_bankmachine1_trascon_count = 2'd0; +reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine1_trascon_valid; +reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0; +wire soc_litedramcore_bankmachine1_trccon_valid; +reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +wire soc_litedramcore_bankmachine1_twtpcon_valid; +reg [2:0] soc_litedramcore_bankmachine1_wrport_adr = 3'd0; +wire [24:0] soc_litedramcore_bankmachine1_wrport_dat_r; +wire [24:0] soc_litedramcore_bankmachine1_wrport_dat_w; +wire soc_litedramcore_bankmachine1_wrport_we; +reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0; +reg [14:0] soc_litedramcore_bankmachine2_cmd_payload_a = 15'd0; +wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba; +reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_consume = 3'd0; +wire soc_litedramcore_bankmachine2_do_read; +wire soc_litedramcore_bankmachine2_fifo_in_first; +wire soc_litedramcore_bankmachine2_fifo_in_last; +wire [21:0] soc_litedramcore_bankmachine2_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine2_fifo_in_payload_we; +wire soc_litedramcore_bankmachine2_fifo_out_first; +wire soc_litedramcore_bankmachine2_fifo_out_last; +wire [21:0] soc_litedramcore_bankmachine2_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine2_fifo_out_payload_we; +reg [3:0] soc_litedramcore_bankmachine2_level = 4'd0; +wire soc_litedramcore_bankmachine2_pipe_valid_sink_first; +wire soc_litedramcore_bankmachine2_pipe_valid_sink_last; +wire [21:0] soc_litedramcore_bankmachine2_pipe_valid_sink_payload_addr; +wire soc_litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire soc_litedramcore_bankmachine2_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine2_pipe_valid_sink_valid; +reg soc_litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; +reg soc_litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; +reg [21:0] soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0; +reg soc_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +wire soc_litedramcore_bankmachine2_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_produce = 3'd0; +wire [2:0] soc_litedramcore_bankmachine2_rdport_adr; +wire [24:0] soc_litedramcore_bankmachine2_rdport_dat_r; +reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; +wire soc_litedramcore_bankmachine2_refresh_req; +reg soc_litedramcore_bankmachine2_replace = 1'd0; +wire [21:0] soc_litedramcore_bankmachine2_req_addr; +wire soc_litedramcore_bankmachine2_req_lock; +reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine2_req_ready; +wire soc_litedramcore_bankmachine2_req_valid; +reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +wire soc_litedramcore_bankmachine2_req_we; +reg [14:0] soc_litedramcore_bankmachine2_row = 15'd0; +reg soc_litedramcore_bankmachine2_row_close = 1'd0; +reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine2_row_hit; +reg soc_litedramcore_bankmachine2_row_open = 1'd0; +reg soc_litedramcore_bankmachine2_row_opened = 1'd0; +reg soc_litedramcore_bankmachine2_sink_first = 1'd0; +reg soc_litedramcore_bankmachine2_sink_last = 1'd0; +wire [21:0] soc_litedramcore_bankmachine2_sink_payload_addr; +wire soc_litedramcore_bankmachine2_sink_payload_we; +wire soc_litedramcore_bankmachine2_sink_ready; +wire soc_litedramcore_bankmachine2_sink_sink_first; +wire soc_litedramcore_bankmachine2_sink_sink_last; +wire [21:0] soc_litedramcore_bankmachine2_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine2_sink_sink_payload_we; +wire soc_litedramcore_bankmachine2_sink_sink_ready; +wire soc_litedramcore_bankmachine2_sink_sink_valid; +wire soc_litedramcore_bankmachine2_sink_valid; +wire soc_litedramcore_bankmachine2_source_first; +wire soc_litedramcore_bankmachine2_source_last; +wire [21:0] soc_litedramcore_bankmachine2_source_payload_addr; +wire soc_litedramcore_bankmachine2_source_payload_we; +wire soc_litedramcore_bankmachine2_source_ready; +wire soc_litedramcore_bankmachine2_source_source_first; +wire soc_litedramcore_bankmachine2_source_source_last; +wire [21:0] soc_litedramcore_bankmachine2_source_source_payload_addr; +wire soc_litedramcore_bankmachine2_source_source_payload_we; +wire soc_litedramcore_bankmachine2_source_source_ready; +wire soc_litedramcore_bankmachine2_source_source_valid; +wire soc_litedramcore_bankmachine2_source_valid; +wire [24:0] soc_litedramcore_bankmachine2_syncfifo2_din; +wire [24:0] soc_litedramcore_bankmachine2_syncfifo2_dout; +wire soc_litedramcore_bankmachine2_syncfifo2_re; +wire soc_litedramcore_bankmachine2_syncfifo2_readable; +wire soc_litedramcore_bankmachine2_syncfifo2_we; +wire soc_litedramcore_bankmachine2_syncfifo2_writable; +reg [1:0] soc_litedramcore_bankmachine2_trascon_count = 2'd0; +reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine2_trascon_valid; +reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0; +wire soc_litedramcore_bankmachine2_trccon_valid; +reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +wire soc_litedramcore_bankmachine2_twtpcon_valid; +reg [2:0] soc_litedramcore_bankmachine2_wrport_adr = 3'd0; +wire [24:0] soc_litedramcore_bankmachine2_wrport_dat_r; +wire [24:0] soc_litedramcore_bankmachine2_wrport_dat_w; +wire soc_litedramcore_bankmachine2_wrport_we; +reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0; +reg [14:0] soc_litedramcore_bankmachine3_cmd_payload_a = 15'd0; +wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba; +reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_consume = 3'd0; +wire soc_litedramcore_bankmachine3_do_read; +wire soc_litedramcore_bankmachine3_fifo_in_first; +wire soc_litedramcore_bankmachine3_fifo_in_last; +wire [21:0] soc_litedramcore_bankmachine3_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine3_fifo_in_payload_we; +wire soc_litedramcore_bankmachine3_fifo_out_first; +wire soc_litedramcore_bankmachine3_fifo_out_last; +wire [21:0] soc_litedramcore_bankmachine3_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine3_fifo_out_payload_we; +reg [3:0] soc_litedramcore_bankmachine3_level = 4'd0; +wire soc_litedramcore_bankmachine3_pipe_valid_sink_first; +wire soc_litedramcore_bankmachine3_pipe_valid_sink_last; +wire [21:0] soc_litedramcore_bankmachine3_pipe_valid_sink_payload_addr; +wire soc_litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire soc_litedramcore_bankmachine3_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine3_pipe_valid_sink_valid; +reg soc_litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; +reg soc_litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; +reg [21:0] soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0; +reg soc_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +wire soc_litedramcore_bankmachine3_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_produce = 3'd0; +wire [2:0] soc_litedramcore_bankmachine3_rdport_adr; +wire [24:0] soc_litedramcore_bankmachine3_rdport_dat_r; +reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; +wire soc_litedramcore_bankmachine3_refresh_req; +reg soc_litedramcore_bankmachine3_replace = 1'd0; +wire [21:0] soc_litedramcore_bankmachine3_req_addr; +wire soc_litedramcore_bankmachine3_req_lock; +reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine3_req_ready; +wire soc_litedramcore_bankmachine3_req_valid; +reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +wire soc_litedramcore_bankmachine3_req_we; +reg [14:0] soc_litedramcore_bankmachine3_row = 15'd0; +reg soc_litedramcore_bankmachine3_row_close = 1'd0; +reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine3_row_hit; +reg soc_litedramcore_bankmachine3_row_open = 1'd0; +reg soc_litedramcore_bankmachine3_row_opened = 1'd0; +reg soc_litedramcore_bankmachine3_sink_first = 1'd0; +reg soc_litedramcore_bankmachine3_sink_last = 1'd0; +wire [21:0] soc_litedramcore_bankmachine3_sink_payload_addr; +wire soc_litedramcore_bankmachine3_sink_payload_we; +wire soc_litedramcore_bankmachine3_sink_ready; +wire soc_litedramcore_bankmachine3_sink_sink_first; +wire soc_litedramcore_bankmachine3_sink_sink_last; +wire [21:0] soc_litedramcore_bankmachine3_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine3_sink_sink_payload_we; +wire soc_litedramcore_bankmachine3_sink_sink_ready; +wire soc_litedramcore_bankmachine3_sink_sink_valid; +wire soc_litedramcore_bankmachine3_sink_valid; +wire soc_litedramcore_bankmachine3_source_first; +wire soc_litedramcore_bankmachine3_source_last; +wire [21:0] soc_litedramcore_bankmachine3_source_payload_addr; +wire soc_litedramcore_bankmachine3_source_payload_we; +wire soc_litedramcore_bankmachine3_source_ready; +wire soc_litedramcore_bankmachine3_source_source_first; +wire soc_litedramcore_bankmachine3_source_source_last; +wire [21:0] soc_litedramcore_bankmachine3_source_source_payload_addr; +wire soc_litedramcore_bankmachine3_source_source_payload_we; +wire soc_litedramcore_bankmachine3_source_source_ready; +wire soc_litedramcore_bankmachine3_source_source_valid; +wire soc_litedramcore_bankmachine3_source_valid; +wire [24:0] soc_litedramcore_bankmachine3_syncfifo3_din; +wire [24:0] soc_litedramcore_bankmachine3_syncfifo3_dout; +wire soc_litedramcore_bankmachine3_syncfifo3_re; +wire soc_litedramcore_bankmachine3_syncfifo3_readable; +wire soc_litedramcore_bankmachine3_syncfifo3_we; +wire soc_litedramcore_bankmachine3_syncfifo3_writable; +reg [1:0] soc_litedramcore_bankmachine3_trascon_count = 2'd0; +reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine3_trascon_valid; +reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0; +wire soc_litedramcore_bankmachine3_trccon_valid; +reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +wire soc_litedramcore_bankmachine3_twtpcon_valid; +reg [2:0] soc_litedramcore_bankmachine3_wrport_adr = 3'd0; +wire [24:0] soc_litedramcore_bankmachine3_wrport_dat_r; +wire [24:0] soc_litedramcore_bankmachine3_wrport_dat_w; +wire soc_litedramcore_bankmachine3_wrport_we; +reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0; +reg [14:0] soc_litedramcore_bankmachine4_cmd_payload_a = 15'd0; +wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba; +reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_consume = 3'd0; +wire soc_litedramcore_bankmachine4_do_read; +wire soc_litedramcore_bankmachine4_fifo_in_first; +wire soc_litedramcore_bankmachine4_fifo_in_last; +wire [21:0] soc_litedramcore_bankmachine4_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine4_fifo_in_payload_we; +wire soc_litedramcore_bankmachine4_fifo_out_first; +wire soc_litedramcore_bankmachine4_fifo_out_last; +wire [21:0] soc_litedramcore_bankmachine4_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine4_fifo_out_payload_we; +reg [3:0] soc_litedramcore_bankmachine4_level = 4'd0; +wire soc_litedramcore_bankmachine4_pipe_valid_sink_first; +wire soc_litedramcore_bankmachine4_pipe_valid_sink_last; +wire [21:0] soc_litedramcore_bankmachine4_pipe_valid_sink_payload_addr; +wire soc_litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire soc_litedramcore_bankmachine4_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine4_pipe_valid_sink_valid; +reg soc_litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; +reg soc_litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; +reg [21:0] soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0; +reg soc_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +wire soc_litedramcore_bankmachine4_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_produce = 3'd0; +wire [2:0] soc_litedramcore_bankmachine4_rdport_adr; +wire [24:0] soc_litedramcore_bankmachine4_rdport_dat_r; +reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; +wire soc_litedramcore_bankmachine4_refresh_req; +reg soc_litedramcore_bankmachine4_replace = 1'd0; +wire [21:0] soc_litedramcore_bankmachine4_req_addr; +wire soc_litedramcore_bankmachine4_req_lock; +reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine4_req_ready; +wire soc_litedramcore_bankmachine4_req_valid; +reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +wire soc_litedramcore_bankmachine4_req_we; +reg [14:0] soc_litedramcore_bankmachine4_row = 15'd0; +reg soc_litedramcore_bankmachine4_row_close = 1'd0; +reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine4_row_hit; +reg soc_litedramcore_bankmachine4_row_open = 1'd0; +reg soc_litedramcore_bankmachine4_row_opened = 1'd0; +reg soc_litedramcore_bankmachine4_sink_first = 1'd0; +reg soc_litedramcore_bankmachine4_sink_last = 1'd0; +wire [21:0] soc_litedramcore_bankmachine4_sink_payload_addr; +wire soc_litedramcore_bankmachine4_sink_payload_we; +wire soc_litedramcore_bankmachine4_sink_ready; +wire soc_litedramcore_bankmachine4_sink_sink_first; +wire soc_litedramcore_bankmachine4_sink_sink_last; +wire [21:0] soc_litedramcore_bankmachine4_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine4_sink_sink_payload_we; +wire soc_litedramcore_bankmachine4_sink_sink_ready; +wire soc_litedramcore_bankmachine4_sink_sink_valid; +wire soc_litedramcore_bankmachine4_sink_valid; +wire soc_litedramcore_bankmachine4_source_first; +wire soc_litedramcore_bankmachine4_source_last; +wire [21:0] soc_litedramcore_bankmachine4_source_payload_addr; +wire soc_litedramcore_bankmachine4_source_payload_we; +wire soc_litedramcore_bankmachine4_source_ready; +wire soc_litedramcore_bankmachine4_source_source_first; +wire soc_litedramcore_bankmachine4_source_source_last; +wire [21:0] soc_litedramcore_bankmachine4_source_source_payload_addr; +wire soc_litedramcore_bankmachine4_source_source_payload_we; +wire soc_litedramcore_bankmachine4_source_source_ready; +wire soc_litedramcore_bankmachine4_source_source_valid; +wire soc_litedramcore_bankmachine4_source_valid; +wire [24:0] soc_litedramcore_bankmachine4_syncfifo4_din; +wire [24:0] soc_litedramcore_bankmachine4_syncfifo4_dout; +wire soc_litedramcore_bankmachine4_syncfifo4_re; +wire soc_litedramcore_bankmachine4_syncfifo4_readable; +wire soc_litedramcore_bankmachine4_syncfifo4_we; +wire soc_litedramcore_bankmachine4_syncfifo4_writable; +reg [1:0] soc_litedramcore_bankmachine4_trascon_count = 2'd0; +reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine4_trascon_valid; +reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0; +wire soc_litedramcore_bankmachine4_trccon_valid; +reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +wire soc_litedramcore_bankmachine4_twtpcon_valid; +reg [2:0] soc_litedramcore_bankmachine4_wrport_adr = 3'd0; +wire [24:0] soc_litedramcore_bankmachine4_wrport_dat_r; +wire [24:0] soc_litedramcore_bankmachine4_wrport_dat_w; +wire soc_litedramcore_bankmachine4_wrport_we; +reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0; +reg [14:0] soc_litedramcore_bankmachine5_cmd_payload_a = 15'd0; +wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba; +reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_consume = 3'd0; +wire soc_litedramcore_bankmachine5_do_read; +wire soc_litedramcore_bankmachine5_fifo_in_first; +wire soc_litedramcore_bankmachine5_fifo_in_last; +wire [21:0] soc_litedramcore_bankmachine5_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine5_fifo_in_payload_we; +wire soc_litedramcore_bankmachine5_fifo_out_first; +wire soc_litedramcore_bankmachine5_fifo_out_last; +wire [21:0] soc_litedramcore_bankmachine5_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine5_fifo_out_payload_we; +reg [3:0] soc_litedramcore_bankmachine5_level = 4'd0; +wire soc_litedramcore_bankmachine5_pipe_valid_sink_first; +wire soc_litedramcore_bankmachine5_pipe_valid_sink_last; +wire [21:0] soc_litedramcore_bankmachine5_pipe_valid_sink_payload_addr; +wire soc_litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire soc_litedramcore_bankmachine5_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine5_pipe_valid_sink_valid; +reg soc_litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; +reg soc_litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; +reg [21:0] soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0; +reg soc_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +wire soc_litedramcore_bankmachine5_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_produce = 3'd0; +wire [2:0] soc_litedramcore_bankmachine5_rdport_adr; +wire [24:0] soc_litedramcore_bankmachine5_rdport_dat_r; +reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; +wire soc_litedramcore_bankmachine5_refresh_req; +reg soc_litedramcore_bankmachine5_replace = 1'd0; +wire [21:0] soc_litedramcore_bankmachine5_req_addr; +wire soc_litedramcore_bankmachine5_req_lock; +reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine5_req_ready; +wire soc_litedramcore_bankmachine5_req_valid; +reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +wire soc_litedramcore_bankmachine5_req_we; +reg [14:0] soc_litedramcore_bankmachine5_row = 15'd0; +reg soc_litedramcore_bankmachine5_row_close = 1'd0; +reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine5_row_hit; +reg soc_litedramcore_bankmachine5_row_open = 1'd0; +reg soc_litedramcore_bankmachine5_row_opened = 1'd0; +reg soc_litedramcore_bankmachine5_sink_first = 1'd0; +reg soc_litedramcore_bankmachine5_sink_last = 1'd0; +wire [21:0] soc_litedramcore_bankmachine5_sink_payload_addr; +wire soc_litedramcore_bankmachine5_sink_payload_we; +wire soc_litedramcore_bankmachine5_sink_ready; +wire soc_litedramcore_bankmachine5_sink_sink_first; +wire soc_litedramcore_bankmachine5_sink_sink_last; +wire [21:0] soc_litedramcore_bankmachine5_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine5_sink_sink_payload_we; +wire soc_litedramcore_bankmachine5_sink_sink_ready; +wire soc_litedramcore_bankmachine5_sink_sink_valid; +wire soc_litedramcore_bankmachine5_sink_valid; +wire soc_litedramcore_bankmachine5_source_first; +wire soc_litedramcore_bankmachine5_source_last; +wire [21:0] soc_litedramcore_bankmachine5_source_payload_addr; +wire soc_litedramcore_bankmachine5_source_payload_we; +wire soc_litedramcore_bankmachine5_source_ready; +wire soc_litedramcore_bankmachine5_source_source_first; +wire soc_litedramcore_bankmachine5_source_source_last; +wire [21:0] soc_litedramcore_bankmachine5_source_source_payload_addr; +wire soc_litedramcore_bankmachine5_source_source_payload_we; +wire soc_litedramcore_bankmachine5_source_source_ready; +wire soc_litedramcore_bankmachine5_source_source_valid; +wire soc_litedramcore_bankmachine5_source_valid; +wire [24:0] soc_litedramcore_bankmachine5_syncfifo5_din; +wire [24:0] soc_litedramcore_bankmachine5_syncfifo5_dout; +wire soc_litedramcore_bankmachine5_syncfifo5_re; +wire soc_litedramcore_bankmachine5_syncfifo5_readable; +wire soc_litedramcore_bankmachine5_syncfifo5_we; +wire soc_litedramcore_bankmachine5_syncfifo5_writable; +reg [1:0] soc_litedramcore_bankmachine5_trascon_count = 2'd0; +reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine5_trascon_valid; +reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0; +wire soc_litedramcore_bankmachine5_trccon_valid; +reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +wire soc_litedramcore_bankmachine5_twtpcon_valid; +reg [2:0] soc_litedramcore_bankmachine5_wrport_adr = 3'd0; +wire [24:0] soc_litedramcore_bankmachine5_wrport_dat_r; +wire [24:0] soc_litedramcore_bankmachine5_wrport_dat_w; +wire soc_litedramcore_bankmachine5_wrport_we; +reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0; +reg [14:0] soc_litedramcore_bankmachine6_cmd_payload_a = 15'd0; +wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba; +reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_consume = 3'd0; +wire soc_litedramcore_bankmachine6_do_read; +wire soc_litedramcore_bankmachine6_fifo_in_first; +wire soc_litedramcore_bankmachine6_fifo_in_last; +wire [21:0] soc_litedramcore_bankmachine6_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine6_fifo_in_payload_we; +wire soc_litedramcore_bankmachine6_fifo_out_first; +wire soc_litedramcore_bankmachine6_fifo_out_last; +wire [21:0] soc_litedramcore_bankmachine6_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine6_fifo_out_payload_we; +reg [3:0] soc_litedramcore_bankmachine6_level = 4'd0; +wire soc_litedramcore_bankmachine6_pipe_valid_sink_first; +wire soc_litedramcore_bankmachine6_pipe_valid_sink_last; +wire [21:0] soc_litedramcore_bankmachine6_pipe_valid_sink_payload_addr; +wire soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire soc_litedramcore_bankmachine6_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine6_pipe_valid_sink_valid; +reg soc_litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; +reg soc_litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; +reg [21:0] soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0; +reg soc_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +wire soc_litedramcore_bankmachine6_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_produce = 3'd0; +wire [2:0] soc_litedramcore_bankmachine6_rdport_adr; +wire [24:0] soc_litedramcore_bankmachine6_rdport_dat_r; +reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; +wire soc_litedramcore_bankmachine6_refresh_req; +reg soc_litedramcore_bankmachine6_replace = 1'd0; +wire [21:0] soc_litedramcore_bankmachine6_req_addr; +wire soc_litedramcore_bankmachine6_req_lock; +reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine6_req_ready; +wire soc_litedramcore_bankmachine6_req_valid; +reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +wire soc_litedramcore_bankmachine6_req_we; +reg [14:0] soc_litedramcore_bankmachine6_row = 15'd0; +reg soc_litedramcore_bankmachine6_row_close = 1'd0; +reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine6_row_hit; +reg soc_litedramcore_bankmachine6_row_open = 1'd0; +reg soc_litedramcore_bankmachine6_row_opened = 1'd0; +reg soc_litedramcore_bankmachine6_sink_first = 1'd0; +reg soc_litedramcore_bankmachine6_sink_last = 1'd0; +wire [21:0] soc_litedramcore_bankmachine6_sink_payload_addr; +wire soc_litedramcore_bankmachine6_sink_payload_we; +wire soc_litedramcore_bankmachine6_sink_ready; +wire soc_litedramcore_bankmachine6_sink_sink_first; +wire soc_litedramcore_bankmachine6_sink_sink_last; +wire [21:0] soc_litedramcore_bankmachine6_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine6_sink_sink_payload_we; +wire soc_litedramcore_bankmachine6_sink_sink_ready; +wire soc_litedramcore_bankmachine6_sink_sink_valid; +wire soc_litedramcore_bankmachine6_sink_valid; +wire soc_litedramcore_bankmachine6_source_first; +wire soc_litedramcore_bankmachine6_source_last; +wire [21:0] soc_litedramcore_bankmachine6_source_payload_addr; +wire soc_litedramcore_bankmachine6_source_payload_we; +wire soc_litedramcore_bankmachine6_source_ready; +wire soc_litedramcore_bankmachine6_source_source_first; +wire soc_litedramcore_bankmachine6_source_source_last; +wire [21:0] soc_litedramcore_bankmachine6_source_source_payload_addr; +wire soc_litedramcore_bankmachine6_source_source_payload_we; +wire soc_litedramcore_bankmachine6_source_source_ready; +wire soc_litedramcore_bankmachine6_source_source_valid; +wire soc_litedramcore_bankmachine6_source_valid; +wire [24:0] soc_litedramcore_bankmachine6_syncfifo6_din; +wire [24:0] soc_litedramcore_bankmachine6_syncfifo6_dout; +wire soc_litedramcore_bankmachine6_syncfifo6_re; +wire soc_litedramcore_bankmachine6_syncfifo6_readable; +wire soc_litedramcore_bankmachine6_syncfifo6_we; +wire soc_litedramcore_bankmachine6_syncfifo6_writable; +reg [1:0] soc_litedramcore_bankmachine6_trascon_count = 2'd0; +reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine6_trascon_valid; +reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0; +wire soc_litedramcore_bankmachine6_trccon_valid; +reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +wire soc_litedramcore_bankmachine6_twtpcon_valid; +reg [2:0] soc_litedramcore_bankmachine6_wrport_adr = 3'd0; +wire [24:0] soc_litedramcore_bankmachine6_wrport_dat_r; +wire [24:0] soc_litedramcore_bankmachine6_wrport_dat_w; +wire soc_litedramcore_bankmachine6_wrport_we; +reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0; +reg [14:0] soc_litedramcore_bankmachine7_cmd_payload_a = 15'd0; +wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba; +reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_consume = 3'd0; +wire soc_litedramcore_bankmachine7_do_read; +wire soc_litedramcore_bankmachine7_fifo_in_first; +wire soc_litedramcore_bankmachine7_fifo_in_last; +wire [21:0] soc_litedramcore_bankmachine7_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine7_fifo_in_payload_we; +wire soc_litedramcore_bankmachine7_fifo_out_first; +wire soc_litedramcore_bankmachine7_fifo_out_last; +wire [21:0] soc_litedramcore_bankmachine7_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine7_fifo_out_payload_we; +reg [3:0] soc_litedramcore_bankmachine7_level = 4'd0; +wire soc_litedramcore_bankmachine7_pipe_valid_sink_first; +wire soc_litedramcore_bankmachine7_pipe_valid_sink_last; +wire [21:0] soc_litedramcore_bankmachine7_pipe_valid_sink_payload_addr; +wire soc_litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire soc_litedramcore_bankmachine7_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine7_pipe_valid_sink_valid; +reg soc_litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; +reg soc_litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; +reg [21:0] soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0; +reg soc_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +wire soc_litedramcore_bankmachine7_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_produce = 3'd0; +wire [2:0] soc_litedramcore_bankmachine7_rdport_adr; +wire [24:0] soc_litedramcore_bankmachine7_rdport_dat_r; +reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; +wire soc_litedramcore_bankmachine7_refresh_req; +reg soc_litedramcore_bankmachine7_replace = 1'd0; +wire [21:0] soc_litedramcore_bankmachine7_req_addr; +wire soc_litedramcore_bankmachine7_req_lock; +reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine7_req_ready; +wire soc_litedramcore_bankmachine7_req_valid; +reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +wire soc_litedramcore_bankmachine7_req_we; +reg [14:0] soc_litedramcore_bankmachine7_row = 15'd0; +reg soc_litedramcore_bankmachine7_row_close = 1'd0; +reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine7_row_hit; +reg soc_litedramcore_bankmachine7_row_open = 1'd0; +reg soc_litedramcore_bankmachine7_row_opened = 1'd0; +reg soc_litedramcore_bankmachine7_sink_first = 1'd0; +reg soc_litedramcore_bankmachine7_sink_last = 1'd0; +wire [21:0] soc_litedramcore_bankmachine7_sink_payload_addr; +wire soc_litedramcore_bankmachine7_sink_payload_we; +wire soc_litedramcore_bankmachine7_sink_ready; +wire soc_litedramcore_bankmachine7_sink_sink_first; +wire soc_litedramcore_bankmachine7_sink_sink_last; +wire [21:0] soc_litedramcore_bankmachine7_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine7_sink_sink_payload_we; +wire soc_litedramcore_bankmachine7_sink_sink_ready; +wire soc_litedramcore_bankmachine7_sink_sink_valid; +wire soc_litedramcore_bankmachine7_sink_valid; +wire soc_litedramcore_bankmachine7_source_first; +wire soc_litedramcore_bankmachine7_source_last; +wire [21:0] soc_litedramcore_bankmachine7_source_payload_addr; +wire soc_litedramcore_bankmachine7_source_payload_we; +wire soc_litedramcore_bankmachine7_source_ready; +wire soc_litedramcore_bankmachine7_source_source_first; +wire soc_litedramcore_bankmachine7_source_source_last; +wire [21:0] soc_litedramcore_bankmachine7_source_source_payload_addr; +wire soc_litedramcore_bankmachine7_source_source_payload_we; +wire soc_litedramcore_bankmachine7_source_source_ready; +wire soc_litedramcore_bankmachine7_source_source_valid; +wire soc_litedramcore_bankmachine7_source_valid; +wire [24:0] soc_litedramcore_bankmachine7_syncfifo7_din; +wire [24:0] soc_litedramcore_bankmachine7_syncfifo7_dout; +wire soc_litedramcore_bankmachine7_syncfifo7_re; +wire soc_litedramcore_bankmachine7_syncfifo7_readable; +wire soc_litedramcore_bankmachine7_syncfifo7_we; +wire soc_litedramcore_bankmachine7_syncfifo7_writable; +reg [1:0] soc_litedramcore_bankmachine7_trascon_count = 2'd0; +reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine7_trascon_valid; +reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0; +wire soc_litedramcore_bankmachine7_trccon_valid; +reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +wire soc_litedramcore_bankmachine7_twtpcon_valid; +reg [2:0] soc_litedramcore_bankmachine7_wrport_adr = 3'd0; +wire [24:0] soc_litedramcore_bankmachine7_wrport_dat_r; +wire [24:0] soc_litedramcore_bankmachine7_wrport_dat_w; +wire soc_litedramcore_bankmachine7_wrport_we; +wire soc_litedramcore_cas_allowed; +wire soc_litedramcore_choose_cmd_ce; +wire [14:0] soc_litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba; +reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd; +wire soc_litedramcore_choose_cmd_cmd_payload_is_read; +wire soc_litedramcore_choose_cmd_cmd_payload_is_write; +reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0; +wire soc_litedramcore_choose_cmd_cmd_valid; +reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0; +wire [7:0] soc_litedramcore_choose_cmd_request; +reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0; +reg soc_litedramcore_choose_cmd_want_activates = 1'd0; +reg soc_litedramcore_choose_cmd_want_cmds = 1'd0; +reg soc_litedramcore_choose_cmd_want_reads = 1'd0; +reg soc_litedramcore_choose_cmd_want_writes = 1'd0; +wire soc_litedramcore_choose_req_ce; +wire [14:0] soc_litedramcore_choose_req_cmd_payload_a; +wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba; +reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0; +wire soc_litedramcore_choose_req_cmd_payload_is_cmd; +wire soc_litedramcore_choose_req_cmd_payload_is_read; +wire soc_litedramcore_choose_req_cmd_payload_is_write; +reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0; +reg soc_litedramcore_choose_req_cmd_ready = 1'd0; +wire soc_litedramcore_choose_req_cmd_valid; +reg [2:0] soc_litedramcore_choose_req_grant = 3'd0; +wire [7:0] soc_litedramcore_choose_req_request; +reg [7:0] soc_litedramcore_choose_req_valids = 8'd0; +reg soc_litedramcore_choose_req_want_activates = 1'd0; +reg soc_litedramcore_choose_req_want_cmds = 1'd0; +reg soc_litedramcore_choose_req_want_reads = 1'd0; +reg soc_litedramcore_choose_req_want_writes = 1'd0; +wire soc_litedramcore_cke; +reg soc_litedramcore_cmd_last = 1'd0; +reg [14:0] soc_litedramcore_cmd_payload_a = 15'd0; +reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0; +reg soc_litedramcore_cmd_payload_cas = 1'd0; +reg soc_litedramcore_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_cmd_payload_ras = 1'd0; +reg soc_litedramcore_cmd_payload_we = 1'd0; +reg soc_litedramcore_cmd_ready = 1'd0; +reg soc_litedramcore_cmd_valid = 1'd0; +reg soc_litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [14:0] soc_litedramcore_csr_dfi_p0_address; +wire [2:0] soc_litedramcore_csr_dfi_p0_bank; +reg soc_litedramcore_csr_dfi_p0_cas_n = 1'd1; +wire soc_litedramcore_csr_dfi_p0_cke; +reg soc_litedramcore_csr_dfi_p0_cs_n = 1'd1; +wire soc_litedramcore_csr_dfi_p0_odt; +reg soc_litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg [31:0] soc_litedramcore_csr_dfi_p0_rddata = 32'd0; +wire soc_litedramcore_csr_dfi_p0_rddata_en; +reg soc_litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire soc_litedramcore_csr_dfi_p0_reset_n; +reg soc_litedramcore_csr_dfi_p0_we_n = 1'd1; +wire [31:0] soc_litedramcore_csr_dfi_p0_wrdata; +wire soc_litedramcore_csr_dfi_p0_wrdata_en; +wire [3:0] soc_litedramcore_csr_dfi_p0_wrdata_mask; +reg soc_litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [14:0] soc_litedramcore_csr_dfi_p1_address; +wire [2:0] soc_litedramcore_csr_dfi_p1_bank; +reg soc_litedramcore_csr_dfi_p1_cas_n = 1'd1; +wire soc_litedramcore_csr_dfi_p1_cke; +reg soc_litedramcore_csr_dfi_p1_cs_n = 1'd1; +wire soc_litedramcore_csr_dfi_p1_odt; +reg soc_litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg [31:0] soc_litedramcore_csr_dfi_p1_rddata = 32'd0; +wire soc_litedramcore_csr_dfi_p1_rddata_en; +reg soc_litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +wire soc_litedramcore_csr_dfi_p1_reset_n; +reg soc_litedramcore_csr_dfi_p1_we_n = 1'd1; +wire [31:0] soc_litedramcore_csr_dfi_p1_wrdata; +wire soc_litedramcore_csr_dfi_p1_wrdata_en; +wire [3:0] soc_litedramcore_csr_dfi_p1_wrdata_mask; +reg soc_litedramcore_csr_dfi_p2_act_n = 1'd1; +wire [14:0] soc_litedramcore_csr_dfi_p2_address; +wire [2:0] soc_litedramcore_csr_dfi_p2_bank; +reg soc_litedramcore_csr_dfi_p2_cas_n = 1'd1; +wire soc_litedramcore_csr_dfi_p2_cke; +reg soc_litedramcore_csr_dfi_p2_cs_n = 1'd1; +wire soc_litedramcore_csr_dfi_p2_odt; +reg soc_litedramcore_csr_dfi_p2_ras_n = 1'd1; +reg [31:0] soc_litedramcore_csr_dfi_p2_rddata = 32'd0; +wire soc_litedramcore_csr_dfi_p2_rddata_en; +reg soc_litedramcore_csr_dfi_p2_rddata_valid = 1'd0; +wire soc_litedramcore_csr_dfi_p2_reset_n; +reg soc_litedramcore_csr_dfi_p2_we_n = 1'd1; +wire [31:0] soc_litedramcore_csr_dfi_p2_wrdata; +wire soc_litedramcore_csr_dfi_p2_wrdata_en; +wire [3:0] soc_litedramcore_csr_dfi_p2_wrdata_mask; +reg soc_litedramcore_csr_dfi_p3_act_n = 1'd1; +wire [14:0] soc_litedramcore_csr_dfi_p3_address; +wire [2:0] soc_litedramcore_csr_dfi_p3_bank; +reg soc_litedramcore_csr_dfi_p3_cas_n = 1'd1; +wire soc_litedramcore_csr_dfi_p3_cke; +reg soc_litedramcore_csr_dfi_p3_cs_n = 1'd1; +wire soc_litedramcore_csr_dfi_p3_odt; +reg soc_litedramcore_csr_dfi_p3_ras_n = 1'd1; +reg [31:0] soc_litedramcore_csr_dfi_p3_rddata = 32'd0; +wire soc_litedramcore_csr_dfi_p3_rddata_en; +reg soc_litedramcore_csr_dfi_p3_rddata_valid = 1'd0; +wire soc_litedramcore_csr_dfi_p3_reset_n; +reg soc_litedramcore_csr_dfi_p3_we_n = 1'd1; +wire [31:0] soc_litedramcore_csr_dfi_p3_wrdata; +wire soc_litedramcore_csr_dfi_p3_wrdata_en; +wire [3:0] soc_litedramcore_csr_dfi_p3_wrdata_mask; +reg soc_litedramcore_dfi_p0_act_n = 1'd1; +reg [14:0] soc_litedramcore_dfi_p0_address = 15'd0; +reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0; +reg soc_litedramcore_dfi_p0_cas_n = 1'd1; +wire soc_litedramcore_dfi_p0_cke; +reg soc_litedramcore_dfi_p0_cs_n = 1'd1; +wire soc_litedramcore_dfi_p0_odt; +reg soc_litedramcore_dfi_p0_ras_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p0_rddata; +reg soc_litedramcore_dfi_p0_rddata_en = 1'd0; +wire soc_litedramcore_dfi_p0_rddata_valid; +wire soc_litedramcore_dfi_p0_reset_n; +reg soc_litedramcore_dfi_p0_we_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p0_wrdata; +reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask; +reg soc_litedramcore_dfi_p1_act_n = 1'd1; +reg [14:0] soc_litedramcore_dfi_p1_address = 15'd0; +reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0; +reg soc_litedramcore_dfi_p1_cas_n = 1'd1; +wire soc_litedramcore_dfi_p1_cke; +reg soc_litedramcore_dfi_p1_cs_n = 1'd1; +wire soc_litedramcore_dfi_p1_odt; +reg soc_litedramcore_dfi_p1_ras_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p1_rddata; +reg soc_litedramcore_dfi_p1_rddata_en = 1'd0; +wire soc_litedramcore_dfi_p1_rddata_valid; +wire soc_litedramcore_dfi_p1_reset_n; +reg soc_litedramcore_dfi_p1_we_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p1_wrdata; +reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask; +reg soc_litedramcore_dfi_p2_act_n = 1'd1; +reg [14:0] soc_litedramcore_dfi_p2_address = 15'd0; +reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0; +reg soc_litedramcore_dfi_p2_cas_n = 1'd1; +wire soc_litedramcore_dfi_p2_cke; +reg soc_litedramcore_dfi_p2_cs_n = 1'd1; +wire soc_litedramcore_dfi_p2_odt; +reg soc_litedramcore_dfi_p2_ras_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p2_rddata; +reg soc_litedramcore_dfi_p2_rddata_en = 1'd0; +wire soc_litedramcore_dfi_p2_rddata_valid; +wire soc_litedramcore_dfi_p2_reset_n; +reg soc_litedramcore_dfi_p2_we_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p2_wrdata; +reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask; +reg soc_litedramcore_dfi_p3_act_n = 1'd1; +reg [14:0] soc_litedramcore_dfi_p3_address = 15'd0; +reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0; +reg soc_litedramcore_dfi_p3_cas_n = 1'd1; +wire soc_litedramcore_dfi_p3_cke; +reg soc_litedramcore_dfi_p3_cs_n = 1'd1; +wire soc_litedramcore_dfi_p3_odt; +reg soc_litedramcore_dfi_p3_ras_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p3_rddata; +reg soc_litedramcore_dfi_p3_rddata_en = 1'd0; +wire soc_litedramcore_dfi_p3_rddata_valid; +wire soc_litedramcore_dfi_p3_reset_n; +reg soc_litedramcore_dfi_p3_we_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p3_wrdata; +reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask; +reg soc_litedramcore_en0 = 1'd0; +reg soc_litedramcore_en1 = 1'd0; +reg soc_litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [14:0] soc_litedramcore_ext_dfi_p0_address = 15'd0; +reg [2:0] soc_litedramcore_ext_dfi_p0_bank = 3'd0; +reg soc_litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg soc_litedramcore_ext_dfi_p0_cke = 1'd0; +reg soc_litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg soc_litedramcore_ext_dfi_p0_odt = 1'd0; +reg soc_litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p0_rddata = 32'd0; +reg soc_litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg soc_litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg soc_litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg soc_litedramcore_ext_dfi_p0_we_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p0_wrdata = 32'd0; +reg soc_litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; +reg soc_litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [14:0] soc_litedramcore_ext_dfi_p1_address = 15'd0; +reg [2:0] soc_litedramcore_ext_dfi_p1_bank = 3'd0; +reg soc_litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg soc_litedramcore_ext_dfi_p1_cke = 1'd0; +reg soc_litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg soc_litedramcore_ext_dfi_p1_odt = 1'd0; +reg soc_litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p1_rddata = 32'd0; +reg soc_litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg soc_litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg soc_litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg soc_litedramcore_ext_dfi_p1_we_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p1_wrdata = 32'd0; +reg soc_litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; +reg soc_litedramcore_ext_dfi_p2_act_n = 1'd1; +reg [14:0] soc_litedramcore_ext_dfi_p2_address = 15'd0; +reg [2:0] soc_litedramcore_ext_dfi_p2_bank = 3'd0; +reg soc_litedramcore_ext_dfi_p2_cas_n = 1'd1; +reg soc_litedramcore_ext_dfi_p2_cke = 1'd0; +reg soc_litedramcore_ext_dfi_p2_cs_n = 1'd1; +reg soc_litedramcore_ext_dfi_p2_odt = 1'd0; +reg soc_litedramcore_ext_dfi_p2_ras_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p2_rddata = 32'd0; +reg soc_litedramcore_ext_dfi_p2_rddata_en = 1'd0; +reg soc_litedramcore_ext_dfi_p2_rddata_valid = 1'd0; +reg soc_litedramcore_ext_dfi_p2_reset_n = 1'd0; +reg soc_litedramcore_ext_dfi_p2_we_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p2_wrdata = 32'd0; +reg soc_litedramcore_ext_dfi_p2_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; +reg soc_litedramcore_ext_dfi_p3_act_n = 1'd1; +reg [14:0] soc_litedramcore_ext_dfi_p3_address = 15'd0; +reg [2:0] soc_litedramcore_ext_dfi_p3_bank = 3'd0; +reg soc_litedramcore_ext_dfi_p3_cas_n = 1'd1; +reg soc_litedramcore_ext_dfi_p3_cke = 1'd0; +reg soc_litedramcore_ext_dfi_p3_cs_n = 1'd1; +reg soc_litedramcore_ext_dfi_p3_odt = 1'd0; +reg soc_litedramcore_ext_dfi_p3_ras_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p3_rddata = 32'd0; +reg soc_litedramcore_ext_dfi_p3_rddata_en = 1'd0; +reg soc_litedramcore_ext_dfi_p3_rddata_valid = 1'd0; +reg soc_litedramcore_ext_dfi_p3_reset_n = 1'd0; +reg soc_litedramcore_ext_dfi_p3_we_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p3_wrdata = 32'd0; +reg soc_litedramcore_ext_dfi_p3_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; +reg soc_litedramcore_ext_dfi_sel = 1'd0; +wire soc_litedramcore_go_to_refresh; +wire [21:0] soc_litedramcore_interface_bank0_addr; +wire soc_litedramcore_interface_bank0_lock; +wire soc_litedramcore_interface_bank0_rdata_valid; +wire soc_litedramcore_interface_bank0_ready; +wire soc_litedramcore_interface_bank0_valid; +wire soc_litedramcore_interface_bank0_wdata_ready; +wire soc_litedramcore_interface_bank0_we; +wire [21:0] soc_litedramcore_interface_bank1_addr; +wire soc_litedramcore_interface_bank1_lock; +wire soc_litedramcore_interface_bank1_rdata_valid; +wire soc_litedramcore_interface_bank1_ready; +wire soc_litedramcore_interface_bank1_valid; +wire soc_litedramcore_interface_bank1_wdata_ready; +wire soc_litedramcore_interface_bank1_we; +wire [21:0] soc_litedramcore_interface_bank2_addr; +wire soc_litedramcore_interface_bank2_lock; +wire soc_litedramcore_interface_bank2_rdata_valid; +wire soc_litedramcore_interface_bank2_ready; +wire soc_litedramcore_interface_bank2_valid; +wire soc_litedramcore_interface_bank2_wdata_ready; +wire soc_litedramcore_interface_bank2_we; +wire [21:0] soc_litedramcore_interface_bank3_addr; +wire soc_litedramcore_interface_bank3_lock; +wire soc_litedramcore_interface_bank3_rdata_valid; +wire soc_litedramcore_interface_bank3_ready; +wire soc_litedramcore_interface_bank3_valid; +wire soc_litedramcore_interface_bank3_wdata_ready; +wire soc_litedramcore_interface_bank3_we; +wire [21:0] soc_litedramcore_interface_bank4_addr; +wire soc_litedramcore_interface_bank4_lock; +wire soc_litedramcore_interface_bank4_rdata_valid; +wire soc_litedramcore_interface_bank4_ready; +wire soc_litedramcore_interface_bank4_valid; +wire soc_litedramcore_interface_bank4_wdata_ready; +wire soc_litedramcore_interface_bank4_we; +wire [21:0] soc_litedramcore_interface_bank5_addr; +wire soc_litedramcore_interface_bank5_lock; +wire soc_litedramcore_interface_bank5_rdata_valid; +wire soc_litedramcore_interface_bank5_ready; +wire soc_litedramcore_interface_bank5_valid; +wire soc_litedramcore_interface_bank5_wdata_ready; +wire soc_litedramcore_interface_bank5_we; +wire [21:0] soc_litedramcore_interface_bank6_addr; +wire soc_litedramcore_interface_bank6_lock; +wire soc_litedramcore_interface_bank6_rdata_valid; +wire soc_litedramcore_interface_bank6_ready; +wire soc_litedramcore_interface_bank6_valid; +wire soc_litedramcore_interface_bank6_wdata_ready; +wire soc_litedramcore_interface_bank6_we; +wire [21:0] soc_litedramcore_interface_bank7_addr; +wire soc_litedramcore_interface_bank7_lock; +wire soc_litedramcore_interface_bank7_rdata_valid; +wire soc_litedramcore_interface_bank7_ready; +wire soc_litedramcore_interface_bank7_valid; +wire soc_litedramcore_interface_bank7_wdata_ready; +wire soc_litedramcore_interface_bank7_we; +wire [127:0] soc_litedramcore_interface_rdata; +reg [127:0] soc_litedramcore_interface_wdata = 128'd0; +reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0; +reg soc_litedramcore_master_p0_act_n = 1'd1; +reg [14:0] soc_litedramcore_master_p0_address = 15'd0; +reg [2:0] soc_litedramcore_master_p0_bank = 3'd0; +reg soc_litedramcore_master_p0_cas_n = 1'd1; +reg soc_litedramcore_master_p0_cke = 1'd0; +reg soc_litedramcore_master_p0_cs_n = 1'd1; +reg soc_litedramcore_master_p0_odt = 1'd0; +reg soc_litedramcore_master_p0_ras_n = 1'd1; +wire [31:0] soc_litedramcore_master_p0_rddata; +reg soc_litedramcore_master_p0_rddata_en = 1'd0; +wire soc_litedramcore_master_p0_rddata_valid; +reg soc_litedramcore_master_p0_reset_n = 1'd0; +reg soc_litedramcore_master_p0_we_n = 1'd1; +reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0; +reg soc_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p1_act_n = 1'd1; +reg [14:0] soc_litedramcore_master_p1_address = 15'd0; +reg [2:0] soc_litedramcore_master_p1_bank = 3'd0; +reg soc_litedramcore_master_p1_cas_n = 1'd1; +reg soc_litedramcore_master_p1_cke = 1'd0; +reg soc_litedramcore_master_p1_cs_n = 1'd1; +reg soc_litedramcore_master_p1_odt = 1'd0; +reg soc_litedramcore_master_p1_ras_n = 1'd1; +wire [31:0] soc_litedramcore_master_p1_rddata; +reg soc_litedramcore_master_p1_rddata_en = 1'd0; +wire soc_litedramcore_master_p1_rddata_valid; +reg soc_litedramcore_master_p1_reset_n = 1'd0; +reg soc_litedramcore_master_p1_we_n = 1'd1; +reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0; +reg soc_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p2_act_n = 1'd1; +reg [14:0] soc_litedramcore_master_p2_address = 15'd0; +reg [2:0] soc_litedramcore_master_p2_bank = 3'd0; +reg soc_litedramcore_master_p2_cas_n = 1'd1; +reg soc_litedramcore_master_p2_cke = 1'd0; +reg soc_litedramcore_master_p2_cs_n = 1'd1; +reg soc_litedramcore_master_p2_odt = 1'd0; +reg soc_litedramcore_master_p2_ras_n = 1'd1; +wire [31:0] soc_litedramcore_master_p2_rddata; +reg soc_litedramcore_master_p2_rddata_en = 1'd0; +wire soc_litedramcore_master_p2_rddata_valid; +reg soc_litedramcore_master_p2_reset_n = 1'd0; +reg soc_litedramcore_master_p2_we_n = 1'd1; +reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0; +reg soc_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p3_act_n = 1'd1; +reg [14:0] soc_litedramcore_master_p3_address = 15'd0; +reg [2:0] soc_litedramcore_master_p3_bank = 3'd0; +reg soc_litedramcore_master_p3_cas_n = 1'd1; +reg soc_litedramcore_master_p3_cke = 1'd0; +reg soc_litedramcore_master_p3_cs_n = 1'd1; +reg soc_litedramcore_master_p3_odt = 1'd0; +reg soc_litedramcore_master_p3_ras_n = 1'd1; +wire [31:0] soc_litedramcore_master_p3_rddata; +reg soc_litedramcore_master_p3_rddata_en = 1'd0; +wire soc_litedramcore_master_p3_rddata_valid; +reg soc_litedramcore_master_p3_reset_n = 1'd0; +reg soc_litedramcore_master_p3_we_n = 1'd1; +reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0; +reg soc_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0; +wire soc_litedramcore_max_time0; +wire soc_litedramcore_max_time1; +reg [14:0] soc_litedramcore_nop_a = 15'd0; +reg [2:0] soc_litedramcore_nop_ba = 3'd0; +wire soc_litedramcore_odt; +reg [14:0] soc_litedramcore_phaseinjector0_address_storage = 15'd0; +reg soc_litedramcore_phaseinjector0_address_wr_stb = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector0_baddress_wr_stb = 1'd0; +wire soc_litedramcore_phaseinjector0_cas; +wire soc_litedramcore_phaseinjector0_command_issue_r; +reg soc_litedramcore_phaseinjector0_command_issue_re = 1'd0; +reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg soc_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg [7:0] soc_litedramcore_phaseinjector0_command_storage = 8'd0; +reg soc_litedramcore_phaseinjector0_command_wr_stb = 1'd0; +wire soc_litedramcore_phaseinjector0_cs; +wire soc_litedramcore_phaseinjector0_cs_bottom; +wire soc_litedramcore_phaseinjector0_cs_top; +wire soc_litedramcore_phaseinjector0_ras; +wire soc_litedramcore_phaseinjector0_rddata_rd_stb; +reg [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0; +reg soc_litedramcore_phaseinjector0_rddata_wr_stb = 1'd0; +wire soc_litedramcore_phaseinjector0_rden; +wire soc_litedramcore_phaseinjector0_we; +reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector0_wrdata_wr_stb = 1'd0; +wire soc_litedramcore_phaseinjector0_wren; +reg [14:0] soc_litedramcore_phaseinjector1_address_storage = 15'd0; +reg soc_litedramcore_phaseinjector1_address_wr_stb = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector1_baddress_wr_stb = 1'd0; +wire soc_litedramcore_phaseinjector1_cas; +wire soc_litedramcore_phaseinjector1_command_issue_r; +reg soc_litedramcore_phaseinjector1_command_issue_re = 1'd0; +reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg soc_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg [7:0] soc_litedramcore_phaseinjector1_command_storage = 8'd0; +reg soc_litedramcore_phaseinjector1_command_wr_stb = 1'd0; +wire soc_litedramcore_phaseinjector1_cs; +wire soc_litedramcore_phaseinjector1_cs_bottom; +wire soc_litedramcore_phaseinjector1_cs_top; +wire soc_litedramcore_phaseinjector1_ras; +wire soc_litedramcore_phaseinjector1_rddata_rd_stb; +reg [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0; +reg soc_litedramcore_phaseinjector1_rddata_wr_stb = 1'd0; +wire soc_litedramcore_phaseinjector1_rden; +wire soc_litedramcore_phaseinjector1_we; +reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector1_wrdata_wr_stb = 1'd0; +wire soc_litedramcore_phaseinjector1_wren; +reg [14:0] soc_litedramcore_phaseinjector2_address_storage = 15'd0; +reg soc_litedramcore_phaseinjector2_address_wr_stb = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector2_baddress_wr_stb = 1'd0; +wire soc_litedramcore_phaseinjector2_cas; +wire soc_litedramcore_phaseinjector2_command_issue_r; +reg soc_litedramcore_phaseinjector2_command_issue_re = 1'd0; +reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg soc_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg [7:0] soc_litedramcore_phaseinjector2_command_storage = 8'd0; +reg soc_litedramcore_phaseinjector2_command_wr_stb = 1'd0; +wire soc_litedramcore_phaseinjector2_cs; +wire soc_litedramcore_phaseinjector2_cs_bottom; +wire soc_litedramcore_phaseinjector2_cs_top; +wire soc_litedramcore_phaseinjector2_ras; +wire soc_litedramcore_phaseinjector2_rddata_rd_stb; +reg [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0; +reg soc_litedramcore_phaseinjector2_rddata_wr_stb = 1'd0; +wire soc_litedramcore_phaseinjector2_rden; +wire soc_litedramcore_phaseinjector2_we; +reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector2_wrdata_wr_stb = 1'd0; +wire soc_litedramcore_phaseinjector2_wren; +reg [14:0] soc_litedramcore_phaseinjector3_address_storage = 15'd0; +reg soc_litedramcore_phaseinjector3_address_wr_stb = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector3_baddress_wr_stb = 1'd0; +wire soc_litedramcore_phaseinjector3_cas; +wire soc_litedramcore_phaseinjector3_command_issue_r; +reg soc_litedramcore_phaseinjector3_command_issue_re = 1'd0; +reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg soc_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg [7:0] soc_litedramcore_phaseinjector3_command_storage = 8'd0; +reg soc_litedramcore_phaseinjector3_command_wr_stb = 1'd0; +wire soc_litedramcore_phaseinjector3_cs; +wire soc_litedramcore_phaseinjector3_cs_bottom; +wire soc_litedramcore_phaseinjector3_cs_top; +wire soc_litedramcore_phaseinjector3_ras; +wire soc_litedramcore_phaseinjector3_rddata_rd_stb; +reg [31:0] soc_litedramcore_phaseinjector3_rddata_status = 32'd0; +reg soc_litedramcore_phaseinjector3_rddata_wr_stb = 1'd0; +wire soc_litedramcore_phaseinjector3_rden; +wire soc_litedramcore_phaseinjector3_we; +reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector3_wrdata_wr_stb = 1'd0; +wire soc_litedramcore_phaseinjector3_wren; +reg soc_litedramcore_postponer_count = 1'd0; +wire soc_litedramcore_postponer_req_i; +reg soc_litedramcore_postponer_req_o = 1'd0; +wire soc_litedramcore_ras_allowed; +wire soc_litedramcore_read_available; +wire soc_litedramcore_reset_n; +wire soc_litedramcore_sel; +reg soc_litedramcore_sequencer_count = 1'd0; +wire soc_litedramcore_sequencer_done0; +reg soc_litedramcore_sequencer_done1 = 1'd0; +reg soc_litedramcore_sequencer_start0 = 1'd0; +wire soc_litedramcore_sequencer_start1; +reg [5:0] soc_litedramcore_sequencer_trigger = 6'd0; +wire soc_litedramcore_slave_p0_act_n; +wire [14:0] soc_litedramcore_slave_p0_address; +wire [2:0] soc_litedramcore_slave_p0_bank; +wire soc_litedramcore_slave_p0_cas_n; +wire soc_litedramcore_slave_p0_cke; +wire soc_litedramcore_slave_p0_cs_n; +wire soc_litedramcore_slave_p0_odt; +wire soc_litedramcore_slave_p0_ras_n; +reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0; +wire soc_litedramcore_slave_p0_rddata_en; +reg soc_litedramcore_slave_p0_rddata_valid = 1'd0; +wire soc_litedramcore_slave_p0_reset_n; +wire soc_litedramcore_slave_p0_we_n; +wire [31:0] soc_litedramcore_slave_p0_wrdata; +wire soc_litedramcore_slave_p0_wrdata_en; +wire [3:0] soc_litedramcore_slave_p0_wrdata_mask; +wire soc_litedramcore_slave_p1_act_n; +wire [14:0] soc_litedramcore_slave_p1_address; +wire [2:0] soc_litedramcore_slave_p1_bank; +wire soc_litedramcore_slave_p1_cas_n; +wire soc_litedramcore_slave_p1_cke; +wire soc_litedramcore_slave_p1_cs_n; +wire soc_litedramcore_slave_p1_odt; +wire soc_litedramcore_slave_p1_ras_n; +reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0; +wire soc_litedramcore_slave_p1_rddata_en; +reg soc_litedramcore_slave_p1_rddata_valid = 1'd0; +wire soc_litedramcore_slave_p1_reset_n; +wire soc_litedramcore_slave_p1_we_n; +wire [31:0] soc_litedramcore_slave_p1_wrdata; +wire soc_litedramcore_slave_p1_wrdata_en; +wire [3:0] soc_litedramcore_slave_p1_wrdata_mask; +wire soc_litedramcore_slave_p2_act_n; +wire [14:0] soc_litedramcore_slave_p2_address; +wire [2:0] soc_litedramcore_slave_p2_bank; +wire soc_litedramcore_slave_p2_cas_n; +wire soc_litedramcore_slave_p2_cke; +wire soc_litedramcore_slave_p2_cs_n; +wire soc_litedramcore_slave_p2_odt; +wire soc_litedramcore_slave_p2_ras_n; +reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0; +wire soc_litedramcore_slave_p2_rddata_en; +reg soc_litedramcore_slave_p2_rddata_valid = 1'd0; +wire soc_litedramcore_slave_p2_reset_n; +wire soc_litedramcore_slave_p2_we_n; +wire [31:0] soc_litedramcore_slave_p2_wrdata; +wire soc_litedramcore_slave_p2_wrdata_en; +wire [3:0] soc_litedramcore_slave_p2_wrdata_mask; +wire soc_litedramcore_slave_p3_act_n; +wire [14:0] soc_litedramcore_slave_p3_address; +wire [2:0] soc_litedramcore_slave_p3_bank; +wire soc_litedramcore_slave_p3_cas_n; +wire soc_litedramcore_slave_p3_cke; +wire soc_litedramcore_slave_p3_cs_n; +wire soc_litedramcore_slave_p3_odt; +wire soc_litedramcore_slave_p3_ras_n; +reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0; +wire soc_litedramcore_slave_p3_rddata_en; +reg soc_litedramcore_slave_p3_rddata_valid = 1'd0; +wire soc_litedramcore_slave_p3_reset_n; +wire soc_litedramcore_slave_p3_we_n; +wire [31:0] soc_litedramcore_slave_p3_wrdata; +wire soc_litedramcore_slave_p3_wrdata_en; +wire [3:0] soc_litedramcore_slave_p3_wrdata_mask; +reg soc_litedramcore_steerer0 = 1'd1; +reg soc_litedramcore_steerer1 = 1'd1; +reg soc_litedramcore_steerer2 = 1'd1; +reg soc_litedramcore_steerer3 = 1'd1; +reg soc_litedramcore_steerer4 = 1'd1; +reg soc_litedramcore_steerer5 = 1'd1; +reg soc_litedramcore_steerer6 = 1'd1; +reg soc_litedramcore_steerer7 = 1'd1; +reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0; +reg [3:0] soc_litedramcore_storage = 4'd1; +reg soc_litedramcore_tccdcon_count = 1'd0; +reg soc_litedramcore_tccdcon_ready = 1'd0; +wire soc_litedramcore_tccdcon_valid; +wire [1:0] soc_litedramcore_tfawcon_count; +reg soc_litedramcore_tfawcon_ready = 1'd1; +wire soc_litedramcore_tfawcon_valid; +reg [3:0] soc_litedramcore_tfawcon_window = 4'd0; +reg [4:0] soc_litedramcore_time0 = 5'd0; +reg [3:0] soc_litedramcore_time1 = 4'd0; +wire [9:0] soc_litedramcore_timer_count0; +reg [9:0] soc_litedramcore_timer_count1 = 10'd585; +wire soc_litedramcore_timer_done0; +wire soc_litedramcore_timer_done1; +wire soc_litedramcore_timer_wait; +reg soc_litedramcore_trrdcon_count = 1'd0; +reg soc_litedramcore_trrdcon_ready = 1'd0; +wire soc_litedramcore_trrdcon_valid; +reg [2:0] soc_litedramcore_twtrcon_count = 3'd0; +reg soc_litedramcore_twtrcon_ready = 1'd0; +wire soc_litedramcore_twtrcon_valid; +wire soc_litedramcore_wants_refresh; +wire soc_litedramcore_wants_zqcs; +reg soc_litedramcore_wr_stb = 1'd0; +wire soc_litedramcore_write_available; +reg soc_litedramcore_zqcs_executer_done = 1'd0; +reg soc_litedramcore_zqcs_executer_start = 1'd0; +reg [4:0] soc_litedramcore_zqcs_executer_trigger = 5'd0; +wire [26:0] soc_litedramcore_zqcs_timer_count0; +reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd74999999; +wire soc_litedramcore_zqcs_timer_done0; +wire soc_litedramcore_zqcs_timer_done1; +wire soc_litedramcore_zqcs_timer_wait; +reg soc_user_enable = 1'd0; +wire [24:0] soc_user_port_cmd_payload_addr; +wire soc_user_port_cmd_payload_we; +wire soc_user_port_cmd_ready; +wire soc_user_port_cmd_valid; +wire [127:0] soc_user_port_rdata_payload_data; +wire soc_user_port_rdata_ready; +wire soc_user_port_rdata_valid; +wire [127:0] soc_user_port_wdata_payload_data; +wire [15:0] soc_user_port_wdata_payload_we; +wire soc_user_port_wdata_ready; +wire soc_user_port_wdata_valid; +wire soc_wb_bus_ack; +wire [29:0] soc_wb_bus_adr; +wire [1:0] soc_wb_bus_bte; +wire [2:0] soc_wb_bus_cti; +wire soc_wb_bus_cyc; +wire [31:0] soc_wb_bus_dat_r; +wire [31:0] soc_wb_bus_dat_w; +wire soc_wb_bus_err; +wire [3:0] soc_wb_bus_sel; +wire soc_wb_bus_stb; +wire soc_wb_bus_we; +reg [1:0] state = 2'd0; +wire sys_clk; +wire sys_rst; +reg t_self0 = 1'd0; +reg t_self1 = 1'd0; +reg t_self2 = 1'd0; +reg t_self3 = 1'd0; +reg t_self4 = 1'd0; +reg t_self5 = 1'd0; +wire wait_1; +wire we; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign init_done = soc_init_done_storage; +assign init_error = soc_init_error_storage; +assign soc_wb_bus_adr = wb_ctrl_adr; +assign soc_wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = soc_wb_bus_dat_r; +assign soc_wb_bus_sel = wb_ctrl_sel; +assign soc_wb_bus_cyc = wb_ctrl_cyc; +assign soc_wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = soc_wb_bus_ack; +assign soc_wb_bus_we = wb_ctrl_we; +assign soc_wb_bus_cti = wb_ctrl_cti; +assign soc_wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = soc_wb_bus_err; +assign user_clk = sys_clk; +assign user_rst = sys_rst; +assign soc_user_port_cmd_valid = (user_port_native_0_cmd_valid & soc_user_enable); +assign user_port_native_0_cmd_ready = (soc_user_port_cmd_ready & soc_user_enable); +assign soc_user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign soc_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign soc_user_port_wdata_valid = (user_port_native_0_wdata_valid & soc_user_enable); +assign user_port_native_0_wdata_ready = (soc_user_port_wdata_ready & soc_user_enable); +assign soc_user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign soc_user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = (soc_user_port_rdata_valid & soc_user_enable); +assign soc_user_port_rdata_ready = (user_port_native_0_rdata_ready & soc_user_enable); +assign user_port_native_0_rdata_data = soc_user_port_rdata_payload_data; +assign shared_adr = rhs_self0; +assign shared_dat_w = rhs_self1; +assign shared_sel = rhs_self2; +assign shared_cyc = rhs_self3; +assign shared_stb = rhs_self4; +assign shared_we = rhs_self5; +assign shared_cti = rhs_self6; +assign shared_bte = rhs_self7; +assign soc_wb_bus_dat_r = shared_dat_r; +assign soc_wb_bus_ack = (shared_ack & (grant == 1'd0)); +assign soc_wb_bus_err = (shared_err & (grant == 1'd0)); +assign request = {soc_wb_bus_cyc}; +assign grant = 1'd0; +assign master = (shared_adr[29:14] == 1'd0); +assign interface0_adr = shared_adr; +assign interface0_dat_w = shared_dat_w; +assign interface0_sel = shared_sel; +assign interface0_stb = shared_stb; +assign interface0_we = shared_we; +assign interface0_cti = shared_cti; +assign interface0_bte = shared_bte; +assign interface0_cyc = (shared_cyc & master); +assign shared_err = interface0_err; +assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack)); +always @(*) begin + error = 1'd0; + shared_ack = 1'd0; + shared_dat_r = 32'd0; + shared_ack = interface0_ack; + shared_dat_r = ({32{slaves}} & interface0_dat_r); + if (done) begin + shared_dat_r = 32'hffffffff; + shared_ack = 1'd1; + error = 1'd1; + end +end +assign done = (count == 1'd0); +assign sys_clk = clk; +assign por_clk = clk; +assign sys_rst = soc_int_rst; +always @(*) begin + soc_ddrphy_activates0 = 4'd0; + soc_ddrphy_activates0[0] = soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates0[1] = soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates0[2] = soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates0[3] = soc_ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + soc_ddrphy_bankmodel0_activate = 1'd0; + soc_ddrphy_bankmodel0_activate_row = 15'd0; + case (soc_ddrphy_activates0) + 1'd1: begin + soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p0_bank == 1'd0); + soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p1_bank == 1'd0); + soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p2_bank == 1'd0); + soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p3_bank == 1'd0); + soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_precharges0 = 4'd0; + soc_ddrphy_precharges0[0] = soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges0[1] = soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges0[2] = soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges0[3] = soc_ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + soc_ddrphy_bankmodel0_precharge = 1'd0; + case (soc_ddrphy_precharges0) + 1'd1: begin + soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p0_bank == 1'd0) | soc_ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p1_bank == 1'd0) | soc_ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p2_bank == 1'd0) | soc_ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p3_bank == 1'd0) | soc_ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + soc_ddrphy_writes0 = 4'd0; + soc_ddrphy_writes0[0] = soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes0[1] = soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes0[2] = soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes0[3] = soc_ddrphy_dfiphasemodel3_write; +end +always @(*) begin + soc_ddrphy_bank_write0 = 1'd0; + soc_ddrphy_bank_write_col0 = 10'd0; + case (soc_ddrphy_writes0) + 1'd1: begin + soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p0_bank == 1'd0); + soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p1_bank == 1'd0); + soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p2_bank == 1'd0); + soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p3_bank == 1'd0); + soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p3_address; + end + endcase +end +assign soc_ddrphy_bankmodel0_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; +assign soc_ddrphy_bankmodel0_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; +assign soc_ddrphy_bankmodel0_write = soc_ddrphy_new_bank_write0; +assign soc_ddrphy_bankmodel0_write_col = soc_ddrphy_new_bank_write_col0; +always @(*) begin + soc_ddrphy_reads0 = 4'd0; + soc_ddrphy_reads0[0] = soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads0[1] = soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads0[2] = soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads0[3] = soc_ddrphy_dfiphasemodel3_read; +end +always @(*) begin + soc_ddrphy_bankmodel0_read = 1'd0; + soc_ddrphy_bankmodel0_read_col = 10'd0; + case (soc_ddrphy_reads0) + 1'd1: begin + soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p0_bank == 1'd0); + soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p1_bank == 1'd0); + soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p2_bank == 1'd0); + soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p3_bank == 1'd0); + soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_activates1 = 4'd0; + soc_ddrphy_activates1[0] = soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates1[1] = soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates1[2] = soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates1[3] = soc_ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + soc_ddrphy_bankmodel1_activate = 1'd0; + soc_ddrphy_bankmodel1_activate_row = 15'd0; + case (soc_ddrphy_activates1) + 1'd1: begin + soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p0_bank == 1'd1); + soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p1_bank == 1'd1); + soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p2_bank == 1'd1); + soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p3_bank == 1'd1); + soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_precharges1 = 4'd0; + soc_ddrphy_precharges1[0] = soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges1[1] = soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges1[2] = soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges1[3] = soc_ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + soc_ddrphy_bankmodel1_precharge = 1'd0; + case (soc_ddrphy_precharges1) + 1'd1: begin + soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p0_bank == 1'd1) | soc_ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p1_bank == 1'd1) | soc_ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p2_bank == 1'd1) | soc_ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p3_bank == 1'd1) | soc_ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + soc_ddrphy_writes1 = 4'd0; + soc_ddrphy_writes1[0] = soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes1[1] = soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes1[2] = soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes1[3] = soc_ddrphy_dfiphasemodel3_write; +end +always @(*) begin + soc_ddrphy_bank_write1 = 1'd0; + soc_ddrphy_bank_write_col1 = 10'd0; + case (soc_ddrphy_writes1) + 1'd1: begin + soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p0_bank == 1'd1); + soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p1_bank == 1'd1); + soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p2_bank == 1'd1); + soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p3_bank == 1'd1); + soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p3_address; + end + endcase +end +assign soc_ddrphy_bankmodel1_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; +assign soc_ddrphy_bankmodel1_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; +assign soc_ddrphy_bankmodel1_write = soc_ddrphy_new_bank_write1; +assign soc_ddrphy_bankmodel1_write_col = soc_ddrphy_new_bank_write_col1; +always @(*) begin + soc_ddrphy_reads1 = 4'd0; + soc_ddrphy_reads1[0] = soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads1[1] = soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads1[2] = soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads1[3] = soc_ddrphy_dfiphasemodel3_read; +end +always @(*) begin + soc_ddrphy_bankmodel1_read = 1'd0; + soc_ddrphy_bankmodel1_read_col = 10'd0; + case (soc_ddrphy_reads1) + 1'd1: begin + soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p0_bank == 1'd1); + soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p1_bank == 1'd1); + soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p2_bank == 1'd1); + soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p3_bank == 1'd1); + soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_activates2 = 4'd0; + soc_ddrphy_activates2[0] = soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates2[1] = soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates2[2] = soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates2[3] = soc_ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + soc_ddrphy_bankmodel2_activate = 1'd0; + soc_ddrphy_bankmodel2_activate_row = 15'd0; + case (soc_ddrphy_activates2) + 1'd1: begin + soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p0_bank == 2'd2); + soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p1_bank == 2'd2); + soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p2_bank == 2'd2); + soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p3_bank == 2'd2); + soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_precharges2 = 4'd0; + soc_ddrphy_precharges2[0] = soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges2[1] = soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges2[2] = soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges2[3] = soc_ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + soc_ddrphy_bankmodel2_precharge = 1'd0; + case (soc_ddrphy_precharges2) + 1'd1: begin + soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p0_bank == 2'd2) | soc_ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p1_bank == 2'd2) | soc_ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p2_bank == 2'd2) | soc_ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p3_bank == 2'd2) | soc_ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + soc_ddrphy_writes2 = 4'd0; + soc_ddrphy_writes2[0] = soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes2[1] = soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes2[2] = soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes2[3] = soc_ddrphy_dfiphasemodel3_write; +end +always @(*) begin + soc_ddrphy_bank_write2 = 1'd0; + soc_ddrphy_bank_write_col2 = 10'd0; + case (soc_ddrphy_writes2) + 1'd1: begin + soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p0_bank == 2'd2); + soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p1_bank == 2'd2); + soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p2_bank == 2'd2); + soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p3_bank == 2'd2); + soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p3_address; + end + endcase +end +assign soc_ddrphy_bankmodel2_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; +assign soc_ddrphy_bankmodel2_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; +assign soc_ddrphy_bankmodel2_write = soc_ddrphy_new_bank_write2; +assign soc_ddrphy_bankmodel2_write_col = soc_ddrphy_new_bank_write_col2; +always @(*) begin + soc_ddrphy_reads2 = 4'd0; + soc_ddrphy_reads2[0] = soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads2[1] = soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads2[2] = soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads2[3] = soc_ddrphy_dfiphasemodel3_read; +end +always @(*) begin + soc_ddrphy_bankmodel2_read = 1'd0; + soc_ddrphy_bankmodel2_read_col = 10'd0; + case (soc_ddrphy_reads2) + 1'd1: begin + soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p0_bank == 2'd2); + soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p1_bank == 2'd2); + soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p2_bank == 2'd2); + soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p3_bank == 2'd2); + soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_activates3 = 4'd0; + soc_ddrphy_activates3[0] = soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates3[1] = soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates3[2] = soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates3[3] = soc_ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + soc_ddrphy_bankmodel3_activate = 1'd0; + soc_ddrphy_bankmodel3_activate_row = 15'd0; + case (soc_ddrphy_activates3) + 1'd1: begin + soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p0_bank == 2'd3); + soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p1_bank == 2'd3); + soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p2_bank == 2'd3); + soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p3_bank == 2'd3); + soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_precharges3 = 4'd0; + soc_ddrphy_precharges3[0] = soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges3[1] = soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges3[2] = soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges3[3] = soc_ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + soc_ddrphy_bankmodel3_precharge = 1'd0; + case (soc_ddrphy_precharges3) + 1'd1: begin + soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p0_bank == 2'd3) | soc_ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p1_bank == 2'd3) | soc_ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p2_bank == 2'd3) | soc_ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p3_bank == 2'd3) | soc_ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + soc_ddrphy_writes3 = 4'd0; + soc_ddrphy_writes3[0] = soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes3[1] = soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes3[2] = soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes3[3] = soc_ddrphy_dfiphasemodel3_write; +end +always @(*) begin + soc_ddrphy_bank_write3 = 1'd0; + soc_ddrphy_bank_write_col3 = 10'd0; + case (soc_ddrphy_writes3) + 1'd1: begin + soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p0_bank == 2'd3); + soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p1_bank == 2'd3); + soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p2_bank == 2'd3); + soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p3_bank == 2'd3); + soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p3_address; + end + endcase +end +assign soc_ddrphy_bankmodel3_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; +assign soc_ddrphy_bankmodel3_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; +assign soc_ddrphy_bankmodel3_write = soc_ddrphy_new_bank_write3; +assign soc_ddrphy_bankmodel3_write_col = soc_ddrphy_new_bank_write_col3; +always @(*) begin + soc_ddrphy_reads3 = 4'd0; + soc_ddrphy_reads3[0] = soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads3[1] = soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads3[2] = soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads3[3] = soc_ddrphy_dfiphasemodel3_read; +end +always @(*) begin + soc_ddrphy_bankmodel3_read = 1'd0; + soc_ddrphy_bankmodel3_read_col = 10'd0; + case (soc_ddrphy_reads3) + 1'd1: begin + soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p0_bank == 2'd3); + soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p1_bank == 2'd3); + soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p2_bank == 2'd3); + soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p3_bank == 2'd3); + soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_activates4 = 4'd0; + soc_ddrphy_activates4[0] = soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates4[1] = soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates4[2] = soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates4[3] = soc_ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + soc_ddrphy_bankmodel4_activate = 1'd0; + soc_ddrphy_bankmodel4_activate_row = 15'd0; + case (soc_ddrphy_activates4) + 1'd1: begin + soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p0_bank == 3'd4); + soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p1_bank == 3'd4); + soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p2_bank == 3'd4); + soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p3_bank == 3'd4); + soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_precharges4 = 4'd0; + soc_ddrphy_precharges4[0] = soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges4[1] = soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges4[2] = soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges4[3] = soc_ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + soc_ddrphy_bankmodel4_precharge = 1'd0; + case (soc_ddrphy_precharges4) + 1'd1: begin + soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd4) | soc_ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd4) | soc_ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd4) | soc_ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd4) | soc_ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + soc_ddrphy_writes4 = 4'd0; + soc_ddrphy_writes4[0] = soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes4[1] = soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes4[2] = soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes4[3] = soc_ddrphy_dfiphasemodel3_write; +end +always @(*) begin + soc_ddrphy_bank_write4 = 1'd0; + soc_ddrphy_bank_write_col4 = 10'd0; + case (soc_ddrphy_writes4) + 1'd1: begin + soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p0_bank == 3'd4); + soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p1_bank == 3'd4); + soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p2_bank == 3'd4); + soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p3_bank == 3'd4); + soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p3_address; + end + endcase +end +assign soc_ddrphy_bankmodel4_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; +assign soc_ddrphy_bankmodel4_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; +assign soc_ddrphy_bankmodel4_write = soc_ddrphy_new_bank_write4; +assign soc_ddrphy_bankmodel4_write_col = soc_ddrphy_new_bank_write_col4; +always @(*) begin + soc_ddrphy_reads4 = 4'd0; + soc_ddrphy_reads4[0] = soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads4[1] = soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads4[2] = soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads4[3] = soc_ddrphy_dfiphasemodel3_read; +end +always @(*) begin + soc_ddrphy_bankmodel4_read = 1'd0; + soc_ddrphy_bankmodel4_read_col = 10'd0; + case (soc_ddrphy_reads4) + 1'd1: begin + soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p0_bank == 3'd4); + soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p1_bank == 3'd4); + soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p2_bank == 3'd4); + soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p3_bank == 3'd4); + soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_activates5 = 4'd0; + soc_ddrphy_activates5[0] = soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates5[1] = soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates5[2] = soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates5[3] = soc_ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + soc_ddrphy_bankmodel5_activate = 1'd0; + soc_ddrphy_bankmodel5_activate_row = 15'd0; + case (soc_ddrphy_activates5) + 1'd1: begin + soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p0_bank == 3'd5); + soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p1_bank == 3'd5); + soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p2_bank == 3'd5); + soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p3_bank == 3'd5); + soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_precharges5 = 4'd0; + soc_ddrphy_precharges5[0] = soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges5[1] = soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges5[2] = soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges5[3] = soc_ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + soc_ddrphy_bankmodel5_precharge = 1'd0; + case (soc_ddrphy_precharges5) + 1'd1: begin + soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd5) | soc_ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd5) | soc_ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd5) | soc_ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd5) | soc_ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + soc_ddrphy_writes5 = 4'd0; + soc_ddrphy_writes5[0] = soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes5[1] = soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes5[2] = soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes5[3] = soc_ddrphy_dfiphasemodel3_write; +end +always @(*) begin + soc_ddrphy_bank_write5 = 1'd0; + soc_ddrphy_bank_write_col5 = 10'd0; + case (soc_ddrphy_writes5) + 1'd1: begin + soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p0_bank == 3'd5); + soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p1_bank == 3'd5); + soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p2_bank == 3'd5); + soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p3_bank == 3'd5); + soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p3_address; + end + endcase +end +assign soc_ddrphy_bankmodel5_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; +assign soc_ddrphy_bankmodel5_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; +assign soc_ddrphy_bankmodel5_write = soc_ddrphy_new_bank_write5; +assign soc_ddrphy_bankmodel5_write_col = soc_ddrphy_new_bank_write_col5; +always @(*) begin + soc_ddrphy_reads5 = 4'd0; + soc_ddrphy_reads5[0] = soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads5[1] = soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads5[2] = soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads5[3] = soc_ddrphy_dfiphasemodel3_read; +end +always @(*) begin + soc_ddrphy_bankmodel5_read = 1'd0; + soc_ddrphy_bankmodel5_read_col = 10'd0; + case (soc_ddrphy_reads5) + 1'd1: begin + soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p0_bank == 3'd5); + soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p1_bank == 3'd5); + soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p2_bank == 3'd5); + soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p3_bank == 3'd5); + soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_activates6 = 4'd0; + soc_ddrphy_activates6[0] = soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates6[1] = soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates6[2] = soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates6[3] = soc_ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + soc_ddrphy_bankmodel6_activate = 1'd0; + soc_ddrphy_bankmodel6_activate_row = 15'd0; + case (soc_ddrphy_activates6) + 1'd1: begin + soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p0_bank == 3'd6); + soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p1_bank == 3'd6); + soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p2_bank == 3'd6); + soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p3_bank == 3'd6); + soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_precharges6 = 4'd0; + soc_ddrphy_precharges6[0] = soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges6[1] = soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges6[2] = soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges6[3] = soc_ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + soc_ddrphy_bankmodel6_precharge = 1'd0; + case (soc_ddrphy_precharges6) + 1'd1: begin + soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd6) | soc_ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd6) | soc_ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd6) | soc_ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd6) | soc_ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + soc_ddrphy_writes6 = 4'd0; + soc_ddrphy_writes6[0] = soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes6[1] = soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes6[2] = soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes6[3] = soc_ddrphy_dfiphasemodel3_write; +end +always @(*) begin + soc_ddrphy_bank_write6 = 1'd0; + soc_ddrphy_bank_write_col6 = 10'd0; + case (soc_ddrphy_writes6) + 1'd1: begin + soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p0_bank == 3'd6); + soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p1_bank == 3'd6); + soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p2_bank == 3'd6); + soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p3_bank == 3'd6); + soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p3_address; + end + endcase +end +assign soc_ddrphy_bankmodel6_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; +assign soc_ddrphy_bankmodel6_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; +assign soc_ddrphy_bankmodel6_write = soc_ddrphy_new_bank_write6; +assign soc_ddrphy_bankmodel6_write_col = soc_ddrphy_new_bank_write_col6; +always @(*) begin + soc_ddrphy_reads6 = 4'd0; + soc_ddrphy_reads6[0] = soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads6[1] = soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads6[2] = soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads6[3] = soc_ddrphy_dfiphasemodel3_read; +end +always @(*) begin + soc_ddrphy_bankmodel6_read = 1'd0; + soc_ddrphy_bankmodel6_read_col = 10'd0; + case (soc_ddrphy_reads6) + 1'd1: begin + soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p0_bank == 3'd6); + soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p1_bank == 3'd6); + soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p2_bank == 3'd6); + soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p3_bank == 3'd6); + soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_activates7 = 4'd0; + soc_ddrphy_activates7[0] = soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates7[1] = soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates7[2] = soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates7[3] = soc_ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + soc_ddrphy_bankmodel7_activate = 1'd0; + soc_ddrphy_bankmodel7_activate_row = 15'd0; + case (soc_ddrphy_activates7) + 1'd1: begin + soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p0_bank == 3'd7); + soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p1_bank == 3'd7); + soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p2_bank == 3'd7); + soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p3_bank == 3'd7); + soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_precharges7 = 4'd0; + soc_ddrphy_precharges7[0] = soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges7[1] = soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges7[2] = soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges7[3] = soc_ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + soc_ddrphy_bankmodel7_precharge = 1'd0; + case (soc_ddrphy_precharges7) + 1'd1: begin + soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd7) | soc_ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd7) | soc_ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd7) | soc_ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd7) | soc_ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + soc_ddrphy_writes7 = 4'd0; + soc_ddrphy_writes7[0] = soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes7[1] = soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes7[2] = soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes7[3] = soc_ddrphy_dfiphasemodel3_write; +end +always @(*) begin + soc_ddrphy_bank_write7 = 1'd0; + soc_ddrphy_bank_write_col7 = 10'd0; + case (soc_ddrphy_writes7) + 1'd1: begin + soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p0_bank == 3'd7); + soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p1_bank == 3'd7); + soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p2_bank == 3'd7); + soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p3_bank == 3'd7); + soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p3_address; + end + endcase +end +assign soc_ddrphy_bankmodel7_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; +assign soc_ddrphy_bankmodel7_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; +assign soc_ddrphy_bankmodel7_write = soc_ddrphy_new_bank_write7; +assign soc_ddrphy_bankmodel7_write_col = soc_ddrphy_new_bank_write_col7; +always @(*) begin + soc_ddrphy_reads7 = 4'd0; + soc_ddrphy_reads7[0] = soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads7[1] = soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads7[2] = soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads7[3] = soc_ddrphy_dfiphasemodel3_read; +end +always @(*) begin + soc_ddrphy_bankmodel7_read = 1'd0; + soc_ddrphy_bankmodel7_read_col = 10'd0; + case (soc_ddrphy_reads7) + 1'd1: begin + soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p0_bank == 3'd7); + soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p1_bank == 3'd7); + soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p2_bank == 3'd7); + soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p3_bank == 3'd7); + soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p3_address; + end + endcase +end +assign soc_ddrphy_banks_read = (((((((soc_ddrphy_bankmodel0_read | soc_ddrphy_bankmodel1_read) | soc_ddrphy_bankmodel2_read) | soc_ddrphy_bankmodel3_read) | soc_ddrphy_bankmodel4_read) | soc_ddrphy_bankmodel5_read) | soc_ddrphy_bankmodel6_read) | soc_ddrphy_bankmodel7_read); +assign soc_ddrphy_banks_read_data = (((((((soc_ddrphy_bankmodel0_read_data | soc_ddrphy_bankmodel1_read_data) | soc_ddrphy_bankmodel2_read_data) | soc_ddrphy_bankmodel3_read_data) | soc_ddrphy_bankmodel4_read_data) | soc_ddrphy_bankmodel5_read_data) | soc_ddrphy_bankmodel6_read_data) | soc_ddrphy_bankmodel7_read_data); +assign {soc_ddrphy_dfi_p3_rddata_valid, soc_ddrphy_dfi_p2_rddata_valid, soc_ddrphy_dfi_p1_rddata_valid, soc_ddrphy_dfi_p0_rddata_valid} = soc_ddrphy_new_banks_read7; +assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7; +always @(*) begin + soc_ddrphy_dfiphasemodel0_activate = 1'd0; + soc_ddrphy_dfiphasemodel0_precharge = 1'd0; + if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin + soc_ddrphy_dfiphasemodel0_activate = soc_ddrphy_dfi_p0_we_n; + soc_ddrphy_dfiphasemodel0_precharge = (~soc_ddrphy_dfi_p0_we_n); + end +end +always @(*) begin + soc_ddrphy_dfiphasemodel0_read = 1'd0; + soc_ddrphy_dfiphasemodel0_write = 1'd0; + if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin + soc_ddrphy_dfiphasemodel0_write = (~soc_ddrphy_dfi_p0_we_n); + soc_ddrphy_dfiphasemodel0_read = soc_ddrphy_dfi_p0_we_n; + end +end +always @(*) begin + soc_ddrphy_dfiphasemodel1_activate = 1'd0; + soc_ddrphy_dfiphasemodel1_precharge = 1'd0; + if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin + soc_ddrphy_dfiphasemodel1_activate = soc_ddrphy_dfi_p1_we_n; + soc_ddrphy_dfiphasemodel1_precharge = (~soc_ddrphy_dfi_p1_we_n); + end +end +always @(*) begin + soc_ddrphy_dfiphasemodel1_read = 1'd0; + soc_ddrphy_dfiphasemodel1_write = 1'd0; + if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin + soc_ddrphy_dfiphasemodel1_write = (~soc_ddrphy_dfi_p1_we_n); + soc_ddrphy_dfiphasemodel1_read = soc_ddrphy_dfi_p1_we_n; + end +end +always @(*) begin + soc_ddrphy_dfiphasemodel2_activate = 1'd0; + soc_ddrphy_dfiphasemodel2_precharge = 1'd0; + if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin + soc_ddrphy_dfiphasemodel2_activate = soc_ddrphy_dfi_p2_we_n; + soc_ddrphy_dfiphasemodel2_precharge = (~soc_ddrphy_dfi_p2_we_n); + end +end +always @(*) begin + soc_ddrphy_dfiphasemodel2_read = 1'd0; + soc_ddrphy_dfiphasemodel2_write = 1'd0; + if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin + soc_ddrphy_dfiphasemodel2_write = (~soc_ddrphy_dfi_p2_we_n); + soc_ddrphy_dfiphasemodel2_read = soc_ddrphy_dfi_p2_we_n; + end +end +always @(*) begin + soc_ddrphy_dfiphasemodel3_activate = 1'd0; + soc_ddrphy_dfiphasemodel3_precharge = 1'd0; + if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin + soc_ddrphy_dfiphasemodel3_activate = soc_ddrphy_dfi_p3_we_n; + soc_ddrphy_dfiphasemodel3_precharge = (~soc_ddrphy_dfi_p3_we_n); + end +end +always @(*) begin + soc_ddrphy_dfiphasemodel3_read = 1'd0; + soc_ddrphy_dfiphasemodel3_write = 1'd0; + if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin + soc_ddrphy_dfiphasemodel3_write = (~soc_ddrphy_dfi_p3_we_n); + soc_ddrphy_dfiphasemodel3_read = soc_ddrphy_dfi_p3_we_n; + end +end +assign soc_ddrphy_bankmodel0_wraddr = slice_proxy0[25:3]; +assign soc_ddrphy_bankmodel0_rdaddr = slice_proxy1[25:3]; +always @(*) begin + soc_ddrphy_bankmodel0_read_data = 128'd0; + soc_ddrphy_bankmodel0_read_port_adr = 22'd0; + soc_ddrphy_bankmodel0_write_port_adr = 22'd0; + soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0; + soc_ddrphy_bankmodel0_write_port_we = 16'd0; + if (soc_ddrphy_bankmodel0_active) begin + soc_ddrphy_bankmodel0_write_port_adr = soc_ddrphy_bankmodel0_wraddr; + soc_ddrphy_bankmodel0_write_port_dat_w = soc_ddrphy_bankmodel0_write_data; + if (4'd8) begin + soc_ddrphy_bankmodel0_write_port_we = ({16{soc_ddrphy_bankmodel0_write}} & (~soc_ddrphy_bankmodel0_write_mask)); + end else begin + soc_ddrphy_bankmodel0_write_port_we = soc_ddrphy_bankmodel0_write; + end + if (soc_ddrphy_bankmodel0_read) begin + soc_ddrphy_bankmodel0_read_port_adr = soc_ddrphy_bankmodel0_rdaddr; + soc_ddrphy_bankmodel0_read_data = soc_ddrphy_bankmodel0_read_port_dat_r; + end + end +end +assign soc_ddrphy_bankmodel1_wraddr = slice_proxy2[25:3]; +assign soc_ddrphy_bankmodel1_rdaddr = slice_proxy3[25:3]; +always @(*) begin + soc_ddrphy_bankmodel1_read_data = 128'd0; + soc_ddrphy_bankmodel1_read_port_adr = 22'd0; + soc_ddrphy_bankmodel1_write_port_adr = 22'd0; + soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0; + soc_ddrphy_bankmodel1_write_port_we = 16'd0; + if (soc_ddrphy_bankmodel1_active) begin + soc_ddrphy_bankmodel1_write_port_adr = soc_ddrphy_bankmodel1_wraddr; + soc_ddrphy_bankmodel1_write_port_dat_w = soc_ddrphy_bankmodel1_write_data; + if (4'd8) begin + soc_ddrphy_bankmodel1_write_port_we = ({16{soc_ddrphy_bankmodel1_write}} & (~soc_ddrphy_bankmodel1_write_mask)); + end else begin + soc_ddrphy_bankmodel1_write_port_we = soc_ddrphy_bankmodel1_write; + end + if (soc_ddrphy_bankmodel1_read) begin + soc_ddrphy_bankmodel1_read_port_adr = soc_ddrphy_bankmodel1_rdaddr; + soc_ddrphy_bankmodel1_read_data = soc_ddrphy_bankmodel1_read_port_dat_r; + end + end +end +assign soc_ddrphy_bankmodel2_wraddr = slice_proxy4[25:3]; +assign soc_ddrphy_bankmodel2_rdaddr = slice_proxy5[25:3]; +always @(*) begin + soc_ddrphy_bankmodel2_read_data = 128'd0; + soc_ddrphy_bankmodel2_read_port_adr = 22'd0; + soc_ddrphy_bankmodel2_write_port_adr = 22'd0; + soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0; + soc_ddrphy_bankmodel2_write_port_we = 16'd0; + if (soc_ddrphy_bankmodel2_active) begin + soc_ddrphy_bankmodel2_write_port_adr = soc_ddrphy_bankmodel2_wraddr; + soc_ddrphy_bankmodel2_write_port_dat_w = soc_ddrphy_bankmodel2_write_data; + if (4'd8) begin + soc_ddrphy_bankmodel2_write_port_we = ({16{soc_ddrphy_bankmodel2_write}} & (~soc_ddrphy_bankmodel2_write_mask)); + end else begin + soc_ddrphy_bankmodel2_write_port_we = soc_ddrphy_bankmodel2_write; + end + if (soc_ddrphy_bankmodel2_read) begin + soc_ddrphy_bankmodel2_read_port_adr = soc_ddrphy_bankmodel2_rdaddr; + soc_ddrphy_bankmodel2_read_data = soc_ddrphy_bankmodel2_read_port_dat_r; + end + end +end +assign soc_ddrphy_bankmodel3_wraddr = slice_proxy6[25:3]; +assign soc_ddrphy_bankmodel3_rdaddr = slice_proxy7[25:3]; +always @(*) begin + soc_ddrphy_bankmodel3_read_data = 128'd0; + soc_ddrphy_bankmodel3_read_port_adr = 22'd0; + soc_ddrphy_bankmodel3_write_port_adr = 22'd0; + soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0; + soc_ddrphy_bankmodel3_write_port_we = 16'd0; + if (soc_ddrphy_bankmodel3_active) begin + soc_ddrphy_bankmodel3_write_port_adr = soc_ddrphy_bankmodel3_wraddr; + soc_ddrphy_bankmodel3_write_port_dat_w = soc_ddrphy_bankmodel3_write_data; + if (4'd8) begin + soc_ddrphy_bankmodel3_write_port_we = ({16{soc_ddrphy_bankmodel3_write}} & (~soc_ddrphy_bankmodel3_write_mask)); + end else begin + soc_ddrphy_bankmodel3_write_port_we = soc_ddrphy_bankmodel3_write; + end + if (soc_ddrphy_bankmodel3_read) begin + soc_ddrphy_bankmodel3_read_port_adr = soc_ddrphy_bankmodel3_rdaddr; + soc_ddrphy_bankmodel3_read_data = soc_ddrphy_bankmodel3_read_port_dat_r; + end + end +end +assign soc_ddrphy_bankmodel4_wraddr = slice_proxy8[25:3]; +assign soc_ddrphy_bankmodel4_rdaddr = slice_proxy9[25:3]; +always @(*) begin + soc_ddrphy_bankmodel4_read_data = 128'd0; + soc_ddrphy_bankmodel4_read_port_adr = 22'd0; + soc_ddrphy_bankmodel4_write_port_adr = 22'd0; + soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0; + soc_ddrphy_bankmodel4_write_port_we = 16'd0; + if (soc_ddrphy_bankmodel4_active) begin + soc_ddrphy_bankmodel4_write_port_adr = soc_ddrphy_bankmodel4_wraddr; + soc_ddrphy_bankmodel4_write_port_dat_w = soc_ddrphy_bankmodel4_write_data; + if (4'd8) begin + soc_ddrphy_bankmodel4_write_port_we = ({16{soc_ddrphy_bankmodel4_write}} & (~soc_ddrphy_bankmodel4_write_mask)); + end else begin + soc_ddrphy_bankmodel4_write_port_we = soc_ddrphy_bankmodel4_write; + end + if (soc_ddrphy_bankmodel4_read) begin + soc_ddrphy_bankmodel4_read_port_adr = soc_ddrphy_bankmodel4_rdaddr; + soc_ddrphy_bankmodel4_read_data = soc_ddrphy_bankmodel4_read_port_dat_r; + end + end +end +assign soc_ddrphy_bankmodel5_wraddr = slice_proxy10[25:3]; +assign soc_ddrphy_bankmodel5_rdaddr = slice_proxy11[25:3]; +always @(*) begin + soc_ddrphy_bankmodel5_read_data = 128'd0; + soc_ddrphy_bankmodel5_read_port_adr = 22'd0; + soc_ddrphy_bankmodel5_write_port_adr = 22'd0; + soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0; + soc_ddrphy_bankmodel5_write_port_we = 16'd0; + if (soc_ddrphy_bankmodel5_active) begin + soc_ddrphy_bankmodel5_write_port_adr = soc_ddrphy_bankmodel5_wraddr; + soc_ddrphy_bankmodel5_write_port_dat_w = soc_ddrphy_bankmodel5_write_data; + if (4'd8) begin + soc_ddrphy_bankmodel5_write_port_we = ({16{soc_ddrphy_bankmodel5_write}} & (~soc_ddrphy_bankmodel5_write_mask)); + end else begin + soc_ddrphy_bankmodel5_write_port_we = soc_ddrphy_bankmodel5_write; + end + if (soc_ddrphy_bankmodel5_read) begin + soc_ddrphy_bankmodel5_read_port_adr = soc_ddrphy_bankmodel5_rdaddr; + soc_ddrphy_bankmodel5_read_data = soc_ddrphy_bankmodel5_read_port_dat_r; + end + end +end +assign soc_ddrphy_bankmodel6_wraddr = slice_proxy12[25:3]; +assign soc_ddrphy_bankmodel6_rdaddr = slice_proxy13[25:3]; +always @(*) begin + soc_ddrphy_bankmodel6_read_data = 128'd0; + soc_ddrphy_bankmodel6_read_port_adr = 22'd0; + soc_ddrphy_bankmodel6_write_port_adr = 22'd0; + soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0; + soc_ddrphy_bankmodel6_write_port_we = 16'd0; + if (soc_ddrphy_bankmodel6_active) begin + soc_ddrphy_bankmodel6_write_port_adr = soc_ddrphy_bankmodel6_wraddr; + soc_ddrphy_bankmodel6_write_port_dat_w = soc_ddrphy_bankmodel6_write_data; + if (4'd8) begin + soc_ddrphy_bankmodel6_write_port_we = ({16{soc_ddrphy_bankmodel6_write}} & (~soc_ddrphy_bankmodel6_write_mask)); + end else begin + soc_ddrphy_bankmodel6_write_port_we = soc_ddrphy_bankmodel6_write; + end + if (soc_ddrphy_bankmodel6_read) begin + soc_ddrphy_bankmodel6_read_port_adr = soc_ddrphy_bankmodel6_rdaddr; + soc_ddrphy_bankmodel6_read_data = soc_ddrphy_bankmodel6_read_port_dat_r; + end + end +end +assign soc_ddrphy_bankmodel7_wraddr = slice_proxy14[25:3]; +assign soc_ddrphy_bankmodel7_rdaddr = slice_proxy15[25:3]; +always @(*) begin + soc_ddrphy_bankmodel7_read_data = 128'd0; + soc_ddrphy_bankmodel7_read_port_adr = 22'd0; + soc_ddrphy_bankmodel7_write_port_adr = 22'd0; + soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0; + soc_ddrphy_bankmodel7_write_port_we = 16'd0; + if (soc_ddrphy_bankmodel7_active) begin + soc_ddrphy_bankmodel7_write_port_adr = soc_ddrphy_bankmodel7_wraddr; + soc_ddrphy_bankmodel7_write_port_dat_w = soc_ddrphy_bankmodel7_write_data; + if (4'd8) begin + soc_ddrphy_bankmodel7_write_port_we = ({16{soc_ddrphy_bankmodel7_write}} & (~soc_ddrphy_bankmodel7_write_mask)); + end else begin + soc_ddrphy_bankmodel7_write_port_we = soc_ddrphy_bankmodel7_write; + end + if (soc_ddrphy_bankmodel7_read) begin + soc_ddrphy_bankmodel7_read_port_adr = soc_ddrphy_bankmodel7_rdaddr; + soc_ddrphy_bankmodel7_read_data = soc_ddrphy_bankmodel7_read_port_dat_r; + end + end +end +assign soc_ddrphy_dfi_p0_address = soc_litedramcore_master_p0_address; +assign soc_ddrphy_dfi_p0_bank = soc_litedramcore_master_p0_bank; +assign soc_ddrphy_dfi_p0_cas_n = soc_litedramcore_master_p0_cas_n; +assign soc_ddrphy_dfi_p0_cs_n = soc_litedramcore_master_p0_cs_n; +assign soc_ddrphy_dfi_p0_ras_n = soc_litedramcore_master_p0_ras_n; +assign soc_ddrphy_dfi_p0_we_n = soc_litedramcore_master_p0_we_n; +assign soc_ddrphy_dfi_p0_cke = soc_litedramcore_master_p0_cke; +assign soc_ddrphy_dfi_p0_odt = soc_litedramcore_master_p0_odt; +assign soc_ddrphy_dfi_p0_reset_n = soc_litedramcore_master_p0_reset_n; +assign soc_ddrphy_dfi_p0_act_n = soc_litedramcore_master_p0_act_n; +assign soc_ddrphy_dfi_p0_wrdata = soc_litedramcore_master_p0_wrdata; +assign soc_ddrphy_dfi_p0_wrdata_en = soc_litedramcore_master_p0_wrdata_en; +assign soc_ddrphy_dfi_p0_wrdata_mask = soc_litedramcore_master_p0_wrdata_mask; +assign soc_ddrphy_dfi_p0_rddata_en = soc_litedramcore_master_p0_rddata_en; +assign soc_litedramcore_master_p0_rddata = soc_ddrphy_dfi_p0_rddata; +assign soc_litedramcore_master_p0_rddata_valid = soc_ddrphy_dfi_p0_rddata_valid; +assign soc_ddrphy_dfi_p1_address = soc_litedramcore_master_p1_address; +assign soc_ddrphy_dfi_p1_bank = soc_litedramcore_master_p1_bank; +assign soc_ddrphy_dfi_p1_cas_n = soc_litedramcore_master_p1_cas_n; +assign soc_ddrphy_dfi_p1_cs_n = soc_litedramcore_master_p1_cs_n; +assign soc_ddrphy_dfi_p1_ras_n = soc_litedramcore_master_p1_ras_n; +assign soc_ddrphy_dfi_p1_we_n = soc_litedramcore_master_p1_we_n; +assign soc_ddrphy_dfi_p1_cke = soc_litedramcore_master_p1_cke; +assign soc_ddrphy_dfi_p1_odt = soc_litedramcore_master_p1_odt; +assign soc_ddrphy_dfi_p1_reset_n = soc_litedramcore_master_p1_reset_n; +assign soc_ddrphy_dfi_p1_act_n = soc_litedramcore_master_p1_act_n; +assign soc_ddrphy_dfi_p1_wrdata = soc_litedramcore_master_p1_wrdata; +assign soc_ddrphy_dfi_p1_wrdata_en = soc_litedramcore_master_p1_wrdata_en; +assign soc_ddrphy_dfi_p1_wrdata_mask = soc_litedramcore_master_p1_wrdata_mask; +assign soc_ddrphy_dfi_p1_rddata_en = soc_litedramcore_master_p1_rddata_en; +assign soc_litedramcore_master_p1_rddata = soc_ddrphy_dfi_p1_rddata; +assign soc_litedramcore_master_p1_rddata_valid = soc_ddrphy_dfi_p1_rddata_valid; +assign soc_ddrphy_dfi_p2_address = soc_litedramcore_master_p2_address; +assign soc_ddrphy_dfi_p2_bank = soc_litedramcore_master_p2_bank; +assign soc_ddrphy_dfi_p2_cas_n = soc_litedramcore_master_p2_cas_n; +assign soc_ddrphy_dfi_p2_cs_n = soc_litedramcore_master_p2_cs_n; +assign soc_ddrphy_dfi_p2_ras_n = soc_litedramcore_master_p2_ras_n; +assign soc_ddrphy_dfi_p2_we_n = soc_litedramcore_master_p2_we_n; +assign soc_ddrphy_dfi_p2_cke = soc_litedramcore_master_p2_cke; +assign soc_ddrphy_dfi_p2_odt = soc_litedramcore_master_p2_odt; +assign soc_ddrphy_dfi_p2_reset_n = soc_litedramcore_master_p2_reset_n; +assign soc_ddrphy_dfi_p2_act_n = soc_litedramcore_master_p2_act_n; +assign soc_ddrphy_dfi_p2_wrdata = soc_litedramcore_master_p2_wrdata; +assign soc_ddrphy_dfi_p2_wrdata_en = soc_litedramcore_master_p2_wrdata_en; +assign soc_ddrphy_dfi_p2_wrdata_mask = soc_litedramcore_master_p2_wrdata_mask; +assign soc_ddrphy_dfi_p2_rddata_en = soc_litedramcore_master_p2_rddata_en; +assign soc_litedramcore_master_p2_rddata = soc_ddrphy_dfi_p2_rddata; +assign soc_litedramcore_master_p2_rddata_valid = soc_ddrphy_dfi_p2_rddata_valid; +assign soc_ddrphy_dfi_p3_address = soc_litedramcore_master_p3_address; +assign soc_ddrphy_dfi_p3_bank = soc_litedramcore_master_p3_bank; +assign soc_ddrphy_dfi_p3_cas_n = soc_litedramcore_master_p3_cas_n; +assign soc_ddrphy_dfi_p3_cs_n = soc_litedramcore_master_p3_cs_n; +assign soc_ddrphy_dfi_p3_ras_n = soc_litedramcore_master_p3_ras_n; +assign soc_ddrphy_dfi_p3_we_n = soc_litedramcore_master_p3_we_n; +assign soc_ddrphy_dfi_p3_cke = soc_litedramcore_master_p3_cke; +assign soc_ddrphy_dfi_p3_odt = soc_litedramcore_master_p3_odt; +assign soc_ddrphy_dfi_p3_reset_n = soc_litedramcore_master_p3_reset_n; +assign soc_ddrphy_dfi_p3_act_n = soc_litedramcore_master_p3_act_n; +assign soc_ddrphy_dfi_p3_wrdata = soc_litedramcore_master_p3_wrdata; +assign soc_ddrphy_dfi_p3_wrdata_en = soc_litedramcore_master_p3_wrdata_en; +assign soc_ddrphy_dfi_p3_wrdata_mask = soc_litedramcore_master_p3_wrdata_mask; +assign soc_ddrphy_dfi_p3_rddata_en = soc_litedramcore_master_p3_rddata_en; +assign soc_litedramcore_master_p3_rddata = soc_ddrphy_dfi_p3_rddata; +assign soc_litedramcore_master_p3_rddata_valid = soc_ddrphy_dfi_p3_rddata_valid; +assign soc_litedramcore_slave_p0_address = soc_litedramcore_dfi_p0_address; +assign soc_litedramcore_slave_p0_bank = soc_litedramcore_dfi_p0_bank; +assign soc_litedramcore_slave_p0_cas_n = soc_litedramcore_dfi_p0_cas_n; +assign soc_litedramcore_slave_p0_cs_n = soc_litedramcore_dfi_p0_cs_n; +assign soc_litedramcore_slave_p0_ras_n = soc_litedramcore_dfi_p0_ras_n; +assign soc_litedramcore_slave_p0_we_n = soc_litedramcore_dfi_p0_we_n; +assign soc_litedramcore_slave_p0_cke = soc_litedramcore_dfi_p0_cke; +assign soc_litedramcore_slave_p0_odt = soc_litedramcore_dfi_p0_odt; +assign soc_litedramcore_slave_p0_reset_n = soc_litedramcore_dfi_p0_reset_n; +assign soc_litedramcore_slave_p0_act_n = soc_litedramcore_dfi_p0_act_n; +assign soc_litedramcore_slave_p0_wrdata = soc_litedramcore_dfi_p0_wrdata; +assign soc_litedramcore_slave_p0_wrdata_en = soc_litedramcore_dfi_p0_wrdata_en; +assign soc_litedramcore_slave_p0_wrdata_mask = soc_litedramcore_dfi_p0_wrdata_mask; +assign soc_litedramcore_slave_p0_rddata_en = soc_litedramcore_dfi_p0_rddata_en; +assign soc_litedramcore_dfi_p0_rddata = soc_litedramcore_slave_p0_rddata; +assign soc_litedramcore_dfi_p0_rddata_valid = soc_litedramcore_slave_p0_rddata_valid; +assign soc_litedramcore_slave_p1_address = soc_litedramcore_dfi_p1_address; +assign soc_litedramcore_slave_p1_bank = soc_litedramcore_dfi_p1_bank; +assign soc_litedramcore_slave_p1_cas_n = soc_litedramcore_dfi_p1_cas_n; +assign soc_litedramcore_slave_p1_cs_n = soc_litedramcore_dfi_p1_cs_n; +assign soc_litedramcore_slave_p1_ras_n = soc_litedramcore_dfi_p1_ras_n; +assign soc_litedramcore_slave_p1_we_n = soc_litedramcore_dfi_p1_we_n; +assign soc_litedramcore_slave_p1_cke = soc_litedramcore_dfi_p1_cke; +assign soc_litedramcore_slave_p1_odt = soc_litedramcore_dfi_p1_odt; +assign soc_litedramcore_slave_p1_reset_n = soc_litedramcore_dfi_p1_reset_n; +assign soc_litedramcore_slave_p1_act_n = soc_litedramcore_dfi_p1_act_n; +assign soc_litedramcore_slave_p1_wrdata = soc_litedramcore_dfi_p1_wrdata; +assign soc_litedramcore_slave_p1_wrdata_en = soc_litedramcore_dfi_p1_wrdata_en; +assign soc_litedramcore_slave_p1_wrdata_mask = soc_litedramcore_dfi_p1_wrdata_mask; +assign soc_litedramcore_slave_p1_rddata_en = soc_litedramcore_dfi_p1_rddata_en; +assign soc_litedramcore_dfi_p1_rddata = soc_litedramcore_slave_p1_rddata; +assign soc_litedramcore_dfi_p1_rddata_valid = soc_litedramcore_slave_p1_rddata_valid; +assign soc_litedramcore_slave_p2_address = soc_litedramcore_dfi_p2_address; +assign soc_litedramcore_slave_p2_bank = soc_litedramcore_dfi_p2_bank; +assign soc_litedramcore_slave_p2_cas_n = soc_litedramcore_dfi_p2_cas_n; +assign soc_litedramcore_slave_p2_cs_n = soc_litedramcore_dfi_p2_cs_n; +assign soc_litedramcore_slave_p2_ras_n = soc_litedramcore_dfi_p2_ras_n; +assign soc_litedramcore_slave_p2_we_n = soc_litedramcore_dfi_p2_we_n; +assign soc_litedramcore_slave_p2_cke = soc_litedramcore_dfi_p2_cke; +assign soc_litedramcore_slave_p2_odt = soc_litedramcore_dfi_p2_odt; +assign soc_litedramcore_slave_p2_reset_n = soc_litedramcore_dfi_p2_reset_n; +assign soc_litedramcore_slave_p2_act_n = soc_litedramcore_dfi_p2_act_n; +assign soc_litedramcore_slave_p2_wrdata = soc_litedramcore_dfi_p2_wrdata; +assign soc_litedramcore_slave_p2_wrdata_en = soc_litedramcore_dfi_p2_wrdata_en; +assign soc_litedramcore_slave_p2_wrdata_mask = soc_litedramcore_dfi_p2_wrdata_mask; +assign soc_litedramcore_slave_p2_rddata_en = soc_litedramcore_dfi_p2_rddata_en; +assign soc_litedramcore_dfi_p2_rddata = soc_litedramcore_slave_p2_rddata; +assign soc_litedramcore_dfi_p2_rddata_valid = soc_litedramcore_slave_p2_rddata_valid; +assign soc_litedramcore_slave_p3_address = soc_litedramcore_dfi_p3_address; +assign soc_litedramcore_slave_p3_bank = soc_litedramcore_dfi_p3_bank; +assign soc_litedramcore_slave_p3_cas_n = soc_litedramcore_dfi_p3_cas_n; +assign soc_litedramcore_slave_p3_cs_n = soc_litedramcore_dfi_p3_cs_n; +assign soc_litedramcore_slave_p3_ras_n = soc_litedramcore_dfi_p3_ras_n; +assign soc_litedramcore_slave_p3_we_n = soc_litedramcore_dfi_p3_we_n; +assign soc_litedramcore_slave_p3_cke = soc_litedramcore_dfi_p3_cke; +assign soc_litedramcore_slave_p3_odt = soc_litedramcore_dfi_p3_odt; +assign soc_litedramcore_slave_p3_reset_n = soc_litedramcore_dfi_p3_reset_n; +assign soc_litedramcore_slave_p3_act_n = soc_litedramcore_dfi_p3_act_n; +assign soc_litedramcore_slave_p3_wrdata = soc_litedramcore_dfi_p3_wrdata; +assign soc_litedramcore_slave_p3_wrdata_en = soc_litedramcore_dfi_p3_wrdata_en; +assign soc_litedramcore_slave_p3_wrdata_mask = soc_litedramcore_dfi_p3_wrdata_mask; +assign soc_litedramcore_slave_p3_rddata_en = soc_litedramcore_dfi_p3_rddata_en; +assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata; +assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid; +always @(*) begin + soc_litedramcore_csr_dfi_p0_rddata = 32'd0; + soc_litedramcore_csr_dfi_p0_rddata_valid = 1'd0; + soc_litedramcore_csr_dfi_p1_rddata = 32'd0; + soc_litedramcore_csr_dfi_p1_rddata_valid = 1'd0; + soc_litedramcore_csr_dfi_p2_rddata = 32'd0; + soc_litedramcore_csr_dfi_p2_rddata_valid = 1'd0; + soc_litedramcore_csr_dfi_p3_rddata = 32'd0; + soc_litedramcore_csr_dfi_p3_rddata_valid = 1'd0; + soc_litedramcore_ext_dfi_p0_rddata = 32'd0; + soc_litedramcore_ext_dfi_p0_rddata_valid = 1'd0; + soc_litedramcore_ext_dfi_p1_rddata = 32'd0; + soc_litedramcore_ext_dfi_p1_rddata_valid = 1'd0; + soc_litedramcore_ext_dfi_p2_rddata = 32'd0; + soc_litedramcore_ext_dfi_p2_rddata_valid = 1'd0; + soc_litedramcore_ext_dfi_p3_rddata = 32'd0; + soc_litedramcore_ext_dfi_p3_rddata_valid = 1'd0; + soc_litedramcore_master_p0_act_n = 1'd1; + soc_litedramcore_master_p0_address = 15'd0; + soc_litedramcore_master_p0_bank = 3'd0; + soc_litedramcore_master_p0_cas_n = 1'd1; + soc_litedramcore_master_p0_cke = 1'd0; + soc_litedramcore_master_p0_cs_n = 1'd1; + soc_litedramcore_master_p0_odt = 1'd0; + soc_litedramcore_master_p0_ras_n = 1'd1; + soc_litedramcore_master_p0_rddata_en = 1'd0; + soc_litedramcore_master_p0_reset_n = 1'd0; + soc_litedramcore_master_p0_we_n = 1'd1; + soc_litedramcore_master_p0_wrdata = 32'd0; + soc_litedramcore_master_p0_wrdata_en = 1'd0; + soc_litedramcore_master_p0_wrdata_mask = 4'd0; + soc_litedramcore_master_p1_act_n = 1'd1; + soc_litedramcore_master_p1_address = 15'd0; + soc_litedramcore_master_p1_bank = 3'd0; + soc_litedramcore_master_p1_cas_n = 1'd1; + soc_litedramcore_master_p1_cke = 1'd0; + soc_litedramcore_master_p1_cs_n = 1'd1; + soc_litedramcore_master_p1_odt = 1'd0; + soc_litedramcore_master_p1_ras_n = 1'd1; + soc_litedramcore_master_p1_rddata_en = 1'd0; + soc_litedramcore_master_p1_reset_n = 1'd0; + soc_litedramcore_master_p1_we_n = 1'd1; + soc_litedramcore_master_p1_wrdata = 32'd0; + soc_litedramcore_master_p1_wrdata_en = 1'd0; + soc_litedramcore_master_p1_wrdata_mask = 4'd0; + soc_litedramcore_master_p2_act_n = 1'd1; + soc_litedramcore_master_p2_address = 15'd0; + soc_litedramcore_master_p2_bank = 3'd0; + soc_litedramcore_master_p2_cas_n = 1'd1; + soc_litedramcore_master_p2_cke = 1'd0; + soc_litedramcore_master_p2_cs_n = 1'd1; + soc_litedramcore_master_p2_odt = 1'd0; + soc_litedramcore_master_p2_ras_n = 1'd1; + soc_litedramcore_master_p2_rddata_en = 1'd0; + soc_litedramcore_master_p2_reset_n = 1'd0; + soc_litedramcore_master_p2_we_n = 1'd1; + soc_litedramcore_master_p2_wrdata = 32'd0; + soc_litedramcore_master_p2_wrdata_en = 1'd0; + soc_litedramcore_master_p2_wrdata_mask = 4'd0; + soc_litedramcore_master_p3_act_n = 1'd1; + soc_litedramcore_master_p3_address = 15'd0; + soc_litedramcore_master_p3_bank = 3'd0; + soc_litedramcore_master_p3_cas_n = 1'd1; + soc_litedramcore_master_p3_cke = 1'd0; + soc_litedramcore_master_p3_cs_n = 1'd1; + soc_litedramcore_master_p3_odt = 1'd0; + soc_litedramcore_master_p3_ras_n = 1'd1; + soc_litedramcore_master_p3_rddata_en = 1'd0; + soc_litedramcore_master_p3_reset_n = 1'd0; + soc_litedramcore_master_p3_we_n = 1'd1; + soc_litedramcore_master_p3_wrdata = 32'd0; + soc_litedramcore_master_p3_wrdata_en = 1'd0; + soc_litedramcore_master_p3_wrdata_mask = 4'd0; + soc_litedramcore_slave_p0_rddata = 32'd0; + soc_litedramcore_slave_p0_rddata_valid = 1'd0; + soc_litedramcore_slave_p1_rddata = 32'd0; + soc_litedramcore_slave_p1_rddata_valid = 1'd0; + soc_litedramcore_slave_p2_rddata = 32'd0; + soc_litedramcore_slave_p2_rddata_valid = 1'd0; + soc_litedramcore_slave_p3_rddata = 32'd0; + soc_litedramcore_slave_p3_rddata_valid = 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p0_address = soc_litedramcore_ext_dfi_p0_address; + soc_litedramcore_master_p0_bank = soc_litedramcore_ext_dfi_p0_bank; + soc_litedramcore_master_p0_cas_n = soc_litedramcore_ext_dfi_p0_cas_n; + soc_litedramcore_master_p0_cs_n = soc_litedramcore_ext_dfi_p0_cs_n; + soc_litedramcore_master_p0_ras_n = soc_litedramcore_ext_dfi_p0_ras_n; + soc_litedramcore_master_p0_we_n = soc_litedramcore_ext_dfi_p0_we_n; + soc_litedramcore_master_p0_cke = soc_litedramcore_ext_dfi_p0_cke; + soc_litedramcore_master_p0_odt = soc_litedramcore_ext_dfi_p0_odt; + soc_litedramcore_master_p0_reset_n = soc_litedramcore_ext_dfi_p0_reset_n; + soc_litedramcore_master_p0_act_n = soc_litedramcore_ext_dfi_p0_act_n; + soc_litedramcore_master_p0_wrdata = soc_litedramcore_ext_dfi_p0_wrdata; + soc_litedramcore_master_p0_wrdata_en = soc_litedramcore_ext_dfi_p0_wrdata_en; + soc_litedramcore_master_p0_wrdata_mask = soc_litedramcore_ext_dfi_p0_wrdata_mask; + soc_litedramcore_master_p0_rddata_en = soc_litedramcore_ext_dfi_p0_rddata_en; + soc_litedramcore_ext_dfi_p0_rddata = soc_litedramcore_master_p0_rddata; + soc_litedramcore_ext_dfi_p0_rddata_valid = soc_litedramcore_master_p0_rddata_valid; + soc_litedramcore_master_p1_address = soc_litedramcore_ext_dfi_p1_address; + soc_litedramcore_master_p1_bank = soc_litedramcore_ext_dfi_p1_bank; + soc_litedramcore_master_p1_cas_n = soc_litedramcore_ext_dfi_p1_cas_n; + soc_litedramcore_master_p1_cs_n = soc_litedramcore_ext_dfi_p1_cs_n; + soc_litedramcore_master_p1_ras_n = soc_litedramcore_ext_dfi_p1_ras_n; + soc_litedramcore_master_p1_we_n = soc_litedramcore_ext_dfi_p1_we_n; + soc_litedramcore_master_p1_cke = soc_litedramcore_ext_dfi_p1_cke; + soc_litedramcore_master_p1_odt = soc_litedramcore_ext_dfi_p1_odt; + soc_litedramcore_master_p1_reset_n = soc_litedramcore_ext_dfi_p1_reset_n; + soc_litedramcore_master_p1_act_n = soc_litedramcore_ext_dfi_p1_act_n; + soc_litedramcore_master_p1_wrdata = soc_litedramcore_ext_dfi_p1_wrdata; + soc_litedramcore_master_p1_wrdata_en = soc_litedramcore_ext_dfi_p1_wrdata_en; + soc_litedramcore_master_p1_wrdata_mask = soc_litedramcore_ext_dfi_p1_wrdata_mask; + soc_litedramcore_master_p1_rddata_en = soc_litedramcore_ext_dfi_p1_rddata_en; + soc_litedramcore_ext_dfi_p1_rddata = soc_litedramcore_master_p1_rddata; + soc_litedramcore_ext_dfi_p1_rddata_valid = soc_litedramcore_master_p1_rddata_valid; + soc_litedramcore_master_p2_address = soc_litedramcore_ext_dfi_p2_address; + soc_litedramcore_master_p2_bank = soc_litedramcore_ext_dfi_p2_bank; + soc_litedramcore_master_p2_cas_n = soc_litedramcore_ext_dfi_p2_cas_n; + soc_litedramcore_master_p2_cs_n = soc_litedramcore_ext_dfi_p2_cs_n; + soc_litedramcore_master_p2_ras_n = soc_litedramcore_ext_dfi_p2_ras_n; + soc_litedramcore_master_p2_we_n = soc_litedramcore_ext_dfi_p2_we_n; + soc_litedramcore_master_p2_cke = soc_litedramcore_ext_dfi_p2_cke; + soc_litedramcore_master_p2_odt = soc_litedramcore_ext_dfi_p2_odt; + soc_litedramcore_master_p2_reset_n = soc_litedramcore_ext_dfi_p2_reset_n; + soc_litedramcore_master_p2_act_n = soc_litedramcore_ext_dfi_p2_act_n; + soc_litedramcore_master_p2_wrdata = soc_litedramcore_ext_dfi_p2_wrdata; + soc_litedramcore_master_p2_wrdata_en = soc_litedramcore_ext_dfi_p2_wrdata_en; + soc_litedramcore_master_p2_wrdata_mask = soc_litedramcore_ext_dfi_p2_wrdata_mask; + soc_litedramcore_master_p2_rddata_en = soc_litedramcore_ext_dfi_p2_rddata_en; + soc_litedramcore_ext_dfi_p2_rddata = soc_litedramcore_master_p2_rddata; + soc_litedramcore_ext_dfi_p2_rddata_valid = soc_litedramcore_master_p2_rddata_valid; + soc_litedramcore_master_p3_address = soc_litedramcore_ext_dfi_p3_address; + soc_litedramcore_master_p3_bank = soc_litedramcore_ext_dfi_p3_bank; + soc_litedramcore_master_p3_cas_n = soc_litedramcore_ext_dfi_p3_cas_n; + soc_litedramcore_master_p3_cs_n = soc_litedramcore_ext_dfi_p3_cs_n; + soc_litedramcore_master_p3_ras_n = soc_litedramcore_ext_dfi_p3_ras_n; + soc_litedramcore_master_p3_we_n = soc_litedramcore_ext_dfi_p3_we_n; + soc_litedramcore_master_p3_cke = soc_litedramcore_ext_dfi_p3_cke; + soc_litedramcore_master_p3_odt = soc_litedramcore_ext_dfi_p3_odt; + soc_litedramcore_master_p3_reset_n = soc_litedramcore_ext_dfi_p3_reset_n; + soc_litedramcore_master_p3_act_n = soc_litedramcore_ext_dfi_p3_act_n; + soc_litedramcore_master_p3_wrdata = soc_litedramcore_ext_dfi_p3_wrdata; + soc_litedramcore_master_p3_wrdata_en = soc_litedramcore_ext_dfi_p3_wrdata_en; + soc_litedramcore_master_p3_wrdata_mask = soc_litedramcore_ext_dfi_p3_wrdata_mask; + soc_litedramcore_master_p3_rddata_en = soc_litedramcore_ext_dfi_p3_rddata_en; + soc_litedramcore_ext_dfi_p3_rddata = soc_litedramcore_master_p3_rddata; + soc_litedramcore_ext_dfi_p3_rddata_valid = soc_litedramcore_master_p3_rddata_valid; + end else begin + soc_litedramcore_master_p0_address = soc_litedramcore_slave_p0_address; + soc_litedramcore_master_p0_bank = soc_litedramcore_slave_p0_bank; + soc_litedramcore_master_p0_cas_n = soc_litedramcore_slave_p0_cas_n; + soc_litedramcore_master_p0_cs_n = soc_litedramcore_slave_p0_cs_n; + soc_litedramcore_master_p0_ras_n = soc_litedramcore_slave_p0_ras_n; + soc_litedramcore_master_p0_we_n = soc_litedramcore_slave_p0_we_n; + soc_litedramcore_master_p0_cke = soc_litedramcore_slave_p0_cke; + soc_litedramcore_master_p0_odt = soc_litedramcore_slave_p0_odt; + soc_litedramcore_master_p0_reset_n = soc_litedramcore_slave_p0_reset_n; + soc_litedramcore_master_p0_act_n = soc_litedramcore_slave_p0_act_n; + soc_litedramcore_master_p0_wrdata = soc_litedramcore_slave_p0_wrdata; + soc_litedramcore_master_p0_wrdata_en = soc_litedramcore_slave_p0_wrdata_en; + soc_litedramcore_master_p0_wrdata_mask = soc_litedramcore_slave_p0_wrdata_mask; + soc_litedramcore_master_p0_rddata_en = soc_litedramcore_slave_p0_rddata_en; + soc_litedramcore_slave_p0_rddata = soc_litedramcore_master_p0_rddata; + soc_litedramcore_slave_p0_rddata_valid = soc_litedramcore_master_p0_rddata_valid; + soc_litedramcore_master_p1_address = soc_litedramcore_slave_p1_address; + soc_litedramcore_master_p1_bank = soc_litedramcore_slave_p1_bank; + soc_litedramcore_master_p1_cas_n = soc_litedramcore_slave_p1_cas_n; + soc_litedramcore_master_p1_cs_n = soc_litedramcore_slave_p1_cs_n; + soc_litedramcore_master_p1_ras_n = soc_litedramcore_slave_p1_ras_n; + soc_litedramcore_master_p1_we_n = soc_litedramcore_slave_p1_we_n; + soc_litedramcore_master_p1_cke = soc_litedramcore_slave_p1_cke; + soc_litedramcore_master_p1_odt = soc_litedramcore_slave_p1_odt; + soc_litedramcore_master_p1_reset_n = soc_litedramcore_slave_p1_reset_n; + soc_litedramcore_master_p1_act_n = soc_litedramcore_slave_p1_act_n; + soc_litedramcore_master_p1_wrdata = soc_litedramcore_slave_p1_wrdata; + soc_litedramcore_master_p1_wrdata_en = soc_litedramcore_slave_p1_wrdata_en; + soc_litedramcore_master_p1_wrdata_mask = soc_litedramcore_slave_p1_wrdata_mask; + soc_litedramcore_master_p1_rddata_en = soc_litedramcore_slave_p1_rddata_en; + soc_litedramcore_slave_p1_rddata = soc_litedramcore_master_p1_rddata; + soc_litedramcore_slave_p1_rddata_valid = soc_litedramcore_master_p1_rddata_valid; + soc_litedramcore_master_p2_address = soc_litedramcore_slave_p2_address; + soc_litedramcore_master_p2_bank = soc_litedramcore_slave_p2_bank; + soc_litedramcore_master_p2_cas_n = soc_litedramcore_slave_p2_cas_n; + soc_litedramcore_master_p2_cs_n = soc_litedramcore_slave_p2_cs_n; + soc_litedramcore_master_p2_ras_n = soc_litedramcore_slave_p2_ras_n; + soc_litedramcore_master_p2_we_n = soc_litedramcore_slave_p2_we_n; + soc_litedramcore_master_p2_cke = soc_litedramcore_slave_p2_cke; + soc_litedramcore_master_p2_odt = soc_litedramcore_slave_p2_odt; + soc_litedramcore_master_p2_reset_n = soc_litedramcore_slave_p2_reset_n; + soc_litedramcore_master_p2_act_n = soc_litedramcore_slave_p2_act_n; + soc_litedramcore_master_p2_wrdata = soc_litedramcore_slave_p2_wrdata; + soc_litedramcore_master_p2_wrdata_en = soc_litedramcore_slave_p2_wrdata_en; + soc_litedramcore_master_p2_wrdata_mask = soc_litedramcore_slave_p2_wrdata_mask; + soc_litedramcore_master_p2_rddata_en = soc_litedramcore_slave_p2_rddata_en; + soc_litedramcore_slave_p2_rddata = soc_litedramcore_master_p2_rddata; + soc_litedramcore_slave_p2_rddata_valid = soc_litedramcore_master_p2_rddata_valid; + soc_litedramcore_master_p3_address = soc_litedramcore_slave_p3_address; + soc_litedramcore_master_p3_bank = soc_litedramcore_slave_p3_bank; + soc_litedramcore_master_p3_cas_n = soc_litedramcore_slave_p3_cas_n; + soc_litedramcore_master_p3_cs_n = soc_litedramcore_slave_p3_cs_n; + soc_litedramcore_master_p3_ras_n = soc_litedramcore_slave_p3_ras_n; + soc_litedramcore_master_p3_we_n = soc_litedramcore_slave_p3_we_n; + soc_litedramcore_master_p3_cke = soc_litedramcore_slave_p3_cke; + soc_litedramcore_master_p3_odt = soc_litedramcore_slave_p3_odt; + soc_litedramcore_master_p3_reset_n = soc_litedramcore_slave_p3_reset_n; + soc_litedramcore_master_p3_act_n = soc_litedramcore_slave_p3_act_n; + soc_litedramcore_master_p3_wrdata = soc_litedramcore_slave_p3_wrdata; + soc_litedramcore_master_p3_wrdata_en = soc_litedramcore_slave_p3_wrdata_en; + soc_litedramcore_master_p3_wrdata_mask = soc_litedramcore_slave_p3_wrdata_mask; + soc_litedramcore_master_p3_rddata_en = soc_litedramcore_slave_p3_rddata_en; + soc_litedramcore_slave_p3_rddata = soc_litedramcore_master_p3_rddata; + soc_litedramcore_slave_p3_rddata_valid = soc_litedramcore_master_p3_rddata_valid; + if (1'd0) begin + soc_litedramcore_master_p0_cs_n = {2{soc_litedramcore_slave_p0_cs_n}}; + soc_litedramcore_master_p1_cs_n = {2{soc_litedramcore_slave_p1_cs_n}}; + soc_litedramcore_master_p2_cs_n = {2{soc_litedramcore_slave_p2_cs_n}}; + soc_litedramcore_master_p3_cs_n = {2{soc_litedramcore_slave_p3_cs_n}}; + end + end + end else begin + soc_litedramcore_master_p0_address = soc_litedramcore_csr_dfi_p0_address; + soc_litedramcore_master_p0_bank = soc_litedramcore_csr_dfi_p0_bank; + soc_litedramcore_master_p0_cas_n = soc_litedramcore_csr_dfi_p0_cas_n; + soc_litedramcore_master_p0_cs_n = soc_litedramcore_csr_dfi_p0_cs_n; + soc_litedramcore_master_p0_ras_n = soc_litedramcore_csr_dfi_p0_ras_n; + soc_litedramcore_master_p0_we_n = soc_litedramcore_csr_dfi_p0_we_n; + soc_litedramcore_master_p0_cke = soc_litedramcore_csr_dfi_p0_cke; + soc_litedramcore_master_p0_odt = soc_litedramcore_csr_dfi_p0_odt; + soc_litedramcore_master_p0_reset_n = soc_litedramcore_csr_dfi_p0_reset_n; + soc_litedramcore_master_p0_act_n = soc_litedramcore_csr_dfi_p0_act_n; + soc_litedramcore_master_p0_wrdata = soc_litedramcore_csr_dfi_p0_wrdata; + soc_litedramcore_master_p0_wrdata_en = soc_litedramcore_csr_dfi_p0_wrdata_en; + soc_litedramcore_master_p0_wrdata_mask = soc_litedramcore_csr_dfi_p0_wrdata_mask; + soc_litedramcore_master_p0_rddata_en = soc_litedramcore_csr_dfi_p0_rddata_en; + soc_litedramcore_csr_dfi_p0_rddata = soc_litedramcore_master_p0_rddata; + soc_litedramcore_csr_dfi_p0_rddata_valid = soc_litedramcore_master_p0_rddata_valid; + soc_litedramcore_master_p1_address = soc_litedramcore_csr_dfi_p1_address; + soc_litedramcore_master_p1_bank = soc_litedramcore_csr_dfi_p1_bank; + soc_litedramcore_master_p1_cas_n = soc_litedramcore_csr_dfi_p1_cas_n; + soc_litedramcore_master_p1_cs_n = soc_litedramcore_csr_dfi_p1_cs_n; + soc_litedramcore_master_p1_ras_n = soc_litedramcore_csr_dfi_p1_ras_n; + soc_litedramcore_master_p1_we_n = soc_litedramcore_csr_dfi_p1_we_n; + soc_litedramcore_master_p1_cke = soc_litedramcore_csr_dfi_p1_cke; + soc_litedramcore_master_p1_odt = soc_litedramcore_csr_dfi_p1_odt; + soc_litedramcore_master_p1_reset_n = soc_litedramcore_csr_dfi_p1_reset_n; + soc_litedramcore_master_p1_act_n = soc_litedramcore_csr_dfi_p1_act_n; + soc_litedramcore_master_p1_wrdata = soc_litedramcore_csr_dfi_p1_wrdata; + soc_litedramcore_master_p1_wrdata_en = soc_litedramcore_csr_dfi_p1_wrdata_en; + soc_litedramcore_master_p1_wrdata_mask = soc_litedramcore_csr_dfi_p1_wrdata_mask; + soc_litedramcore_master_p1_rddata_en = soc_litedramcore_csr_dfi_p1_rddata_en; + soc_litedramcore_csr_dfi_p1_rddata = soc_litedramcore_master_p1_rddata; + soc_litedramcore_csr_dfi_p1_rddata_valid = soc_litedramcore_master_p1_rddata_valid; + soc_litedramcore_master_p2_address = soc_litedramcore_csr_dfi_p2_address; + soc_litedramcore_master_p2_bank = soc_litedramcore_csr_dfi_p2_bank; + soc_litedramcore_master_p2_cas_n = soc_litedramcore_csr_dfi_p2_cas_n; + soc_litedramcore_master_p2_cs_n = soc_litedramcore_csr_dfi_p2_cs_n; + soc_litedramcore_master_p2_ras_n = soc_litedramcore_csr_dfi_p2_ras_n; + soc_litedramcore_master_p2_we_n = soc_litedramcore_csr_dfi_p2_we_n; + soc_litedramcore_master_p2_cke = soc_litedramcore_csr_dfi_p2_cke; + soc_litedramcore_master_p2_odt = soc_litedramcore_csr_dfi_p2_odt; + soc_litedramcore_master_p2_reset_n = soc_litedramcore_csr_dfi_p2_reset_n; + soc_litedramcore_master_p2_act_n = soc_litedramcore_csr_dfi_p2_act_n; + soc_litedramcore_master_p2_wrdata = soc_litedramcore_csr_dfi_p2_wrdata; + soc_litedramcore_master_p2_wrdata_en = soc_litedramcore_csr_dfi_p2_wrdata_en; + soc_litedramcore_master_p2_wrdata_mask = soc_litedramcore_csr_dfi_p2_wrdata_mask; + soc_litedramcore_master_p2_rddata_en = soc_litedramcore_csr_dfi_p2_rddata_en; + soc_litedramcore_csr_dfi_p2_rddata = soc_litedramcore_master_p2_rddata; + soc_litedramcore_csr_dfi_p2_rddata_valid = soc_litedramcore_master_p2_rddata_valid; + soc_litedramcore_master_p3_address = soc_litedramcore_csr_dfi_p3_address; + soc_litedramcore_master_p3_bank = soc_litedramcore_csr_dfi_p3_bank; + soc_litedramcore_master_p3_cas_n = soc_litedramcore_csr_dfi_p3_cas_n; + soc_litedramcore_master_p3_cs_n = soc_litedramcore_csr_dfi_p3_cs_n; + soc_litedramcore_master_p3_ras_n = soc_litedramcore_csr_dfi_p3_ras_n; + soc_litedramcore_master_p3_we_n = soc_litedramcore_csr_dfi_p3_we_n; + soc_litedramcore_master_p3_cke = soc_litedramcore_csr_dfi_p3_cke; + soc_litedramcore_master_p3_odt = soc_litedramcore_csr_dfi_p3_odt; + soc_litedramcore_master_p3_reset_n = soc_litedramcore_csr_dfi_p3_reset_n; + soc_litedramcore_master_p3_act_n = soc_litedramcore_csr_dfi_p3_act_n; + soc_litedramcore_master_p3_wrdata = soc_litedramcore_csr_dfi_p3_wrdata; + soc_litedramcore_master_p3_wrdata_en = soc_litedramcore_csr_dfi_p3_wrdata_en; + soc_litedramcore_master_p3_wrdata_mask = soc_litedramcore_csr_dfi_p3_wrdata_mask; + soc_litedramcore_master_p3_rddata_en = soc_litedramcore_csr_dfi_p3_rddata_en; + soc_litedramcore_csr_dfi_p3_rddata = soc_litedramcore_master_p3_rddata; + soc_litedramcore_csr_dfi_p3_rddata_valid = soc_litedramcore_master_p3_rddata_valid; + end +end +assign soc_litedramcore_csr_dfi_p0_cke = soc_litedramcore_cke; +assign soc_litedramcore_csr_dfi_p1_cke = soc_litedramcore_cke; +assign soc_litedramcore_csr_dfi_p2_cke = soc_litedramcore_cke; +assign soc_litedramcore_csr_dfi_p3_cke = soc_litedramcore_cke; +assign soc_litedramcore_csr_dfi_p0_odt = soc_litedramcore_odt; +assign soc_litedramcore_csr_dfi_p1_odt = soc_litedramcore_odt; +assign soc_litedramcore_csr_dfi_p2_odt = soc_litedramcore_odt; +assign soc_litedramcore_csr_dfi_p3_odt = soc_litedramcore_odt; +assign soc_litedramcore_csr_dfi_p0_reset_n = soc_litedramcore_reset_n; +assign soc_litedramcore_csr_dfi_p1_reset_n = soc_litedramcore_reset_n; +assign soc_litedramcore_csr_dfi_p2_reset_n = soc_litedramcore_reset_n; +assign soc_litedramcore_csr_dfi_p3_reset_n = soc_litedramcore_reset_n; +always @(*) begin + soc_litedramcore_csr_dfi_p0_cas_n = 1'd1; + soc_litedramcore_csr_dfi_p0_cs_n = 1'd1; + soc_litedramcore_csr_dfi_p0_ras_n = 1'd1; + soc_litedramcore_csr_dfi_p0_we_n = 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + if (soc_litedramcore_phaseinjector0_cs_top) begin + soc_litedramcore_csr_dfi_p0_cs_n = 2'd2; + end else begin + if (soc_litedramcore_phaseinjector0_cs_bottom) begin + soc_litedramcore_csr_dfi_p0_cs_n = 1'd1; + end else begin + soc_litedramcore_csr_dfi_p0_cs_n = {1{(~soc_litedramcore_phaseinjector0_cs)}}; + end + end + soc_litedramcore_csr_dfi_p0_we_n = (~soc_litedramcore_phaseinjector0_we); + soc_litedramcore_csr_dfi_p0_cas_n = (~soc_litedramcore_phaseinjector0_cas); + soc_litedramcore_csr_dfi_p0_ras_n = (~soc_litedramcore_phaseinjector0_ras); + end else begin + soc_litedramcore_csr_dfi_p0_cs_n = {1{1'd1}}; + soc_litedramcore_csr_dfi_p0_we_n = 1'd1; + soc_litedramcore_csr_dfi_p0_cas_n = 1'd1; + soc_litedramcore_csr_dfi_p0_ras_n = 1'd1; + end +end +assign soc_litedramcore_csr_dfi_p0_address = soc_litedramcore_phaseinjector0_address_storage; +assign soc_litedramcore_csr_dfi_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage; +assign soc_litedramcore_csr_dfi_p0_wrdata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_wren); +assign soc_litedramcore_csr_dfi_p0_rddata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_rden); +assign soc_litedramcore_csr_dfi_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage; +assign soc_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; +always @(*) begin + soc_litedramcore_csr_dfi_p1_cas_n = 1'd1; + soc_litedramcore_csr_dfi_p1_cs_n = 1'd1; + soc_litedramcore_csr_dfi_p1_ras_n = 1'd1; + soc_litedramcore_csr_dfi_p1_we_n = 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + if (soc_litedramcore_phaseinjector1_cs_top) begin + soc_litedramcore_csr_dfi_p1_cs_n = 2'd2; + end else begin + if (soc_litedramcore_phaseinjector1_cs_bottom) begin + soc_litedramcore_csr_dfi_p1_cs_n = 1'd1; + end else begin + soc_litedramcore_csr_dfi_p1_cs_n = {1{(~soc_litedramcore_phaseinjector1_cs)}}; + end + end + soc_litedramcore_csr_dfi_p1_we_n = (~soc_litedramcore_phaseinjector1_we); + soc_litedramcore_csr_dfi_p1_cas_n = (~soc_litedramcore_phaseinjector1_cas); + soc_litedramcore_csr_dfi_p1_ras_n = (~soc_litedramcore_phaseinjector1_ras); + end else begin + soc_litedramcore_csr_dfi_p1_cs_n = {1{1'd1}}; + soc_litedramcore_csr_dfi_p1_we_n = 1'd1; + soc_litedramcore_csr_dfi_p1_cas_n = 1'd1; + soc_litedramcore_csr_dfi_p1_ras_n = 1'd1; + end +end +assign soc_litedramcore_csr_dfi_p1_address = soc_litedramcore_phaseinjector1_address_storage; +assign soc_litedramcore_csr_dfi_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage; +assign soc_litedramcore_csr_dfi_p1_wrdata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_wren); +assign soc_litedramcore_csr_dfi_p1_rddata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_rden); +assign soc_litedramcore_csr_dfi_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage; +assign soc_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; +always @(*) begin + soc_litedramcore_csr_dfi_p2_cas_n = 1'd1; + soc_litedramcore_csr_dfi_p2_cs_n = 1'd1; + soc_litedramcore_csr_dfi_p2_ras_n = 1'd1; + soc_litedramcore_csr_dfi_p2_we_n = 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + if (soc_litedramcore_phaseinjector2_cs_top) begin + soc_litedramcore_csr_dfi_p2_cs_n = 2'd2; + end else begin + if (soc_litedramcore_phaseinjector2_cs_bottom) begin + soc_litedramcore_csr_dfi_p2_cs_n = 1'd1; + end else begin + soc_litedramcore_csr_dfi_p2_cs_n = {1{(~soc_litedramcore_phaseinjector2_cs)}}; + end + end + soc_litedramcore_csr_dfi_p2_we_n = (~soc_litedramcore_phaseinjector2_we); + soc_litedramcore_csr_dfi_p2_cas_n = (~soc_litedramcore_phaseinjector2_cas); + soc_litedramcore_csr_dfi_p2_ras_n = (~soc_litedramcore_phaseinjector2_ras); + end else begin + soc_litedramcore_csr_dfi_p2_cs_n = {1{1'd1}}; + soc_litedramcore_csr_dfi_p2_we_n = 1'd1; + soc_litedramcore_csr_dfi_p2_cas_n = 1'd1; + soc_litedramcore_csr_dfi_p2_ras_n = 1'd1; + end +end +assign soc_litedramcore_csr_dfi_p2_address = soc_litedramcore_phaseinjector2_address_storage; +assign soc_litedramcore_csr_dfi_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage; +assign soc_litedramcore_csr_dfi_p2_wrdata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_wren); +assign soc_litedramcore_csr_dfi_p2_rddata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_rden); +assign soc_litedramcore_csr_dfi_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage; +assign soc_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; +always @(*) begin + soc_litedramcore_csr_dfi_p3_cas_n = 1'd1; + soc_litedramcore_csr_dfi_p3_cs_n = 1'd1; + soc_litedramcore_csr_dfi_p3_ras_n = 1'd1; + soc_litedramcore_csr_dfi_p3_we_n = 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + if (soc_litedramcore_phaseinjector3_cs_top) begin + soc_litedramcore_csr_dfi_p3_cs_n = 2'd2; + end else begin + if (soc_litedramcore_phaseinjector3_cs_bottom) begin + soc_litedramcore_csr_dfi_p3_cs_n = 1'd1; + end else begin + soc_litedramcore_csr_dfi_p3_cs_n = {1{(~soc_litedramcore_phaseinjector3_cs)}}; + end + end + soc_litedramcore_csr_dfi_p3_we_n = (~soc_litedramcore_phaseinjector3_we); + soc_litedramcore_csr_dfi_p3_cas_n = (~soc_litedramcore_phaseinjector3_cas); + soc_litedramcore_csr_dfi_p3_ras_n = (~soc_litedramcore_phaseinjector3_ras); + end else begin + soc_litedramcore_csr_dfi_p3_cs_n = {1{1'd1}}; + soc_litedramcore_csr_dfi_p3_we_n = 1'd1; + soc_litedramcore_csr_dfi_p3_cas_n = 1'd1; + soc_litedramcore_csr_dfi_p3_ras_n = 1'd1; + end +end +assign soc_litedramcore_csr_dfi_p3_address = soc_litedramcore_phaseinjector3_address_storage; +assign soc_litedramcore_csr_dfi_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage; +assign soc_litedramcore_csr_dfi_p3_wrdata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_wren); +assign soc_litedramcore_csr_dfi_p3_rddata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_rden); +assign soc_litedramcore_csr_dfi_p3_wrdata = soc_litedramcore_phaseinjector3_wrdata_storage; +assign soc_litedramcore_csr_dfi_p3_wrdata_mask = 1'd0; +assign soc_litedramcore_bankmachine0_req_valid = soc_litedramcore_interface_bank0_valid; +assign soc_litedramcore_interface_bank0_ready = soc_litedramcore_bankmachine0_req_ready; +assign soc_litedramcore_bankmachine0_req_we = soc_litedramcore_interface_bank0_we; +assign soc_litedramcore_bankmachine0_req_addr = soc_litedramcore_interface_bank0_addr; +assign soc_litedramcore_interface_bank0_lock = soc_litedramcore_bankmachine0_req_lock; +assign soc_litedramcore_interface_bank0_wdata_ready = soc_litedramcore_bankmachine0_req_wdata_ready; +assign soc_litedramcore_interface_bank0_rdata_valid = soc_litedramcore_bankmachine0_req_rdata_valid; +assign soc_litedramcore_bankmachine1_req_valid = soc_litedramcore_interface_bank1_valid; +assign soc_litedramcore_interface_bank1_ready = soc_litedramcore_bankmachine1_req_ready; +assign soc_litedramcore_bankmachine1_req_we = soc_litedramcore_interface_bank1_we; +assign soc_litedramcore_bankmachine1_req_addr = soc_litedramcore_interface_bank1_addr; +assign soc_litedramcore_interface_bank1_lock = soc_litedramcore_bankmachine1_req_lock; +assign soc_litedramcore_interface_bank1_wdata_ready = soc_litedramcore_bankmachine1_req_wdata_ready; +assign soc_litedramcore_interface_bank1_rdata_valid = soc_litedramcore_bankmachine1_req_rdata_valid; +assign soc_litedramcore_bankmachine2_req_valid = soc_litedramcore_interface_bank2_valid; +assign soc_litedramcore_interface_bank2_ready = soc_litedramcore_bankmachine2_req_ready; +assign soc_litedramcore_bankmachine2_req_we = soc_litedramcore_interface_bank2_we; +assign soc_litedramcore_bankmachine2_req_addr = soc_litedramcore_interface_bank2_addr; +assign soc_litedramcore_interface_bank2_lock = soc_litedramcore_bankmachine2_req_lock; +assign soc_litedramcore_interface_bank2_wdata_ready = soc_litedramcore_bankmachine2_req_wdata_ready; +assign soc_litedramcore_interface_bank2_rdata_valid = soc_litedramcore_bankmachine2_req_rdata_valid; +assign soc_litedramcore_bankmachine3_req_valid = soc_litedramcore_interface_bank3_valid; +assign soc_litedramcore_interface_bank3_ready = soc_litedramcore_bankmachine3_req_ready; +assign soc_litedramcore_bankmachine3_req_we = soc_litedramcore_interface_bank3_we; +assign soc_litedramcore_bankmachine3_req_addr = soc_litedramcore_interface_bank3_addr; +assign soc_litedramcore_interface_bank3_lock = soc_litedramcore_bankmachine3_req_lock; +assign soc_litedramcore_interface_bank3_wdata_ready = soc_litedramcore_bankmachine3_req_wdata_ready; +assign soc_litedramcore_interface_bank3_rdata_valid = soc_litedramcore_bankmachine3_req_rdata_valid; +assign soc_litedramcore_bankmachine4_req_valid = soc_litedramcore_interface_bank4_valid; +assign soc_litedramcore_interface_bank4_ready = soc_litedramcore_bankmachine4_req_ready; +assign soc_litedramcore_bankmachine4_req_we = soc_litedramcore_interface_bank4_we; +assign soc_litedramcore_bankmachine4_req_addr = soc_litedramcore_interface_bank4_addr; +assign soc_litedramcore_interface_bank4_lock = soc_litedramcore_bankmachine4_req_lock; +assign soc_litedramcore_interface_bank4_wdata_ready = soc_litedramcore_bankmachine4_req_wdata_ready; +assign soc_litedramcore_interface_bank4_rdata_valid = soc_litedramcore_bankmachine4_req_rdata_valid; +assign soc_litedramcore_bankmachine5_req_valid = soc_litedramcore_interface_bank5_valid; +assign soc_litedramcore_interface_bank5_ready = soc_litedramcore_bankmachine5_req_ready; +assign soc_litedramcore_bankmachine5_req_we = soc_litedramcore_interface_bank5_we; +assign soc_litedramcore_bankmachine5_req_addr = soc_litedramcore_interface_bank5_addr; +assign soc_litedramcore_interface_bank5_lock = soc_litedramcore_bankmachine5_req_lock; +assign soc_litedramcore_interface_bank5_wdata_ready = soc_litedramcore_bankmachine5_req_wdata_ready; +assign soc_litedramcore_interface_bank5_rdata_valid = soc_litedramcore_bankmachine5_req_rdata_valid; +assign soc_litedramcore_bankmachine6_req_valid = soc_litedramcore_interface_bank6_valid; +assign soc_litedramcore_interface_bank6_ready = soc_litedramcore_bankmachine6_req_ready; +assign soc_litedramcore_bankmachine6_req_we = soc_litedramcore_interface_bank6_we; +assign soc_litedramcore_bankmachine6_req_addr = soc_litedramcore_interface_bank6_addr; +assign soc_litedramcore_interface_bank6_lock = soc_litedramcore_bankmachine6_req_lock; +assign soc_litedramcore_interface_bank6_wdata_ready = soc_litedramcore_bankmachine6_req_wdata_ready; +assign soc_litedramcore_interface_bank6_rdata_valid = soc_litedramcore_bankmachine6_req_rdata_valid; +assign soc_litedramcore_bankmachine7_req_valid = soc_litedramcore_interface_bank7_valid; +assign soc_litedramcore_interface_bank7_ready = soc_litedramcore_bankmachine7_req_ready; +assign soc_litedramcore_bankmachine7_req_we = soc_litedramcore_interface_bank7_we; +assign soc_litedramcore_bankmachine7_req_addr = soc_litedramcore_interface_bank7_addr; +assign soc_litedramcore_interface_bank7_lock = soc_litedramcore_bankmachine7_req_lock; +assign soc_litedramcore_interface_bank7_wdata_ready = soc_litedramcore_bankmachine7_req_wdata_ready; +assign soc_litedramcore_interface_bank7_rdata_valid = soc_litedramcore_bankmachine7_req_rdata_valid; +assign soc_litedramcore_timer_wait = (~soc_litedramcore_timer_done0); +assign soc_litedramcore_postponer_req_i = soc_litedramcore_timer_done0; +assign soc_litedramcore_wants_refresh = soc_litedramcore_postponer_req_o; +assign soc_litedramcore_wants_zqcs = soc_litedramcore_zqcs_timer_done0; +assign soc_litedramcore_zqcs_timer_wait = (~soc_litedramcore_zqcs_executer_done); +assign soc_litedramcore_timer_done1 = (soc_litedramcore_timer_count1 == 1'd0); +assign soc_litedramcore_timer_done0 = soc_litedramcore_timer_done1; +assign soc_litedramcore_timer_count0 = soc_litedramcore_timer_count1; +assign soc_litedramcore_sequencer_start1 = (soc_litedramcore_sequencer_start0 | (soc_litedramcore_sequencer_count != 1'd0)); +assign soc_litedramcore_sequencer_done0 = (soc_litedramcore_sequencer_done1 & (soc_litedramcore_sequencer_count == 1'd0)); +assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 == 1'd0); +assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1; +assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1; +always @(*) begin + refresher_next_state = 2'd0; + soc_litedramcore_cmd_last = 1'd0; + soc_litedramcore_cmd_valid = 1'd0; + soc_litedramcore_sequencer_start0 = 1'd0; + soc_litedramcore_zqcs_executer_start = 1'd0; + refresher_next_state = refresher_state; + case (refresher_state) + 1'd1: begin + soc_litedramcore_cmd_valid = 1'd1; + if (soc_litedramcore_cmd_ready) begin + soc_litedramcore_sequencer_start0 = 1'd1; + refresher_next_state = 2'd2; + end + end + 2'd2: begin + soc_litedramcore_cmd_valid = 1'd1; + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin + soc_litedramcore_zqcs_executer_start = 1'd1; + refresher_next_state = 2'd3; + end else begin + soc_litedramcore_cmd_valid = 1'd0; + soc_litedramcore_cmd_last = 1'd1; + refresher_next_state = 1'd0; + end + end + end + 2'd3: begin + soc_litedramcore_cmd_valid = 1'd1; + if (soc_litedramcore_zqcs_executer_done) begin + soc_litedramcore_cmd_valid = 1'd0; + soc_litedramcore_cmd_last = 1'd1; + refresher_next_state = 1'd0; + end + end + default: begin + if (1'd1) begin + if (soc_litedramcore_wants_refresh) begin + refresher_next_state = 1'd1; + end + end + end + endcase +end +assign soc_litedramcore_bankmachine0_sink_valid = soc_litedramcore_bankmachine0_req_valid; +assign soc_litedramcore_bankmachine0_req_ready = soc_litedramcore_bankmachine0_sink_ready; +assign soc_litedramcore_bankmachine0_sink_payload_we = soc_litedramcore_bankmachine0_req_we; +assign soc_litedramcore_bankmachine0_sink_payload_addr = soc_litedramcore_bankmachine0_req_addr; +assign soc_litedramcore_bankmachine0_sink_sink_valid = soc_litedramcore_bankmachine0_source_valid; +assign soc_litedramcore_bankmachine0_source_ready = soc_litedramcore_bankmachine0_sink_sink_ready; +assign soc_litedramcore_bankmachine0_sink_sink_first = soc_litedramcore_bankmachine0_source_first; +assign soc_litedramcore_bankmachine0_sink_sink_last = soc_litedramcore_bankmachine0_source_last; +assign soc_litedramcore_bankmachine0_sink_sink_payload_we = soc_litedramcore_bankmachine0_source_payload_we; +assign soc_litedramcore_bankmachine0_sink_sink_payload_addr = soc_litedramcore_bankmachine0_source_payload_addr; +assign soc_litedramcore_bankmachine0_source_source_ready = (soc_litedramcore_bankmachine0_req_wdata_ready | soc_litedramcore_bankmachine0_req_rdata_valid); +assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_source_valid | soc_litedramcore_bankmachine0_source_source_valid); +assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_source_source_payload_addr[21:7]); +assign soc_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_a = 15'd0; + if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine0_cmd_payload_a = soc_litedramcore_bankmachine0_source_source_payload_addr[21:7]; + end else begin + soc_litedramcore_bankmachine0_cmd_payload_a = ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign soc_litedramcore_bankmachine0_twtpcon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_cmd_payload_is_write); +assign soc_litedramcore_bankmachine0_trccon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); +assign soc_litedramcore_bankmachine0_trascon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); +always @(*) begin + soc_litedramcore_bankmachine0_auto_precharge = 1'd0; + if ((soc_litedramcore_bankmachine0_source_valid & soc_litedramcore_bankmachine0_source_source_valid)) begin + if ((soc_litedramcore_bankmachine0_source_payload_addr[21:7] != soc_litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin + soc_litedramcore_bankmachine0_auto_precharge = (soc_litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign soc_litedramcore_bankmachine0_syncfifo0_din = {soc_litedramcore_bankmachine0_fifo_in_last, soc_litedramcore_bankmachine0_fifo_in_first, soc_litedramcore_bankmachine0_fifo_in_payload_addr, soc_litedramcore_bankmachine0_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine0_fifo_out_last, soc_litedramcore_bankmachine0_fifo_out_first, soc_litedramcore_bankmachine0_fifo_out_payload_addr, soc_litedramcore_bankmachine0_fifo_out_payload_we} = soc_litedramcore_bankmachine0_syncfifo0_dout; +assign soc_litedramcore_bankmachine0_sink_ready = soc_litedramcore_bankmachine0_syncfifo0_writable; +assign soc_litedramcore_bankmachine0_syncfifo0_we = soc_litedramcore_bankmachine0_sink_valid; +assign soc_litedramcore_bankmachine0_fifo_in_first = soc_litedramcore_bankmachine0_sink_first; +assign soc_litedramcore_bankmachine0_fifo_in_last = soc_litedramcore_bankmachine0_sink_last; +assign soc_litedramcore_bankmachine0_fifo_in_payload_we = soc_litedramcore_bankmachine0_sink_payload_we; +assign soc_litedramcore_bankmachine0_fifo_in_payload_addr = soc_litedramcore_bankmachine0_sink_payload_addr; +assign soc_litedramcore_bankmachine0_source_valid = soc_litedramcore_bankmachine0_syncfifo0_readable; +assign soc_litedramcore_bankmachine0_source_first = soc_litedramcore_bankmachine0_fifo_out_first; +assign soc_litedramcore_bankmachine0_source_last = soc_litedramcore_bankmachine0_fifo_out_last; +assign soc_litedramcore_bankmachine0_source_payload_we = soc_litedramcore_bankmachine0_fifo_out_payload_we; +assign soc_litedramcore_bankmachine0_source_payload_addr = soc_litedramcore_bankmachine0_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine0_syncfifo0_re = soc_litedramcore_bankmachine0_source_ready; +always @(*) begin + soc_litedramcore_bankmachine0_wrport_adr = 3'd0; + if (soc_litedramcore_bankmachine0_replace) begin + soc_litedramcore_bankmachine0_wrport_adr = (soc_litedramcore_bankmachine0_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine0_wrport_adr = soc_litedramcore_bankmachine0_produce; + end +end +assign soc_litedramcore_bankmachine0_wrport_dat_w = soc_litedramcore_bankmachine0_syncfifo0_din; +assign soc_litedramcore_bankmachine0_wrport_we = (soc_litedramcore_bankmachine0_syncfifo0_we & (soc_litedramcore_bankmachine0_syncfifo0_writable | soc_litedramcore_bankmachine0_replace)); +assign soc_litedramcore_bankmachine0_do_read = (soc_litedramcore_bankmachine0_syncfifo0_readable & soc_litedramcore_bankmachine0_syncfifo0_re); +assign soc_litedramcore_bankmachine0_rdport_adr = soc_litedramcore_bankmachine0_consume; +assign soc_litedramcore_bankmachine0_syncfifo0_dout = soc_litedramcore_bankmachine0_rdport_dat_r; +assign soc_litedramcore_bankmachine0_syncfifo0_writable = (soc_litedramcore_bankmachine0_level != 4'd8); +assign soc_litedramcore_bankmachine0_syncfifo0_readable = (soc_litedramcore_bankmachine0_level != 1'd0); +assign soc_litedramcore_bankmachine0_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine0_pipe_valid_source_valid) | soc_litedramcore_bankmachine0_pipe_valid_source_ready); +assign soc_litedramcore_bankmachine0_pipe_valid_sink_valid = soc_litedramcore_bankmachine0_sink_sink_valid; +assign soc_litedramcore_bankmachine0_sink_sink_ready = soc_litedramcore_bankmachine0_pipe_valid_sink_ready; +assign soc_litedramcore_bankmachine0_pipe_valid_sink_first = soc_litedramcore_bankmachine0_sink_sink_first; +assign soc_litedramcore_bankmachine0_pipe_valid_sink_last = soc_litedramcore_bankmachine0_sink_sink_last; +assign soc_litedramcore_bankmachine0_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine0_sink_sink_payload_we; +assign soc_litedramcore_bankmachine0_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine0_sink_sink_payload_addr; +assign soc_litedramcore_bankmachine0_source_source_valid = soc_litedramcore_bankmachine0_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine0_pipe_valid_source_ready = soc_litedramcore_bankmachine0_source_source_ready; +assign soc_litedramcore_bankmachine0_source_source_first = soc_litedramcore_bankmachine0_pipe_valid_source_first; +assign soc_litedramcore_bankmachine0_source_source_last = soc_litedramcore_bankmachine0_pipe_valid_source_last; +assign soc_litedramcore_bankmachine0_source_source_payload_we = soc_litedramcore_bankmachine0_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine0_source_source_payload_addr = soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr; +always @(*) begin + bankmachine0_next_state = 3'd0; + soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine0_cmd_valid = 1'd0; + soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine0_row_close = 1'd0; + soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine0_row_open = 1'd0; + bankmachine0_next_state = bankmachine0_state; + case (bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine0_cmd_ready) begin + bankmachine0_next_state = 3'd5; + end + soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd1; + soc_litedramcore_bankmachine0_cmd_payload_we = 1'd1; + soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; + end + soc_litedramcore_bankmachine0_row_close = 1'd1; + end + 2'd2: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + bankmachine0_next_state = 3'd5; + end + soc_litedramcore_bankmachine0_row_close = 1'd1; + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1; + soc_litedramcore_bankmachine0_row_open = 1'd1; + soc_litedramcore_bankmachine0_cmd_valid = 1'd1; + soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; + if (soc_litedramcore_bankmachine0_cmd_ready) begin + bankmachine0_next_state = 3'd6; + end + soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + if (soc_litedramcore_bankmachine0_twtpcon_ready) begin + soc_litedramcore_bankmachine0_refresh_gnt = 1'd1; + end + soc_litedramcore_bankmachine0_row_close = 1'd1; + soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; + if ((~soc_litedramcore_bankmachine0_refresh_req)) begin + bankmachine0_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine0_next_state = 2'd3; + end + 3'd6: begin + bankmachine0_next_state = 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + bankmachine0_next_state = 3'd4; + end else begin + if (soc_litedramcore_bankmachine0_source_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + soc_litedramcore_bankmachine0_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine0_source_source_payload_we) begin + soc_litedramcore_bankmachine0_req_wdata_ready = soc_litedramcore_bankmachine0_cmd_ready; + soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd1; + soc_litedramcore_bankmachine0_cmd_payload_we = 1'd1; + end else begin + soc_litedramcore_bankmachine0_req_rdata_valid = soc_litedramcore_bankmachine0_cmd_ready; + soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd1; + end + soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd1; + if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin + bankmachine0_next_state = 2'd2; + end + end else begin + bankmachine0_next_state = 1'd1; + end + end else begin + bankmachine0_next_state = 2'd3; + end + end + end + end + endcase +end +assign soc_litedramcore_bankmachine1_sink_valid = soc_litedramcore_bankmachine1_req_valid; +assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_sink_ready; +assign soc_litedramcore_bankmachine1_sink_payload_we = soc_litedramcore_bankmachine1_req_we; +assign soc_litedramcore_bankmachine1_sink_payload_addr = soc_litedramcore_bankmachine1_req_addr; +assign soc_litedramcore_bankmachine1_sink_sink_valid = soc_litedramcore_bankmachine1_source_valid; +assign soc_litedramcore_bankmachine1_source_ready = soc_litedramcore_bankmachine1_sink_sink_ready; +assign soc_litedramcore_bankmachine1_sink_sink_first = soc_litedramcore_bankmachine1_source_first; +assign soc_litedramcore_bankmachine1_sink_sink_last = soc_litedramcore_bankmachine1_source_last; +assign soc_litedramcore_bankmachine1_sink_sink_payload_we = soc_litedramcore_bankmachine1_source_payload_we; +assign soc_litedramcore_bankmachine1_sink_sink_payload_addr = soc_litedramcore_bankmachine1_source_payload_addr; +assign soc_litedramcore_bankmachine1_source_source_ready = (soc_litedramcore_bankmachine1_req_wdata_ready | soc_litedramcore_bankmachine1_req_rdata_valid); +assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_source_valid | soc_litedramcore_bankmachine1_source_source_valid); +assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_source_source_payload_addr[21:7]); +assign soc_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_a = 15'd0; + if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine1_cmd_payload_a = soc_litedramcore_bankmachine1_source_source_payload_addr[21:7]; + end else begin + soc_litedramcore_bankmachine1_cmd_payload_a = ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign soc_litedramcore_bankmachine1_twtpcon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_cmd_payload_is_write); +assign soc_litedramcore_bankmachine1_trccon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); +assign soc_litedramcore_bankmachine1_trascon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); +always @(*) begin + soc_litedramcore_bankmachine1_auto_precharge = 1'd0; + if ((soc_litedramcore_bankmachine1_source_valid & soc_litedramcore_bankmachine1_source_source_valid)) begin + if ((soc_litedramcore_bankmachine1_source_payload_addr[21:7] != soc_litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin + soc_litedramcore_bankmachine1_auto_precharge = (soc_litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign soc_litedramcore_bankmachine1_syncfifo1_din = {soc_litedramcore_bankmachine1_fifo_in_last, soc_litedramcore_bankmachine1_fifo_in_first, soc_litedramcore_bankmachine1_fifo_in_payload_addr, soc_litedramcore_bankmachine1_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine1_fifo_out_last, soc_litedramcore_bankmachine1_fifo_out_first, soc_litedramcore_bankmachine1_fifo_out_payload_addr, soc_litedramcore_bankmachine1_fifo_out_payload_we} = soc_litedramcore_bankmachine1_syncfifo1_dout; +assign soc_litedramcore_bankmachine1_sink_ready = soc_litedramcore_bankmachine1_syncfifo1_writable; +assign soc_litedramcore_bankmachine1_syncfifo1_we = soc_litedramcore_bankmachine1_sink_valid; +assign soc_litedramcore_bankmachine1_fifo_in_first = soc_litedramcore_bankmachine1_sink_first; +assign soc_litedramcore_bankmachine1_fifo_in_last = soc_litedramcore_bankmachine1_sink_last; +assign soc_litedramcore_bankmachine1_fifo_in_payload_we = soc_litedramcore_bankmachine1_sink_payload_we; +assign soc_litedramcore_bankmachine1_fifo_in_payload_addr = soc_litedramcore_bankmachine1_sink_payload_addr; +assign soc_litedramcore_bankmachine1_source_valid = soc_litedramcore_bankmachine1_syncfifo1_readable; +assign soc_litedramcore_bankmachine1_source_first = soc_litedramcore_bankmachine1_fifo_out_first; +assign soc_litedramcore_bankmachine1_source_last = soc_litedramcore_bankmachine1_fifo_out_last; +assign soc_litedramcore_bankmachine1_source_payload_we = soc_litedramcore_bankmachine1_fifo_out_payload_we; +assign soc_litedramcore_bankmachine1_source_payload_addr = soc_litedramcore_bankmachine1_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine1_syncfifo1_re = soc_litedramcore_bankmachine1_source_ready; +always @(*) begin + soc_litedramcore_bankmachine1_wrport_adr = 3'd0; + if (soc_litedramcore_bankmachine1_replace) begin + soc_litedramcore_bankmachine1_wrport_adr = (soc_litedramcore_bankmachine1_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine1_wrport_adr = soc_litedramcore_bankmachine1_produce; + end +end +assign soc_litedramcore_bankmachine1_wrport_dat_w = soc_litedramcore_bankmachine1_syncfifo1_din; +assign soc_litedramcore_bankmachine1_wrport_we = (soc_litedramcore_bankmachine1_syncfifo1_we & (soc_litedramcore_bankmachine1_syncfifo1_writable | soc_litedramcore_bankmachine1_replace)); +assign soc_litedramcore_bankmachine1_do_read = (soc_litedramcore_bankmachine1_syncfifo1_readable & soc_litedramcore_bankmachine1_syncfifo1_re); +assign soc_litedramcore_bankmachine1_rdport_adr = soc_litedramcore_bankmachine1_consume; +assign soc_litedramcore_bankmachine1_syncfifo1_dout = soc_litedramcore_bankmachine1_rdport_dat_r; +assign soc_litedramcore_bankmachine1_syncfifo1_writable = (soc_litedramcore_bankmachine1_level != 4'd8); +assign soc_litedramcore_bankmachine1_syncfifo1_readable = (soc_litedramcore_bankmachine1_level != 1'd0); +assign soc_litedramcore_bankmachine1_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine1_pipe_valid_source_valid) | soc_litedramcore_bankmachine1_pipe_valid_source_ready); +assign soc_litedramcore_bankmachine1_pipe_valid_sink_valid = soc_litedramcore_bankmachine1_sink_sink_valid; +assign soc_litedramcore_bankmachine1_sink_sink_ready = soc_litedramcore_bankmachine1_pipe_valid_sink_ready; +assign soc_litedramcore_bankmachine1_pipe_valid_sink_first = soc_litedramcore_bankmachine1_sink_sink_first; +assign soc_litedramcore_bankmachine1_pipe_valid_sink_last = soc_litedramcore_bankmachine1_sink_sink_last; +assign soc_litedramcore_bankmachine1_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine1_sink_sink_payload_we; +assign soc_litedramcore_bankmachine1_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine1_sink_sink_payload_addr; +assign soc_litedramcore_bankmachine1_source_source_valid = soc_litedramcore_bankmachine1_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine1_pipe_valid_source_ready = soc_litedramcore_bankmachine1_source_source_ready; +assign soc_litedramcore_bankmachine1_source_source_first = soc_litedramcore_bankmachine1_pipe_valid_source_first; +assign soc_litedramcore_bankmachine1_source_source_last = soc_litedramcore_bankmachine1_pipe_valid_source_last; +assign soc_litedramcore_bankmachine1_source_source_payload_we = soc_litedramcore_bankmachine1_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine1_source_source_payload_addr = soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr; +always @(*) begin + bankmachine1_next_state = 3'd0; + soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine1_cmd_valid = 1'd0; + soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine1_row_close = 1'd0; + soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine1_row_open = 1'd0; + bankmachine1_next_state = bankmachine1_state; + case (bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine1_cmd_ready) begin + bankmachine1_next_state = 3'd5; + end + soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd1; + soc_litedramcore_bankmachine1_cmd_payload_we = 1'd1; + soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + end + soc_litedramcore_bankmachine1_row_close = 1'd1; + end + 2'd2: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + bankmachine1_next_state = 3'd5; + end + soc_litedramcore_bankmachine1_row_close = 1'd1; + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1; + soc_litedramcore_bankmachine1_row_open = 1'd1; + soc_litedramcore_bankmachine1_cmd_valid = 1'd1; + soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + if (soc_litedramcore_bankmachine1_cmd_ready) begin + bankmachine1_next_state = 3'd6; + end + soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + if (soc_litedramcore_bankmachine1_twtpcon_ready) begin + soc_litedramcore_bankmachine1_refresh_gnt = 1'd1; + end + soc_litedramcore_bankmachine1_row_close = 1'd1; + soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + if ((~soc_litedramcore_bankmachine1_refresh_req)) begin + bankmachine1_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine1_next_state = 2'd3; + end + 3'd6: begin + bankmachine1_next_state = 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + bankmachine1_next_state = 3'd4; + end else begin + if (soc_litedramcore_bankmachine1_source_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + soc_litedramcore_bankmachine1_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine1_source_source_payload_we) begin + soc_litedramcore_bankmachine1_req_wdata_ready = soc_litedramcore_bankmachine1_cmd_ready; + soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd1; + soc_litedramcore_bankmachine1_cmd_payload_we = 1'd1; + end else begin + soc_litedramcore_bankmachine1_req_rdata_valid = soc_litedramcore_bankmachine1_cmd_ready; + soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd1; + end + soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd1; + if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin + bankmachine1_next_state = 2'd2; + end + end else begin + bankmachine1_next_state = 1'd1; + end + end else begin + bankmachine1_next_state = 2'd3; + end + end + end + end + endcase +end +assign soc_litedramcore_bankmachine2_sink_valid = soc_litedramcore_bankmachine2_req_valid; +assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_sink_ready; +assign soc_litedramcore_bankmachine2_sink_payload_we = soc_litedramcore_bankmachine2_req_we; +assign soc_litedramcore_bankmachine2_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr; +assign soc_litedramcore_bankmachine2_sink_sink_valid = soc_litedramcore_bankmachine2_source_valid; +assign soc_litedramcore_bankmachine2_source_ready = soc_litedramcore_bankmachine2_sink_sink_ready; +assign soc_litedramcore_bankmachine2_sink_sink_first = soc_litedramcore_bankmachine2_source_first; +assign soc_litedramcore_bankmachine2_sink_sink_last = soc_litedramcore_bankmachine2_source_last; +assign soc_litedramcore_bankmachine2_sink_sink_payload_we = soc_litedramcore_bankmachine2_source_payload_we; +assign soc_litedramcore_bankmachine2_sink_sink_payload_addr = soc_litedramcore_bankmachine2_source_payload_addr; +assign soc_litedramcore_bankmachine2_source_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid); +assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_source_valid | soc_litedramcore_bankmachine2_source_source_valid); +assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_source_source_payload_addr[21:7]); +assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_a = 15'd0; + if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine2_cmd_payload_a = soc_litedramcore_bankmachine2_source_source_payload_addr[21:7]; + end else begin + soc_litedramcore_bankmachine2_cmd_payload_a = ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write); +assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); +assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); +always @(*) begin + soc_litedramcore_bankmachine2_auto_precharge = 1'd0; + if ((soc_litedramcore_bankmachine2_source_valid & soc_litedramcore_bankmachine2_source_source_valid)) begin + if ((soc_litedramcore_bankmachine2_source_payload_addr[21:7] != soc_litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin + soc_litedramcore_bankmachine2_auto_precharge = (soc_litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign soc_litedramcore_bankmachine2_syncfifo2_din = {soc_litedramcore_bankmachine2_fifo_in_last, soc_litedramcore_bankmachine2_fifo_in_first, soc_litedramcore_bankmachine2_fifo_in_payload_addr, soc_litedramcore_bankmachine2_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine2_fifo_out_last, soc_litedramcore_bankmachine2_fifo_out_first, soc_litedramcore_bankmachine2_fifo_out_payload_addr, soc_litedramcore_bankmachine2_fifo_out_payload_we} = soc_litedramcore_bankmachine2_syncfifo2_dout; +assign soc_litedramcore_bankmachine2_sink_ready = soc_litedramcore_bankmachine2_syncfifo2_writable; +assign soc_litedramcore_bankmachine2_syncfifo2_we = soc_litedramcore_bankmachine2_sink_valid; +assign soc_litedramcore_bankmachine2_fifo_in_first = soc_litedramcore_bankmachine2_sink_first; +assign soc_litedramcore_bankmachine2_fifo_in_last = soc_litedramcore_bankmachine2_sink_last; +assign soc_litedramcore_bankmachine2_fifo_in_payload_we = soc_litedramcore_bankmachine2_sink_payload_we; +assign soc_litedramcore_bankmachine2_fifo_in_payload_addr = soc_litedramcore_bankmachine2_sink_payload_addr; +assign soc_litedramcore_bankmachine2_source_valid = soc_litedramcore_bankmachine2_syncfifo2_readable; +assign soc_litedramcore_bankmachine2_source_first = soc_litedramcore_bankmachine2_fifo_out_first; +assign soc_litedramcore_bankmachine2_source_last = soc_litedramcore_bankmachine2_fifo_out_last; +assign soc_litedramcore_bankmachine2_source_payload_we = soc_litedramcore_bankmachine2_fifo_out_payload_we; +assign soc_litedramcore_bankmachine2_source_payload_addr = soc_litedramcore_bankmachine2_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine2_syncfifo2_re = soc_litedramcore_bankmachine2_source_ready; +always @(*) begin + soc_litedramcore_bankmachine2_wrport_adr = 3'd0; + if (soc_litedramcore_bankmachine2_replace) begin + soc_litedramcore_bankmachine2_wrport_adr = (soc_litedramcore_bankmachine2_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine2_wrport_adr = soc_litedramcore_bankmachine2_produce; + end +end +assign soc_litedramcore_bankmachine2_wrport_dat_w = soc_litedramcore_bankmachine2_syncfifo2_din; +assign soc_litedramcore_bankmachine2_wrport_we = (soc_litedramcore_bankmachine2_syncfifo2_we & (soc_litedramcore_bankmachine2_syncfifo2_writable | soc_litedramcore_bankmachine2_replace)); +assign soc_litedramcore_bankmachine2_do_read = (soc_litedramcore_bankmachine2_syncfifo2_readable & soc_litedramcore_bankmachine2_syncfifo2_re); +assign soc_litedramcore_bankmachine2_rdport_adr = soc_litedramcore_bankmachine2_consume; +assign soc_litedramcore_bankmachine2_syncfifo2_dout = soc_litedramcore_bankmachine2_rdport_dat_r; +assign soc_litedramcore_bankmachine2_syncfifo2_writable = (soc_litedramcore_bankmachine2_level != 4'd8); +assign soc_litedramcore_bankmachine2_syncfifo2_readable = (soc_litedramcore_bankmachine2_level != 1'd0); +assign soc_litedramcore_bankmachine2_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine2_pipe_valid_source_valid) | soc_litedramcore_bankmachine2_pipe_valid_source_ready); +assign soc_litedramcore_bankmachine2_pipe_valid_sink_valid = soc_litedramcore_bankmachine2_sink_sink_valid; +assign soc_litedramcore_bankmachine2_sink_sink_ready = soc_litedramcore_bankmachine2_pipe_valid_sink_ready; +assign soc_litedramcore_bankmachine2_pipe_valid_sink_first = soc_litedramcore_bankmachine2_sink_sink_first; +assign soc_litedramcore_bankmachine2_pipe_valid_sink_last = soc_litedramcore_bankmachine2_sink_sink_last; +assign soc_litedramcore_bankmachine2_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine2_sink_sink_payload_we; +assign soc_litedramcore_bankmachine2_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine2_sink_sink_payload_addr; +assign soc_litedramcore_bankmachine2_source_source_valid = soc_litedramcore_bankmachine2_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine2_pipe_valid_source_ready = soc_litedramcore_bankmachine2_source_source_ready; +assign soc_litedramcore_bankmachine2_source_source_first = soc_litedramcore_bankmachine2_pipe_valid_source_first; +assign soc_litedramcore_bankmachine2_source_source_last = soc_litedramcore_bankmachine2_pipe_valid_source_last; +assign soc_litedramcore_bankmachine2_source_source_payload_we = soc_litedramcore_bankmachine2_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine2_source_source_payload_addr = soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr; +always @(*) begin + bankmachine2_next_state = 3'd0; + soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine2_cmd_valid = 1'd0; + soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine2_row_close = 1'd0; + soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine2_row_open = 1'd0; + bankmachine2_next_state = bankmachine2_state; + case (bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine2_cmd_ready) begin + bankmachine2_next_state = 3'd5; + end + soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd1; + soc_litedramcore_bankmachine2_cmd_payload_we = 1'd1; + soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; + end + soc_litedramcore_bankmachine2_row_close = 1'd1; + end + 2'd2: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + bankmachine2_next_state = 3'd5; + end + soc_litedramcore_bankmachine2_row_close = 1'd1; + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1; + soc_litedramcore_bankmachine2_row_open = 1'd1; + soc_litedramcore_bankmachine2_cmd_valid = 1'd1; + soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; + if (soc_litedramcore_bankmachine2_cmd_ready) begin + bankmachine2_next_state = 3'd6; + end + soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + if (soc_litedramcore_bankmachine2_twtpcon_ready) begin + soc_litedramcore_bankmachine2_refresh_gnt = 1'd1; + end + soc_litedramcore_bankmachine2_row_close = 1'd1; + soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; + if ((~soc_litedramcore_bankmachine2_refresh_req)) begin + bankmachine2_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine2_next_state = 2'd3; + end + 3'd6: begin + bankmachine2_next_state = 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + bankmachine2_next_state = 3'd4; + end else begin + if (soc_litedramcore_bankmachine2_source_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + soc_litedramcore_bankmachine2_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine2_source_source_payload_we) begin + soc_litedramcore_bankmachine2_req_wdata_ready = soc_litedramcore_bankmachine2_cmd_ready; + soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd1; + soc_litedramcore_bankmachine2_cmd_payload_we = 1'd1; + end else begin + soc_litedramcore_bankmachine2_req_rdata_valid = soc_litedramcore_bankmachine2_cmd_ready; + soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd1; + end + soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd1; + if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin + bankmachine2_next_state = 2'd2; + end + end else begin + bankmachine2_next_state = 1'd1; + end + end else begin + bankmachine2_next_state = 2'd3; + end + end + end + end + endcase +end +assign soc_litedramcore_bankmachine3_sink_valid = soc_litedramcore_bankmachine3_req_valid; +assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_sink_ready; +assign soc_litedramcore_bankmachine3_sink_payload_we = soc_litedramcore_bankmachine3_req_we; +assign soc_litedramcore_bankmachine3_sink_payload_addr = soc_litedramcore_bankmachine3_req_addr; +assign soc_litedramcore_bankmachine3_sink_sink_valid = soc_litedramcore_bankmachine3_source_valid; +assign soc_litedramcore_bankmachine3_source_ready = soc_litedramcore_bankmachine3_sink_sink_ready; +assign soc_litedramcore_bankmachine3_sink_sink_first = soc_litedramcore_bankmachine3_source_first; +assign soc_litedramcore_bankmachine3_sink_sink_last = soc_litedramcore_bankmachine3_source_last; +assign soc_litedramcore_bankmachine3_sink_sink_payload_we = soc_litedramcore_bankmachine3_source_payload_we; +assign soc_litedramcore_bankmachine3_sink_sink_payload_addr = soc_litedramcore_bankmachine3_source_payload_addr; +assign soc_litedramcore_bankmachine3_source_source_ready = (soc_litedramcore_bankmachine3_req_wdata_ready | soc_litedramcore_bankmachine3_req_rdata_valid); +assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_source_valid | soc_litedramcore_bankmachine3_source_source_valid); +assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_source_source_payload_addr[21:7]); +assign soc_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_a = 15'd0; + if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine3_cmd_payload_a = soc_litedramcore_bankmachine3_source_source_payload_addr[21:7]; + end else begin + soc_litedramcore_bankmachine3_cmd_payload_a = ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign soc_litedramcore_bankmachine3_twtpcon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_cmd_payload_is_write); +assign soc_litedramcore_bankmachine3_trccon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); +assign soc_litedramcore_bankmachine3_trascon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); +always @(*) begin + soc_litedramcore_bankmachine3_auto_precharge = 1'd0; + if ((soc_litedramcore_bankmachine3_source_valid & soc_litedramcore_bankmachine3_source_source_valid)) begin + if ((soc_litedramcore_bankmachine3_source_payload_addr[21:7] != soc_litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin + soc_litedramcore_bankmachine3_auto_precharge = (soc_litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign soc_litedramcore_bankmachine3_syncfifo3_din = {soc_litedramcore_bankmachine3_fifo_in_last, soc_litedramcore_bankmachine3_fifo_in_first, soc_litedramcore_bankmachine3_fifo_in_payload_addr, soc_litedramcore_bankmachine3_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine3_fifo_out_last, soc_litedramcore_bankmachine3_fifo_out_first, soc_litedramcore_bankmachine3_fifo_out_payload_addr, soc_litedramcore_bankmachine3_fifo_out_payload_we} = soc_litedramcore_bankmachine3_syncfifo3_dout; +assign soc_litedramcore_bankmachine3_sink_ready = soc_litedramcore_bankmachine3_syncfifo3_writable; +assign soc_litedramcore_bankmachine3_syncfifo3_we = soc_litedramcore_bankmachine3_sink_valid; +assign soc_litedramcore_bankmachine3_fifo_in_first = soc_litedramcore_bankmachine3_sink_first; +assign soc_litedramcore_bankmachine3_fifo_in_last = soc_litedramcore_bankmachine3_sink_last; +assign soc_litedramcore_bankmachine3_fifo_in_payload_we = soc_litedramcore_bankmachine3_sink_payload_we; +assign soc_litedramcore_bankmachine3_fifo_in_payload_addr = soc_litedramcore_bankmachine3_sink_payload_addr; +assign soc_litedramcore_bankmachine3_source_valid = soc_litedramcore_bankmachine3_syncfifo3_readable; +assign soc_litedramcore_bankmachine3_source_first = soc_litedramcore_bankmachine3_fifo_out_first; +assign soc_litedramcore_bankmachine3_source_last = soc_litedramcore_bankmachine3_fifo_out_last; +assign soc_litedramcore_bankmachine3_source_payload_we = soc_litedramcore_bankmachine3_fifo_out_payload_we; +assign soc_litedramcore_bankmachine3_source_payload_addr = soc_litedramcore_bankmachine3_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine3_syncfifo3_re = soc_litedramcore_bankmachine3_source_ready; +always @(*) begin + soc_litedramcore_bankmachine3_wrport_adr = 3'd0; + if (soc_litedramcore_bankmachine3_replace) begin + soc_litedramcore_bankmachine3_wrport_adr = (soc_litedramcore_bankmachine3_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine3_wrport_adr = soc_litedramcore_bankmachine3_produce; + end +end +assign soc_litedramcore_bankmachine3_wrport_dat_w = soc_litedramcore_bankmachine3_syncfifo3_din; +assign soc_litedramcore_bankmachine3_wrport_we = (soc_litedramcore_bankmachine3_syncfifo3_we & (soc_litedramcore_bankmachine3_syncfifo3_writable | soc_litedramcore_bankmachine3_replace)); +assign soc_litedramcore_bankmachine3_do_read = (soc_litedramcore_bankmachine3_syncfifo3_readable & soc_litedramcore_bankmachine3_syncfifo3_re); +assign soc_litedramcore_bankmachine3_rdport_adr = soc_litedramcore_bankmachine3_consume; +assign soc_litedramcore_bankmachine3_syncfifo3_dout = soc_litedramcore_bankmachine3_rdport_dat_r; +assign soc_litedramcore_bankmachine3_syncfifo3_writable = (soc_litedramcore_bankmachine3_level != 4'd8); +assign soc_litedramcore_bankmachine3_syncfifo3_readable = (soc_litedramcore_bankmachine3_level != 1'd0); +assign soc_litedramcore_bankmachine3_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine3_pipe_valid_source_valid) | soc_litedramcore_bankmachine3_pipe_valid_source_ready); +assign soc_litedramcore_bankmachine3_pipe_valid_sink_valid = soc_litedramcore_bankmachine3_sink_sink_valid; +assign soc_litedramcore_bankmachine3_sink_sink_ready = soc_litedramcore_bankmachine3_pipe_valid_sink_ready; +assign soc_litedramcore_bankmachine3_pipe_valid_sink_first = soc_litedramcore_bankmachine3_sink_sink_first; +assign soc_litedramcore_bankmachine3_pipe_valid_sink_last = soc_litedramcore_bankmachine3_sink_sink_last; +assign soc_litedramcore_bankmachine3_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine3_sink_sink_payload_we; +assign soc_litedramcore_bankmachine3_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine3_sink_sink_payload_addr; +assign soc_litedramcore_bankmachine3_source_source_valid = soc_litedramcore_bankmachine3_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine3_pipe_valid_source_ready = soc_litedramcore_bankmachine3_source_source_ready; +assign soc_litedramcore_bankmachine3_source_source_first = soc_litedramcore_bankmachine3_pipe_valid_source_first; +assign soc_litedramcore_bankmachine3_source_source_last = soc_litedramcore_bankmachine3_pipe_valid_source_last; +assign soc_litedramcore_bankmachine3_source_source_payload_we = soc_litedramcore_bankmachine3_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine3_source_source_payload_addr = soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr; +always @(*) begin + bankmachine3_next_state = 3'd0; + soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine3_cmd_valid = 1'd0; + soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine3_row_close = 1'd0; + soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine3_row_open = 1'd0; + bankmachine3_next_state = bankmachine3_state; + case (bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine3_cmd_ready) begin + bankmachine3_next_state = 3'd5; + end + soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd1; + soc_litedramcore_bankmachine3_cmd_payload_we = 1'd1; + soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + end + soc_litedramcore_bankmachine3_row_close = 1'd1; + end + 2'd2: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + bankmachine3_next_state = 3'd5; + end + soc_litedramcore_bankmachine3_row_close = 1'd1; + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd1; + soc_litedramcore_bankmachine3_row_open = 1'd1; + soc_litedramcore_bankmachine3_cmd_valid = 1'd1; + soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + if (soc_litedramcore_bankmachine3_cmd_ready) begin + bankmachine3_next_state = 3'd6; + end + soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + if (soc_litedramcore_bankmachine3_twtpcon_ready) begin + soc_litedramcore_bankmachine3_refresh_gnt = 1'd1; + end + soc_litedramcore_bankmachine3_row_close = 1'd1; + soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + if ((~soc_litedramcore_bankmachine3_refresh_req)) begin + bankmachine3_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine3_next_state = 2'd3; + end + 3'd6: begin + bankmachine3_next_state = 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + bankmachine3_next_state = 3'd4; + end else begin + if (soc_litedramcore_bankmachine3_source_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + soc_litedramcore_bankmachine3_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine3_source_source_payload_we) begin + soc_litedramcore_bankmachine3_req_wdata_ready = soc_litedramcore_bankmachine3_cmd_ready; + soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd1; + soc_litedramcore_bankmachine3_cmd_payload_we = 1'd1; + end else begin + soc_litedramcore_bankmachine3_req_rdata_valid = soc_litedramcore_bankmachine3_cmd_ready; + soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd1; + end + soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd1; + if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin + bankmachine3_next_state = 2'd2; + end + end else begin + bankmachine3_next_state = 1'd1; + end + end else begin + bankmachine3_next_state = 2'd3; + end + end + end + end + endcase +end +assign soc_litedramcore_bankmachine4_sink_valid = soc_litedramcore_bankmachine4_req_valid; +assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_sink_ready; +assign soc_litedramcore_bankmachine4_sink_payload_we = soc_litedramcore_bankmachine4_req_we; +assign soc_litedramcore_bankmachine4_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr; +assign soc_litedramcore_bankmachine4_sink_sink_valid = soc_litedramcore_bankmachine4_source_valid; +assign soc_litedramcore_bankmachine4_source_ready = soc_litedramcore_bankmachine4_sink_sink_ready; +assign soc_litedramcore_bankmachine4_sink_sink_first = soc_litedramcore_bankmachine4_source_first; +assign soc_litedramcore_bankmachine4_sink_sink_last = soc_litedramcore_bankmachine4_source_last; +assign soc_litedramcore_bankmachine4_sink_sink_payload_we = soc_litedramcore_bankmachine4_source_payload_we; +assign soc_litedramcore_bankmachine4_sink_sink_payload_addr = soc_litedramcore_bankmachine4_source_payload_addr; +assign soc_litedramcore_bankmachine4_source_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid); +assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_source_valid | soc_litedramcore_bankmachine4_source_source_valid); +assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_source_source_payload_addr[21:7]); +assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_a = 15'd0; + if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine4_cmd_payload_a = soc_litedramcore_bankmachine4_source_source_payload_addr[21:7]; + end else begin + soc_litedramcore_bankmachine4_cmd_payload_a = ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign soc_litedramcore_bankmachine4_twtpcon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_cmd_payload_is_write); +assign soc_litedramcore_bankmachine4_trccon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); +assign soc_litedramcore_bankmachine4_trascon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); +always @(*) begin + soc_litedramcore_bankmachine4_auto_precharge = 1'd0; + if ((soc_litedramcore_bankmachine4_source_valid & soc_litedramcore_bankmachine4_source_source_valid)) begin + if ((soc_litedramcore_bankmachine4_source_payload_addr[21:7] != soc_litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin + soc_litedramcore_bankmachine4_auto_precharge = (soc_litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign soc_litedramcore_bankmachine4_syncfifo4_din = {soc_litedramcore_bankmachine4_fifo_in_last, soc_litedramcore_bankmachine4_fifo_in_first, soc_litedramcore_bankmachine4_fifo_in_payload_addr, soc_litedramcore_bankmachine4_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine4_fifo_out_last, soc_litedramcore_bankmachine4_fifo_out_first, soc_litedramcore_bankmachine4_fifo_out_payload_addr, soc_litedramcore_bankmachine4_fifo_out_payload_we} = soc_litedramcore_bankmachine4_syncfifo4_dout; +assign soc_litedramcore_bankmachine4_sink_ready = soc_litedramcore_bankmachine4_syncfifo4_writable; +assign soc_litedramcore_bankmachine4_syncfifo4_we = soc_litedramcore_bankmachine4_sink_valid; +assign soc_litedramcore_bankmachine4_fifo_in_first = soc_litedramcore_bankmachine4_sink_first; +assign soc_litedramcore_bankmachine4_fifo_in_last = soc_litedramcore_bankmachine4_sink_last; +assign soc_litedramcore_bankmachine4_fifo_in_payload_we = soc_litedramcore_bankmachine4_sink_payload_we; +assign soc_litedramcore_bankmachine4_fifo_in_payload_addr = soc_litedramcore_bankmachine4_sink_payload_addr; +assign soc_litedramcore_bankmachine4_source_valid = soc_litedramcore_bankmachine4_syncfifo4_readable; +assign soc_litedramcore_bankmachine4_source_first = soc_litedramcore_bankmachine4_fifo_out_first; +assign soc_litedramcore_bankmachine4_source_last = soc_litedramcore_bankmachine4_fifo_out_last; +assign soc_litedramcore_bankmachine4_source_payload_we = soc_litedramcore_bankmachine4_fifo_out_payload_we; +assign soc_litedramcore_bankmachine4_source_payload_addr = soc_litedramcore_bankmachine4_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine4_syncfifo4_re = soc_litedramcore_bankmachine4_source_ready; +always @(*) begin + soc_litedramcore_bankmachine4_wrport_adr = 3'd0; + if (soc_litedramcore_bankmachine4_replace) begin + soc_litedramcore_bankmachine4_wrport_adr = (soc_litedramcore_bankmachine4_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine4_wrport_adr = soc_litedramcore_bankmachine4_produce; + end +end +assign soc_litedramcore_bankmachine4_wrport_dat_w = soc_litedramcore_bankmachine4_syncfifo4_din; +assign soc_litedramcore_bankmachine4_wrport_we = (soc_litedramcore_bankmachine4_syncfifo4_we & (soc_litedramcore_bankmachine4_syncfifo4_writable | soc_litedramcore_bankmachine4_replace)); +assign soc_litedramcore_bankmachine4_do_read = (soc_litedramcore_bankmachine4_syncfifo4_readable & soc_litedramcore_bankmachine4_syncfifo4_re); +assign soc_litedramcore_bankmachine4_rdport_adr = soc_litedramcore_bankmachine4_consume; +assign soc_litedramcore_bankmachine4_syncfifo4_dout = soc_litedramcore_bankmachine4_rdport_dat_r; +assign soc_litedramcore_bankmachine4_syncfifo4_writable = (soc_litedramcore_bankmachine4_level != 4'd8); +assign soc_litedramcore_bankmachine4_syncfifo4_readable = (soc_litedramcore_bankmachine4_level != 1'd0); +assign soc_litedramcore_bankmachine4_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine4_pipe_valid_source_valid) | soc_litedramcore_bankmachine4_pipe_valid_source_ready); +assign soc_litedramcore_bankmachine4_pipe_valid_sink_valid = soc_litedramcore_bankmachine4_sink_sink_valid; +assign soc_litedramcore_bankmachine4_sink_sink_ready = soc_litedramcore_bankmachine4_pipe_valid_sink_ready; +assign soc_litedramcore_bankmachine4_pipe_valid_sink_first = soc_litedramcore_bankmachine4_sink_sink_first; +assign soc_litedramcore_bankmachine4_pipe_valid_sink_last = soc_litedramcore_bankmachine4_sink_sink_last; +assign soc_litedramcore_bankmachine4_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine4_sink_sink_payload_we; +assign soc_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine4_sink_sink_payload_addr; +assign soc_litedramcore_bankmachine4_source_source_valid = soc_litedramcore_bankmachine4_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine4_pipe_valid_source_ready = soc_litedramcore_bankmachine4_source_source_ready; +assign soc_litedramcore_bankmachine4_source_source_first = soc_litedramcore_bankmachine4_pipe_valid_source_first; +assign soc_litedramcore_bankmachine4_source_source_last = soc_litedramcore_bankmachine4_pipe_valid_source_last; +assign soc_litedramcore_bankmachine4_source_source_payload_we = soc_litedramcore_bankmachine4_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine4_source_source_payload_addr = soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr; +always @(*) begin + bankmachine4_next_state = 3'd0; + soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine4_cmd_valid = 1'd0; + soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine4_row_close = 1'd0; + soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine4_row_open = 1'd0; + bankmachine4_next_state = bankmachine4_state; + case (bankmachine4_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine4_cmd_ready) begin + bankmachine4_next_state = 3'd5; + end + soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd1; + soc_litedramcore_bankmachine4_cmd_payload_we = 1'd1; + soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + end + soc_litedramcore_bankmachine4_row_close = 1'd1; + end + 2'd2: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + bankmachine4_next_state = 3'd5; + end + soc_litedramcore_bankmachine4_row_close = 1'd1; + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd1; + soc_litedramcore_bankmachine4_row_open = 1'd1; + soc_litedramcore_bankmachine4_cmd_valid = 1'd1; + soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + if (soc_litedramcore_bankmachine4_cmd_ready) begin + bankmachine4_next_state = 3'd6; + end + soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + if (soc_litedramcore_bankmachine4_twtpcon_ready) begin + soc_litedramcore_bankmachine4_refresh_gnt = 1'd1; + end + soc_litedramcore_bankmachine4_row_close = 1'd1; + soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + if ((~soc_litedramcore_bankmachine4_refresh_req)) begin + bankmachine4_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine4_next_state = 2'd3; + end + 3'd6: begin + bankmachine4_next_state = 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + bankmachine4_next_state = 3'd4; + end else begin + if (soc_litedramcore_bankmachine4_source_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + soc_litedramcore_bankmachine4_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine4_source_source_payload_we) begin + soc_litedramcore_bankmachine4_req_wdata_ready = soc_litedramcore_bankmachine4_cmd_ready; + soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd1; + soc_litedramcore_bankmachine4_cmd_payload_we = 1'd1; + end else begin + soc_litedramcore_bankmachine4_req_rdata_valid = soc_litedramcore_bankmachine4_cmd_ready; + soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd1; + end + soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd1; + if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin + bankmachine4_next_state = 2'd2; + end + end else begin + bankmachine4_next_state = 1'd1; + end + end else begin + bankmachine4_next_state = 2'd3; + end + end + end + end + endcase +end +assign soc_litedramcore_bankmachine5_sink_valid = soc_litedramcore_bankmachine5_req_valid; +assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_sink_ready; +assign soc_litedramcore_bankmachine5_sink_payload_we = soc_litedramcore_bankmachine5_req_we; +assign soc_litedramcore_bankmachine5_sink_payload_addr = soc_litedramcore_bankmachine5_req_addr; +assign soc_litedramcore_bankmachine5_sink_sink_valid = soc_litedramcore_bankmachine5_source_valid; +assign soc_litedramcore_bankmachine5_source_ready = soc_litedramcore_bankmachine5_sink_sink_ready; +assign soc_litedramcore_bankmachine5_sink_sink_first = soc_litedramcore_bankmachine5_source_first; +assign soc_litedramcore_bankmachine5_sink_sink_last = soc_litedramcore_bankmachine5_source_last; +assign soc_litedramcore_bankmachine5_sink_sink_payload_we = soc_litedramcore_bankmachine5_source_payload_we; +assign soc_litedramcore_bankmachine5_sink_sink_payload_addr = soc_litedramcore_bankmachine5_source_payload_addr; +assign soc_litedramcore_bankmachine5_source_source_ready = (soc_litedramcore_bankmachine5_req_wdata_ready | soc_litedramcore_bankmachine5_req_rdata_valid); +assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_source_valid | soc_litedramcore_bankmachine5_source_source_valid); +assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_source_source_payload_addr[21:7]); +assign soc_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_a = 15'd0; + if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine5_cmd_payload_a = soc_litedramcore_bankmachine5_source_source_payload_addr[21:7]; + end else begin + soc_litedramcore_bankmachine5_cmd_payload_a = ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign soc_litedramcore_bankmachine5_twtpcon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_cmd_payload_is_write); +assign soc_litedramcore_bankmachine5_trccon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); +assign soc_litedramcore_bankmachine5_trascon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); +always @(*) begin + soc_litedramcore_bankmachine5_auto_precharge = 1'd0; + if ((soc_litedramcore_bankmachine5_source_valid & soc_litedramcore_bankmachine5_source_source_valid)) begin + if ((soc_litedramcore_bankmachine5_source_payload_addr[21:7] != soc_litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin + soc_litedramcore_bankmachine5_auto_precharge = (soc_litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign soc_litedramcore_bankmachine5_syncfifo5_din = {soc_litedramcore_bankmachine5_fifo_in_last, soc_litedramcore_bankmachine5_fifo_in_first, soc_litedramcore_bankmachine5_fifo_in_payload_addr, soc_litedramcore_bankmachine5_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine5_fifo_out_last, soc_litedramcore_bankmachine5_fifo_out_first, soc_litedramcore_bankmachine5_fifo_out_payload_addr, soc_litedramcore_bankmachine5_fifo_out_payload_we} = soc_litedramcore_bankmachine5_syncfifo5_dout; +assign soc_litedramcore_bankmachine5_sink_ready = soc_litedramcore_bankmachine5_syncfifo5_writable; +assign soc_litedramcore_bankmachine5_syncfifo5_we = soc_litedramcore_bankmachine5_sink_valid; +assign soc_litedramcore_bankmachine5_fifo_in_first = soc_litedramcore_bankmachine5_sink_first; +assign soc_litedramcore_bankmachine5_fifo_in_last = soc_litedramcore_bankmachine5_sink_last; +assign soc_litedramcore_bankmachine5_fifo_in_payload_we = soc_litedramcore_bankmachine5_sink_payload_we; +assign soc_litedramcore_bankmachine5_fifo_in_payload_addr = soc_litedramcore_bankmachine5_sink_payload_addr; +assign soc_litedramcore_bankmachine5_source_valid = soc_litedramcore_bankmachine5_syncfifo5_readable; +assign soc_litedramcore_bankmachine5_source_first = soc_litedramcore_bankmachine5_fifo_out_first; +assign soc_litedramcore_bankmachine5_source_last = soc_litedramcore_bankmachine5_fifo_out_last; +assign soc_litedramcore_bankmachine5_source_payload_we = soc_litedramcore_bankmachine5_fifo_out_payload_we; +assign soc_litedramcore_bankmachine5_source_payload_addr = soc_litedramcore_bankmachine5_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine5_syncfifo5_re = soc_litedramcore_bankmachine5_source_ready; +always @(*) begin + soc_litedramcore_bankmachine5_wrport_adr = 3'd0; + if (soc_litedramcore_bankmachine5_replace) begin + soc_litedramcore_bankmachine5_wrport_adr = (soc_litedramcore_bankmachine5_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine5_wrport_adr = soc_litedramcore_bankmachine5_produce; + end +end +assign soc_litedramcore_bankmachine5_wrport_dat_w = soc_litedramcore_bankmachine5_syncfifo5_din; +assign soc_litedramcore_bankmachine5_wrport_we = (soc_litedramcore_bankmachine5_syncfifo5_we & (soc_litedramcore_bankmachine5_syncfifo5_writable | soc_litedramcore_bankmachine5_replace)); +assign soc_litedramcore_bankmachine5_do_read = (soc_litedramcore_bankmachine5_syncfifo5_readable & soc_litedramcore_bankmachine5_syncfifo5_re); +assign soc_litedramcore_bankmachine5_rdport_adr = soc_litedramcore_bankmachine5_consume; +assign soc_litedramcore_bankmachine5_syncfifo5_dout = soc_litedramcore_bankmachine5_rdport_dat_r; +assign soc_litedramcore_bankmachine5_syncfifo5_writable = (soc_litedramcore_bankmachine5_level != 4'd8); +assign soc_litedramcore_bankmachine5_syncfifo5_readable = (soc_litedramcore_bankmachine5_level != 1'd0); +assign soc_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine5_pipe_valid_source_valid) | soc_litedramcore_bankmachine5_pipe_valid_source_ready); +assign soc_litedramcore_bankmachine5_pipe_valid_sink_valid = soc_litedramcore_bankmachine5_sink_sink_valid; +assign soc_litedramcore_bankmachine5_sink_sink_ready = soc_litedramcore_bankmachine5_pipe_valid_sink_ready; +assign soc_litedramcore_bankmachine5_pipe_valid_sink_first = soc_litedramcore_bankmachine5_sink_sink_first; +assign soc_litedramcore_bankmachine5_pipe_valid_sink_last = soc_litedramcore_bankmachine5_sink_sink_last; +assign soc_litedramcore_bankmachine5_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine5_sink_sink_payload_we; +assign soc_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine5_sink_sink_payload_addr; +assign soc_litedramcore_bankmachine5_source_source_valid = soc_litedramcore_bankmachine5_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine5_pipe_valid_source_ready = soc_litedramcore_bankmachine5_source_source_ready; +assign soc_litedramcore_bankmachine5_source_source_first = soc_litedramcore_bankmachine5_pipe_valid_source_first; +assign soc_litedramcore_bankmachine5_source_source_last = soc_litedramcore_bankmachine5_pipe_valid_source_last; +assign soc_litedramcore_bankmachine5_source_source_payload_we = soc_litedramcore_bankmachine5_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine5_source_source_payload_addr = soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr; +always @(*) begin + bankmachine5_next_state = 3'd0; + soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine5_cmd_valid = 1'd0; + soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine5_row_close = 1'd0; + soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine5_row_open = 1'd0; + bankmachine5_next_state = bankmachine5_state; + case (bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine5_cmd_ready) begin + bankmachine5_next_state = 3'd5; + end + soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd1; + soc_litedramcore_bankmachine5_cmd_payload_we = 1'd1; + soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + end + soc_litedramcore_bankmachine5_row_close = 1'd1; + end + 2'd2: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + bankmachine5_next_state = 3'd5; + end + soc_litedramcore_bankmachine5_row_close = 1'd1; + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd1; + soc_litedramcore_bankmachine5_row_open = 1'd1; + soc_litedramcore_bankmachine5_cmd_valid = 1'd1; + soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + if (soc_litedramcore_bankmachine5_cmd_ready) begin + bankmachine5_next_state = 3'd6; + end + soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + if (soc_litedramcore_bankmachine5_twtpcon_ready) begin + soc_litedramcore_bankmachine5_refresh_gnt = 1'd1; + end + soc_litedramcore_bankmachine5_row_close = 1'd1; + soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + if ((~soc_litedramcore_bankmachine5_refresh_req)) begin + bankmachine5_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine5_next_state = 2'd3; + end + 3'd6: begin + bankmachine5_next_state = 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + bankmachine5_next_state = 3'd4; + end else begin + if (soc_litedramcore_bankmachine5_source_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + soc_litedramcore_bankmachine5_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine5_source_source_payload_we) begin + soc_litedramcore_bankmachine5_req_wdata_ready = soc_litedramcore_bankmachine5_cmd_ready; + soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd1; + soc_litedramcore_bankmachine5_cmd_payload_we = 1'd1; + end else begin + soc_litedramcore_bankmachine5_req_rdata_valid = soc_litedramcore_bankmachine5_cmd_ready; + soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd1; + end + soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd1; + if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin + bankmachine5_next_state = 2'd2; + end + end else begin + bankmachine5_next_state = 1'd1; + end + end else begin + bankmachine5_next_state = 2'd3; + end + end + end + end + endcase +end +assign soc_litedramcore_bankmachine6_sink_valid = soc_litedramcore_bankmachine6_req_valid; +assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_sink_ready; +assign soc_litedramcore_bankmachine6_sink_payload_we = soc_litedramcore_bankmachine6_req_we; +assign soc_litedramcore_bankmachine6_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr; +assign soc_litedramcore_bankmachine6_sink_sink_valid = soc_litedramcore_bankmachine6_source_valid; +assign soc_litedramcore_bankmachine6_source_ready = soc_litedramcore_bankmachine6_sink_sink_ready; +assign soc_litedramcore_bankmachine6_sink_sink_first = soc_litedramcore_bankmachine6_source_first; +assign soc_litedramcore_bankmachine6_sink_sink_last = soc_litedramcore_bankmachine6_source_last; +assign soc_litedramcore_bankmachine6_sink_sink_payload_we = soc_litedramcore_bankmachine6_source_payload_we; +assign soc_litedramcore_bankmachine6_sink_sink_payload_addr = soc_litedramcore_bankmachine6_source_payload_addr; +assign soc_litedramcore_bankmachine6_source_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid); +assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_source_valid | soc_litedramcore_bankmachine6_source_source_valid); +assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_source_source_payload_addr[21:7]); +assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_a = 15'd0; + if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine6_cmd_payload_a = soc_litedramcore_bankmachine6_source_source_payload_addr[21:7]; + end else begin + soc_litedramcore_bankmachine6_cmd_payload_a = ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign soc_litedramcore_bankmachine6_twtpcon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_cmd_payload_is_write); +assign soc_litedramcore_bankmachine6_trccon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); +assign soc_litedramcore_bankmachine6_trascon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); +always @(*) begin + soc_litedramcore_bankmachine6_auto_precharge = 1'd0; + if ((soc_litedramcore_bankmachine6_source_valid & soc_litedramcore_bankmachine6_source_source_valid)) begin + if ((soc_litedramcore_bankmachine6_source_payload_addr[21:7] != soc_litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin + soc_litedramcore_bankmachine6_auto_precharge = (soc_litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign soc_litedramcore_bankmachine6_syncfifo6_din = {soc_litedramcore_bankmachine6_fifo_in_last, soc_litedramcore_bankmachine6_fifo_in_first, soc_litedramcore_bankmachine6_fifo_in_payload_addr, soc_litedramcore_bankmachine6_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine6_fifo_out_last, soc_litedramcore_bankmachine6_fifo_out_first, soc_litedramcore_bankmachine6_fifo_out_payload_addr, soc_litedramcore_bankmachine6_fifo_out_payload_we} = soc_litedramcore_bankmachine6_syncfifo6_dout; +assign soc_litedramcore_bankmachine6_sink_ready = soc_litedramcore_bankmachine6_syncfifo6_writable; +assign soc_litedramcore_bankmachine6_syncfifo6_we = soc_litedramcore_bankmachine6_sink_valid; +assign soc_litedramcore_bankmachine6_fifo_in_first = soc_litedramcore_bankmachine6_sink_first; +assign soc_litedramcore_bankmachine6_fifo_in_last = soc_litedramcore_bankmachine6_sink_last; +assign soc_litedramcore_bankmachine6_fifo_in_payload_we = soc_litedramcore_bankmachine6_sink_payload_we; +assign soc_litedramcore_bankmachine6_fifo_in_payload_addr = soc_litedramcore_bankmachine6_sink_payload_addr; +assign soc_litedramcore_bankmachine6_source_valid = soc_litedramcore_bankmachine6_syncfifo6_readable; +assign soc_litedramcore_bankmachine6_source_first = soc_litedramcore_bankmachine6_fifo_out_first; +assign soc_litedramcore_bankmachine6_source_last = soc_litedramcore_bankmachine6_fifo_out_last; +assign soc_litedramcore_bankmachine6_source_payload_we = soc_litedramcore_bankmachine6_fifo_out_payload_we; +assign soc_litedramcore_bankmachine6_source_payload_addr = soc_litedramcore_bankmachine6_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine6_syncfifo6_re = soc_litedramcore_bankmachine6_source_ready; +always @(*) begin + soc_litedramcore_bankmachine6_wrport_adr = 3'd0; + if (soc_litedramcore_bankmachine6_replace) begin + soc_litedramcore_bankmachine6_wrport_adr = (soc_litedramcore_bankmachine6_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine6_wrport_adr = soc_litedramcore_bankmachine6_produce; + end +end +assign soc_litedramcore_bankmachine6_wrport_dat_w = soc_litedramcore_bankmachine6_syncfifo6_din; +assign soc_litedramcore_bankmachine6_wrport_we = (soc_litedramcore_bankmachine6_syncfifo6_we & (soc_litedramcore_bankmachine6_syncfifo6_writable | soc_litedramcore_bankmachine6_replace)); +assign soc_litedramcore_bankmachine6_do_read = (soc_litedramcore_bankmachine6_syncfifo6_readable & soc_litedramcore_bankmachine6_syncfifo6_re); +assign soc_litedramcore_bankmachine6_rdport_adr = soc_litedramcore_bankmachine6_consume; +assign soc_litedramcore_bankmachine6_syncfifo6_dout = soc_litedramcore_bankmachine6_rdport_dat_r; +assign soc_litedramcore_bankmachine6_syncfifo6_writable = (soc_litedramcore_bankmachine6_level != 4'd8); +assign soc_litedramcore_bankmachine6_syncfifo6_readable = (soc_litedramcore_bankmachine6_level != 1'd0); +assign soc_litedramcore_bankmachine6_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine6_pipe_valid_source_valid) | soc_litedramcore_bankmachine6_pipe_valid_source_ready); +assign soc_litedramcore_bankmachine6_pipe_valid_sink_valid = soc_litedramcore_bankmachine6_sink_sink_valid; +assign soc_litedramcore_bankmachine6_sink_sink_ready = soc_litedramcore_bankmachine6_pipe_valid_sink_ready; +assign soc_litedramcore_bankmachine6_pipe_valid_sink_first = soc_litedramcore_bankmachine6_sink_sink_first; +assign soc_litedramcore_bankmachine6_pipe_valid_sink_last = soc_litedramcore_bankmachine6_sink_sink_last; +assign soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine6_sink_sink_payload_we; +assign soc_litedramcore_bankmachine6_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine6_sink_sink_payload_addr; +assign soc_litedramcore_bankmachine6_source_source_valid = soc_litedramcore_bankmachine6_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine6_pipe_valid_source_ready = soc_litedramcore_bankmachine6_source_source_ready; +assign soc_litedramcore_bankmachine6_source_source_first = soc_litedramcore_bankmachine6_pipe_valid_source_first; +assign soc_litedramcore_bankmachine6_source_source_last = soc_litedramcore_bankmachine6_pipe_valid_source_last; +assign soc_litedramcore_bankmachine6_source_source_payload_we = soc_litedramcore_bankmachine6_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine6_source_source_payload_addr = soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr; +always @(*) begin + bankmachine6_next_state = 3'd0; + soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine6_cmd_valid = 1'd0; + soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine6_row_close = 1'd0; + soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine6_row_open = 1'd0; + bankmachine6_next_state = bankmachine6_state; + case (bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine6_cmd_ready) begin + bankmachine6_next_state = 3'd5; + end + soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd1; + soc_litedramcore_bankmachine6_cmd_payload_we = 1'd1; + soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; + end + soc_litedramcore_bankmachine6_row_close = 1'd1; + end + 2'd2: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + bankmachine6_next_state = 3'd5; + end + soc_litedramcore_bankmachine6_row_close = 1'd1; + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd1; + soc_litedramcore_bankmachine6_row_open = 1'd1; + soc_litedramcore_bankmachine6_cmd_valid = 1'd1; + soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; + if (soc_litedramcore_bankmachine6_cmd_ready) begin + bankmachine6_next_state = 3'd6; + end + soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + if (soc_litedramcore_bankmachine6_twtpcon_ready) begin + soc_litedramcore_bankmachine6_refresh_gnt = 1'd1; + end + soc_litedramcore_bankmachine6_row_close = 1'd1; + soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; + if ((~soc_litedramcore_bankmachine6_refresh_req)) begin + bankmachine6_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine6_next_state = 2'd3; + end + 3'd6: begin + bankmachine6_next_state = 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + bankmachine6_next_state = 3'd4; + end else begin + if (soc_litedramcore_bankmachine6_source_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + soc_litedramcore_bankmachine6_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine6_source_source_payload_we) begin + soc_litedramcore_bankmachine6_req_wdata_ready = soc_litedramcore_bankmachine6_cmd_ready; + soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd1; + soc_litedramcore_bankmachine6_cmd_payload_we = 1'd1; + end else begin + soc_litedramcore_bankmachine6_req_rdata_valid = soc_litedramcore_bankmachine6_cmd_ready; + soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd1; + end + soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd1; + if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin + bankmachine6_next_state = 2'd2; + end + end else begin + bankmachine6_next_state = 1'd1; + end + end else begin + bankmachine6_next_state = 2'd3; + end + end + end + end + endcase +end +assign soc_litedramcore_bankmachine7_sink_valid = soc_litedramcore_bankmachine7_req_valid; +assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_sink_ready; +assign soc_litedramcore_bankmachine7_sink_payload_we = soc_litedramcore_bankmachine7_req_we; +assign soc_litedramcore_bankmachine7_sink_payload_addr = soc_litedramcore_bankmachine7_req_addr; +assign soc_litedramcore_bankmachine7_sink_sink_valid = soc_litedramcore_bankmachine7_source_valid; +assign soc_litedramcore_bankmachine7_source_ready = soc_litedramcore_bankmachine7_sink_sink_ready; +assign soc_litedramcore_bankmachine7_sink_sink_first = soc_litedramcore_bankmachine7_source_first; +assign soc_litedramcore_bankmachine7_sink_sink_last = soc_litedramcore_bankmachine7_source_last; +assign soc_litedramcore_bankmachine7_sink_sink_payload_we = soc_litedramcore_bankmachine7_source_payload_we; +assign soc_litedramcore_bankmachine7_sink_sink_payload_addr = soc_litedramcore_bankmachine7_source_payload_addr; +assign soc_litedramcore_bankmachine7_source_source_ready = (soc_litedramcore_bankmachine7_req_wdata_ready | soc_litedramcore_bankmachine7_req_rdata_valid); +assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_source_valid | soc_litedramcore_bankmachine7_source_source_valid); +assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_source_source_payload_addr[21:7]); +assign soc_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_a = 15'd0; + if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine7_cmd_payload_a = soc_litedramcore_bankmachine7_source_source_payload_addr[21:7]; + end else begin + soc_litedramcore_bankmachine7_cmd_payload_a = ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign soc_litedramcore_bankmachine7_twtpcon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_cmd_payload_is_write); +assign soc_litedramcore_bankmachine7_trccon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); +assign soc_litedramcore_bankmachine7_trascon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); +always @(*) begin + soc_litedramcore_bankmachine7_auto_precharge = 1'd0; + if ((soc_litedramcore_bankmachine7_source_valid & soc_litedramcore_bankmachine7_source_source_valid)) begin + if ((soc_litedramcore_bankmachine7_source_payload_addr[21:7] != soc_litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin + soc_litedramcore_bankmachine7_auto_precharge = (soc_litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign soc_litedramcore_bankmachine7_syncfifo7_din = {soc_litedramcore_bankmachine7_fifo_in_last, soc_litedramcore_bankmachine7_fifo_in_first, soc_litedramcore_bankmachine7_fifo_in_payload_addr, soc_litedramcore_bankmachine7_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine7_fifo_out_last, soc_litedramcore_bankmachine7_fifo_out_first, soc_litedramcore_bankmachine7_fifo_out_payload_addr, soc_litedramcore_bankmachine7_fifo_out_payload_we} = soc_litedramcore_bankmachine7_syncfifo7_dout; +assign soc_litedramcore_bankmachine7_sink_ready = soc_litedramcore_bankmachine7_syncfifo7_writable; +assign soc_litedramcore_bankmachine7_syncfifo7_we = soc_litedramcore_bankmachine7_sink_valid; +assign soc_litedramcore_bankmachine7_fifo_in_first = soc_litedramcore_bankmachine7_sink_first; +assign soc_litedramcore_bankmachine7_fifo_in_last = soc_litedramcore_bankmachine7_sink_last; +assign soc_litedramcore_bankmachine7_fifo_in_payload_we = soc_litedramcore_bankmachine7_sink_payload_we; +assign soc_litedramcore_bankmachine7_fifo_in_payload_addr = soc_litedramcore_bankmachine7_sink_payload_addr; +assign soc_litedramcore_bankmachine7_source_valid = soc_litedramcore_bankmachine7_syncfifo7_readable; +assign soc_litedramcore_bankmachine7_source_first = soc_litedramcore_bankmachine7_fifo_out_first; +assign soc_litedramcore_bankmachine7_source_last = soc_litedramcore_bankmachine7_fifo_out_last; +assign soc_litedramcore_bankmachine7_source_payload_we = soc_litedramcore_bankmachine7_fifo_out_payload_we; +assign soc_litedramcore_bankmachine7_source_payload_addr = soc_litedramcore_bankmachine7_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine7_syncfifo7_re = soc_litedramcore_bankmachine7_source_ready; +always @(*) begin + soc_litedramcore_bankmachine7_wrport_adr = 3'd0; + if (soc_litedramcore_bankmachine7_replace) begin + soc_litedramcore_bankmachine7_wrport_adr = (soc_litedramcore_bankmachine7_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine7_wrport_adr = soc_litedramcore_bankmachine7_produce; + end +end +assign soc_litedramcore_bankmachine7_wrport_dat_w = soc_litedramcore_bankmachine7_syncfifo7_din; +assign soc_litedramcore_bankmachine7_wrport_we = (soc_litedramcore_bankmachine7_syncfifo7_we & (soc_litedramcore_bankmachine7_syncfifo7_writable | soc_litedramcore_bankmachine7_replace)); +assign soc_litedramcore_bankmachine7_do_read = (soc_litedramcore_bankmachine7_syncfifo7_readable & soc_litedramcore_bankmachine7_syncfifo7_re); +assign soc_litedramcore_bankmachine7_rdport_adr = soc_litedramcore_bankmachine7_consume; +assign soc_litedramcore_bankmachine7_syncfifo7_dout = soc_litedramcore_bankmachine7_rdport_dat_r; +assign soc_litedramcore_bankmachine7_syncfifo7_writable = (soc_litedramcore_bankmachine7_level != 4'd8); +assign soc_litedramcore_bankmachine7_syncfifo7_readable = (soc_litedramcore_bankmachine7_level != 1'd0); +assign soc_litedramcore_bankmachine7_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine7_pipe_valid_source_valid) | soc_litedramcore_bankmachine7_pipe_valid_source_ready); +assign soc_litedramcore_bankmachine7_pipe_valid_sink_valid = soc_litedramcore_bankmachine7_sink_sink_valid; +assign soc_litedramcore_bankmachine7_sink_sink_ready = soc_litedramcore_bankmachine7_pipe_valid_sink_ready; +assign soc_litedramcore_bankmachine7_pipe_valid_sink_first = soc_litedramcore_bankmachine7_sink_sink_first; +assign soc_litedramcore_bankmachine7_pipe_valid_sink_last = soc_litedramcore_bankmachine7_sink_sink_last; +assign soc_litedramcore_bankmachine7_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine7_sink_sink_payload_we; +assign soc_litedramcore_bankmachine7_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine7_sink_sink_payload_addr; +assign soc_litedramcore_bankmachine7_source_source_valid = soc_litedramcore_bankmachine7_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine7_pipe_valid_source_ready = soc_litedramcore_bankmachine7_source_source_ready; +assign soc_litedramcore_bankmachine7_source_source_first = soc_litedramcore_bankmachine7_pipe_valid_source_first; +assign soc_litedramcore_bankmachine7_source_source_last = soc_litedramcore_bankmachine7_pipe_valid_source_last; +assign soc_litedramcore_bankmachine7_source_source_payload_we = soc_litedramcore_bankmachine7_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine7_source_source_payload_addr = soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr; +always @(*) begin + bankmachine7_next_state = 3'd0; + soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine7_cmd_valid = 1'd0; + soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine7_row_close = 1'd0; + soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine7_row_open = 1'd0; + bankmachine7_next_state = bankmachine7_state; + case (bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine7_cmd_ready) begin + bankmachine7_next_state = 3'd5; + end + soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd1; + soc_litedramcore_bankmachine7_cmd_payload_we = 1'd1; + soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + end + soc_litedramcore_bankmachine7_row_close = 1'd1; + end + 2'd2: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + bankmachine7_next_state = 3'd5; + end + soc_litedramcore_bankmachine7_row_close = 1'd1; + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd1; + soc_litedramcore_bankmachine7_row_open = 1'd1; + soc_litedramcore_bankmachine7_cmd_valid = 1'd1; + soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + if (soc_litedramcore_bankmachine7_cmd_ready) begin + bankmachine7_next_state = 3'd6; + end + soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + if (soc_litedramcore_bankmachine7_twtpcon_ready) begin + soc_litedramcore_bankmachine7_refresh_gnt = 1'd1; + end + soc_litedramcore_bankmachine7_row_close = 1'd1; + soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + if ((~soc_litedramcore_bankmachine7_refresh_req)) begin + bankmachine7_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine7_next_state = 2'd3; + end + 3'd6: begin + bankmachine7_next_state = 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + bankmachine7_next_state = 3'd4; + end else begin + if (soc_litedramcore_bankmachine7_source_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + soc_litedramcore_bankmachine7_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine7_source_source_payload_we) begin + soc_litedramcore_bankmachine7_req_wdata_ready = soc_litedramcore_bankmachine7_cmd_ready; + soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd1; + soc_litedramcore_bankmachine7_cmd_payload_we = 1'd1; + end else begin + soc_litedramcore_bankmachine7_req_rdata_valid = soc_litedramcore_bankmachine7_cmd_ready; + soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd1; + end + soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd1; + if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin + bankmachine7_next_state = 2'd2; + end + end else begin + bankmachine7_next_state = 1'd1; + end + end else begin + bankmachine7_next_state = 2'd3; + end + end + end + end + endcase +end +assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); +assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); +assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready); +assign soc_litedramcore_tccdcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_cmd_payload_is_write | soc_litedramcore_choose_req_cmd_payload_is_read)); +assign soc_litedramcore_cas_allowed = soc_litedramcore_tccdcon_ready; +assign soc_litedramcore_twtrcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); +assign soc_litedramcore_read_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_read) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_read)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_read)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_read)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_read)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_read)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_read)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_read)); +assign soc_litedramcore_write_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_write) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_write)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_write)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_write)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_write)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_write)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_write)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_write)); +assign soc_litedramcore_max_time0 = (soc_litedramcore_time0 == 1'd0); +assign soc_litedramcore_max_time1 = (soc_litedramcore_time1 == 1'd0); +assign soc_litedramcore_bankmachine0_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine1_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine2_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine3_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine4_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine5_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine6_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine7_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_go_to_refresh = (((((((soc_litedramcore_bankmachine0_refresh_gnt & soc_litedramcore_bankmachine1_refresh_gnt) & soc_litedramcore_bankmachine2_refresh_gnt) & soc_litedramcore_bankmachine3_refresh_gnt) & soc_litedramcore_bankmachine4_refresh_gnt) & soc_litedramcore_bankmachine5_refresh_gnt) & soc_litedramcore_bankmachine6_refresh_gnt) & soc_litedramcore_bankmachine7_refresh_gnt); +assign soc_litedramcore_interface_rdata = {soc_litedramcore_dfi_p3_rddata, soc_litedramcore_dfi_p2_rddata, soc_litedramcore_dfi_p1_rddata, soc_litedramcore_dfi_p0_rddata}; +assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; +assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); +always @(*) begin + soc_litedramcore_choose_cmd_valids = 8'd0; + soc_litedramcore_choose_cmd_valids[0] = (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[1] = (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[2] = (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[3] = (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[4] = (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[5] = (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[6] = (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[7] = (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); +end +assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids; +assign soc_litedramcore_choose_cmd_cmd_valid = rhs_self8; +assign soc_litedramcore_choose_cmd_cmd_payload_a = rhs_self9; +assign soc_litedramcore_choose_cmd_cmd_payload_ba = rhs_self10; +assign soc_litedramcore_choose_cmd_cmd_payload_is_read = rhs_self11; +assign soc_litedramcore_choose_cmd_cmd_payload_is_write = rhs_self12; +assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_self13; +always @(*) begin + soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; + if (soc_litedramcore_choose_cmd_cmd_valid) begin + soc_litedramcore_choose_cmd_cmd_payload_cas = t_self0; + end +end +always @(*) begin + soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; + if (soc_litedramcore_choose_cmd_cmd_valid) begin + soc_litedramcore_choose_cmd_cmd_payload_ras = t_self1; + end +end +always @(*) begin + soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; + if (soc_litedramcore_choose_cmd_cmd_valid) begin + soc_litedramcore_choose_cmd_cmd_payload_we = t_self2; + end +end +assign soc_litedramcore_choose_cmd_ce = (soc_litedramcore_choose_cmd_cmd_ready | (~soc_litedramcore_choose_cmd_cmd_valid)); +always @(*) begin + soc_litedramcore_choose_req_valids = 8'd0; + soc_litedramcore_choose_req_valids[0] = (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[1] = (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[2] = (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[3] = (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[4] = (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[5] = (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[6] = (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[7] = (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); +end +assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids; +assign soc_litedramcore_choose_req_cmd_valid = rhs_self14; +assign soc_litedramcore_choose_req_cmd_payload_a = rhs_self15; +assign soc_litedramcore_choose_req_cmd_payload_ba = rhs_self16; +assign soc_litedramcore_choose_req_cmd_payload_is_read = rhs_self17; +assign soc_litedramcore_choose_req_cmd_payload_is_write = rhs_self18; +assign soc_litedramcore_choose_req_cmd_payload_is_cmd = rhs_self19; +always @(*) begin + soc_litedramcore_choose_req_cmd_payload_cas = 1'd0; + if (soc_litedramcore_choose_req_cmd_valid) begin + soc_litedramcore_choose_req_cmd_payload_cas = t_self3; + end +end +always @(*) begin + soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; + if (soc_litedramcore_choose_req_cmd_valid) begin + soc_litedramcore_choose_req_cmd_payload_ras = t_self4; + end +end +always @(*) begin + soc_litedramcore_choose_req_cmd_payload_we = 1'd0; + if (soc_litedramcore_choose_req_cmd_valid) begin + soc_litedramcore_choose_req_cmd_payload_we = t_self5; + end +end +always @(*) begin + soc_litedramcore_bankmachine0_cmd_ready = 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin + soc_litedramcore_bankmachine0_cmd_ready = 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin + soc_litedramcore_bankmachine0_cmd_ready = 1'd1; + end +end +always @(*) begin + soc_litedramcore_bankmachine1_cmd_ready = 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin + soc_litedramcore_bankmachine1_cmd_ready = 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin + soc_litedramcore_bankmachine1_cmd_ready = 1'd1; + end +end +always @(*) begin + soc_litedramcore_bankmachine2_cmd_ready = 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin + soc_litedramcore_bankmachine2_cmd_ready = 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin + soc_litedramcore_bankmachine2_cmd_ready = 1'd1; + end +end +always @(*) begin + soc_litedramcore_bankmachine3_cmd_ready = 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin + soc_litedramcore_bankmachine3_cmd_ready = 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin + soc_litedramcore_bankmachine3_cmd_ready = 1'd1; + end +end +always @(*) begin + soc_litedramcore_bankmachine4_cmd_ready = 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin + soc_litedramcore_bankmachine4_cmd_ready = 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin + soc_litedramcore_bankmachine4_cmd_ready = 1'd1; + end +end +always @(*) begin + soc_litedramcore_bankmachine5_cmd_ready = 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin + soc_litedramcore_bankmachine5_cmd_ready = 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin + soc_litedramcore_bankmachine5_cmd_ready = 1'd1; + end +end +always @(*) begin + soc_litedramcore_bankmachine6_cmd_ready = 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin + soc_litedramcore_bankmachine6_cmd_ready = 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin + soc_litedramcore_bankmachine6_cmd_ready = 1'd1; + end +end +always @(*) begin + soc_litedramcore_bankmachine7_cmd_ready = 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin + soc_litedramcore_bankmachine7_cmd_ready = 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin + soc_litedramcore_bankmachine7_cmd_ready = 1'd1; + end +end +assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid)); +assign soc_litedramcore_dfi_p0_reset_n = 1'd1; +assign soc_litedramcore_dfi_p0_cke = {1{soc_litedramcore_steerer0}}; +assign soc_litedramcore_dfi_p0_odt = {1{soc_litedramcore_steerer1}}; +assign soc_litedramcore_dfi_p1_reset_n = 1'd1; +assign soc_litedramcore_dfi_p1_cke = {1{soc_litedramcore_steerer2}}; +assign soc_litedramcore_dfi_p1_odt = {1{soc_litedramcore_steerer3}}; +assign soc_litedramcore_dfi_p2_reset_n = 1'd1; +assign soc_litedramcore_dfi_p2_cke = {1{soc_litedramcore_steerer4}}; +assign soc_litedramcore_dfi_p2_odt = {1{soc_litedramcore_steerer5}}; +assign soc_litedramcore_dfi_p3_reset_n = 1'd1; +assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}}; +assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}}; +assign soc_litedramcore_tfawcon_count = (((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]); +always @(*) begin + multiplexer_next_state = 4'd0; + soc_litedramcore_choose_cmd_cmd_ready = 1'd0; + soc_litedramcore_choose_cmd_want_activates = 1'd0; + soc_litedramcore_choose_req_cmd_ready = 1'd0; + soc_litedramcore_choose_req_want_reads = 1'd0; + soc_litedramcore_choose_req_want_writes = 1'd0; + soc_litedramcore_cmd_ready = 1'd0; + soc_litedramcore_en0 = 1'd0; + soc_litedramcore_en1 = 1'd0; + soc_litedramcore_steerer_sel0 = 2'd0; + soc_litedramcore_steerer_sel1 = 2'd0; + soc_litedramcore_steerer_sel2 = 2'd0; + soc_litedramcore_steerer_sel3 = 2'd0; + multiplexer_next_state = multiplexer_state; + case (multiplexer_state) + 1'd1: begin + soc_litedramcore_en1 = 1'd1; + soc_litedramcore_choose_req_want_writes = 1'd1; + if (1'd0) begin + soc_litedramcore_choose_req_cmd_ready = (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + end else begin + soc_litedramcore_choose_cmd_want_activates = soc_litedramcore_ras_allowed; + soc_litedramcore_choose_cmd_cmd_ready = ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); + soc_litedramcore_choose_req_cmd_ready = soc_litedramcore_cas_allowed; + end + soc_litedramcore_steerer_sel0 = 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel0 = 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel0 = 1'd1; + end + soc_litedramcore_steerer_sel1 = 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel1 = 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel1 = 1'd1; + end + soc_litedramcore_steerer_sel2 = 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel2 = 2'd2; + end + if (1'd1) begin + soc_litedramcore_steerer_sel2 = 1'd1; + end + soc_litedramcore_steerer_sel3 = 1'd0; + if (1'd1) begin + soc_litedramcore_steerer_sel3 = 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel3 = 1'd1; + end + if (soc_litedramcore_read_available) begin + if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin + multiplexer_next_state = 2'd3; + end + end + if (soc_litedramcore_go_to_refresh) begin + multiplexer_next_state = 2'd2; + end + end + 2'd2: begin + soc_litedramcore_steerer_sel0 = 2'd3; + soc_litedramcore_cmd_ready = 1'd1; + if (soc_litedramcore_cmd_last) begin + multiplexer_next_state = 1'd0; + end + end + 2'd3: begin + if (soc_litedramcore_twtrcon_ready) begin + multiplexer_next_state = 1'd0; + end + end + 3'd4: begin + multiplexer_next_state = 3'd5; + end + 3'd5: begin + multiplexer_next_state = 3'd6; + end + 3'd6: begin + multiplexer_next_state = 3'd7; + end + 3'd7: begin + multiplexer_next_state = 4'd8; + end + 4'd8: begin + multiplexer_next_state = 4'd9; + end + 4'd9: begin + multiplexer_next_state = 4'd10; + end + 4'd10: begin + multiplexer_next_state = 1'd1; + end + default: begin + soc_litedramcore_en0 = 1'd1; + soc_litedramcore_choose_req_want_reads = 1'd1; + if (1'd0) begin + soc_litedramcore_choose_req_cmd_ready = (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + end else begin + soc_litedramcore_choose_cmd_want_activates = soc_litedramcore_ras_allowed; + soc_litedramcore_choose_cmd_cmd_ready = ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); + soc_litedramcore_choose_req_cmd_ready = soc_litedramcore_cas_allowed; + end + soc_litedramcore_steerer_sel0 = 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel0 = 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel0 = 1'd1; + end + soc_litedramcore_steerer_sel1 = 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel1 = 2'd2; + end + if (1'd1) begin + soc_litedramcore_steerer_sel1 = 1'd1; + end + soc_litedramcore_steerer_sel2 = 1'd0; + if (1'd1) begin + soc_litedramcore_steerer_sel2 = 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel2 = 1'd1; + end + soc_litedramcore_steerer_sel3 = 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel3 = 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel3 = 1'd1; + end + if (soc_litedramcore_write_available) begin + if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin + multiplexer_next_state = 3'd4; + end + end + if (soc_litedramcore_go_to_refresh) begin + multiplexer_next_state = 2'd2; + end + end + endcase +end +assign roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock)); +assign soc_litedramcore_interface_bank0_addr = rhs_self20; +assign soc_litedramcore_interface_bank0_we = rhs_self21; +assign soc_litedramcore_interface_bank0_valid = rhs_self22; +assign roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock)); +assign soc_litedramcore_interface_bank1_addr = rhs_self23; +assign soc_litedramcore_interface_bank1_we = rhs_self24; +assign soc_litedramcore_interface_bank1_valid = rhs_self25; +assign roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock)); +assign soc_litedramcore_interface_bank2_addr = rhs_self26; +assign soc_litedramcore_interface_bank2_we = rhs_self27; +assign soc_litedramcore_interface_bank2_valid = rhs_self28; +assign roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock)); +assign soc_litedramcore_interface_bank3_addr = rhs_self29; +assign soc_litedramcore_interface_bank3_we = rhs_self30; +assign soc_litedramcore_interface_bank3_valid = rhs_self31; +assign roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock)); +assign soc_litedramcore_interface_bank4_addr = rhs_self32; +assign soc_litedramcore_interface_bank4_we = rhs_self33; +assign soc_litedramcore_interface_bank4_valid = rhs_self34; +assign roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock)); +assign soc_litedramcore_interface_bank5_addr = rhs_self35; +assign soc_litedramcore_interface_bank5_we = rhs_self36; +assign soc_litedramcore_interface_bank5_valid = rhs_self37; +assign roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock)); +assign soc_litedramcore_interface_bank6_addr = rhs_self38; +assign soc_litedramcore_interface_bank6_we = rhs_self39; +assign soc_litedramcore_interface_bank6_valid = rhs_self40; +assign roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock)); +assign soc_litedramcore_interface_bank7_addr = rhs_self41; +assign soc_litedramcore_interface_bank7_we = rhs_self42; +assign soc_litedramcore_interface_bank7_valid = rhs_self43; +assign soc_user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready)); +assign soc_user_port_wdata_ready = new_master_wdata_ready1; +assign soc_user_port_rdata_valid = new_master_rdata_valid8; +always @(*) begin + soc_litedramcore_interface_wdata = 128'd0; + soc_litedramcore_interface_wdata_we = 16'd0; + case ({new_master_wdata_ready1}) + 1'd1: begin + soc_litedramcore_interface_wdata = soc_user_port_wdata_payload_data; + soc_litedramcore_interface_wdata_we = soc_user_port_wdata_payload_we; + end + default: begin + soc_litedramcore_interface_wdata = 1'd0; + soc_litedramcore_interface_wdata_we = 1'd0; + end + endcase +end +assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata; +assign roundrobin0_grant = 1'd0; +assign roundrobin1_grant = 1'd0; +assign roundrobin2_grant = 1'd0; +assign roundrobin3_grant = 1'd0; +assign roundrobin4_grant = 1'd0; +assign roundrobin5_grant = 1'd0; +assign roundrobin6_grant = 1'd0; +assign roundrobin7_grant = 1'd0; +always @(*) begin + csr_data_width = 1'd0; + csr_data_width = 1'd0; + if ((interface0_sel != 1'd0)) begin + csr_data_width = 1'd0; + end +end +always @(*) begin + interface0_ack = 1'd0; + interface0_dat_r = 32'd0; + interface1_adr_next_value2 = 14'd0; + interface1_adr_next_value_ce2 = 1'd0; + interface1_dat_w_next_value0 = 32'd0; + interface1_dat_w_next_value_ce0 = 1'd0; + interface1_re_next_value3 = 1'd0; + interface1_re_next_value_ce3 = 1'd0; + interface1_we_next_value4 = 1'd0; + interface1_we_next_value_ce4 = 1'd0; + next_state = 2'd0; + selected_r_next_value1 = 1'd0; + selected_r_next_value_ce1 = 1'd0; + next_state = state; + case (state) + 1'd1: begin + interface1_adr_next_value2 = 1'd0; + interface1_adr_next_value_ce2 = 1'd1; + interface1_re_next_value3 = 1'd0; + interface1_re_next_value_ce3 = 1'd1; + interface1_we_next_value4 = 1'd0; + interface1_we_next_value_ce4 = 1'd1; + next_state = 2'd2; + end + 2'd2: begin + interface0_ack = 1'd1; + interface0_dat_r = 1'd0; + case (selected_r) + 1'd0: begin + interface0_dat_r = interface1_dat_r; + end + endcase + next_state = 1'd0; + end + default: begin + interface1_dat_w_next_value0 = cases_self; + interface1_dat_w_next_value_ce0 = 1'd1; + if ((interface0_cyc & interface0_stb)) begin + selected_r_next_value1 = csr_data_width; + selected_r_next_value_ce1 = 1'd1; + interface1_adr_next_value2 = interface0_adr; + interface1_adr_next_value_ce2 = 1'd1; + interface1_re_next_value3 = ((~interface0_we) & (interface0_sel != 1'd0)); + interface1_re_next_value_ce3 = 1'd1; + interface1_we_next_value4 = (interface0_we & (interface0_sel != 1'd0)); + interface1_we_next_value_ce4 = 1'd1; + next_state = 1'd1; + end + end + endcase +end +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); +assign csrbank0_init_done_r = interface0_bank_bus_dat_w[0]; +always @(*) begin + csrbank0_init_done_re = 1'd0; + csrbank0_init_done_we = 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done_re = interface0_bank_bus_we; + csrbank0_init_done_we = interface0_bank_bus_re; + end +end +assign csrbank0_init_error_r = interface0_bank_bus_dat_w[0]; +always @(*) begin + csrbank0_init_error_re = 1'd0; + csrbank0_init_error_we = 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error_re = interface0_bank_bus_we; + csrbank0_init_error_we = interface0_bank_bus_re; + end +end +assign csrbank0_init_done_w = soc_init_done_storage; +assign csrbank0_init_error_w = soc_init_error_storage; +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); +assign reserved_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + reserved_re = 1'd0; + reserved_we = 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + reserved_re = interface1_bank_bus_we; + reserved_we = interface1_bank_bus_re; + end +end +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); +assign csrbank2_dfii_control_r = interface2_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank2_dfii_control_re = 1'd0; + csrbank2_dfii_control_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control_re = interface2_bank_bus_we; + csrbank2_dfii_control_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi0_command_r = interface2_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank2_dfii_pi0_command_re = 1'd0; + csrbank2_dfii_pi0_command_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command_re = interface2_bank_bus_we; + csrbank2_dfii_pi0_command_we = interface2_bank_bus_re; + end +end +assign soc_litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; +always @(*) begin + soc_litedramcore_phaseinjector0_command_issue_re = 1'd0; + soc_litedramcore_phaseinjector0_command_issue_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + soc_litedramcore_phaseinjector0_command_issue_re = interface2_bank_bus_we; + soc_litedramcore_phaseinjector0_command_issue_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi0_address_r = interface2_bank_bus_dat_w[14:0]; +always @(*) begin + csrbank2_dfii_pi0_address_re = 1'd0; + csrbank2_dfii_pi0_address_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address_re = interface2_bank_bus_we; + csrbank2_dfii_pi0_address_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi0_baddress_r = interface2_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank2_dfii_pi0_baddress_re = 1'd0; + csrbank2_dfii_pi0_baddress_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress_re = interface2_bank_bus_we; + csrbank2_dfii_pi0_baddress_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi0_wrdata_r = interface2_bank_bus_dat_w; +always @(*) begin + csrbank2_dfii_pi0_wrdata_re = 1'd0; + csrbank2_dfii_pi0_wrdata_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata_re = interface2_bank_bus_we; + csrbank2_dfii_pi0_wrdata_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w; +always @(*) begin + csrbank2_dfii_pi0_rddata_re = 1'd0; + csrbank2_dfii_pi0_rddata_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_rddata_re = interface2_bank_bus_we; + csrbank2_dfii_pi0_rddata_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi1_command_r = interface2_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank2_dfii_pi1_command_re = 1'd0; + csrbank2_dfii_pi1_command_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi1_command_re = interface2_bank_bus_we; + csrbank2_dfii_pi1_command_we = interface2_bank_bus_re; + end +end +assign soc_litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; +always @(*) begin + soc_litedramcore_phaseinjector1_command_issue_re = 1'd0; + soc_litedramcore_phaseinjector1_command_issue_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + soc_litedramcore_phaseinjector1_command_issue_re = interface2_bank_bus_we; + soc_litedramcore_phaseinjector1_command_issue_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi1_address_r = interface2_bank_bus_dat_w[14:0]; +always @(*) begin + csrbank2_dfii_pi1_address_re = 1'd0; + csrbank2_dfii_pi1_address_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_address_re = interface2_bank_bus_we; + csrbank2_dfii_pi1_address_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi1_baddress_r = interface2_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank2_dfii_pi1_baddress_re = 1'd0; + csrbank2_dfii_pi1_baddress_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + csrbank2_dfii_pi1_baddress_re = interface2_bank_bus_we; + csrbank2_dfii_pi1_baddress_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi1_wrdata_r = interface2_bank_bus_dat_w; +always @(*) begin + csrbank2_dfii_pi1_wrdata_re = 1'd0; + csrbank2_dfii_pi1_wrdata_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_wrdata_re = interface2_bank_bus_we; + csrbank2_dfii_pi1_wrdata_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w; +always @(*) begin + csrbank2_dfii_pi1_rddata_re = 1'd0; + csrbank2_dfii_pi1_rddata_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_rddata_re = interface2_bank_bus_we; + csrbank2_dfii_pi1_rddata_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi2_command_r = interface2_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank2_dfii_pi2_command_re = 1'd0; + csrbank2_dfii_pi2_command_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi2_command_re = interface2_bank_bus_we; + csrbank2_dfii_pi2_command_we = interface2_bank_bus_re; + end +end +assign soc_litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; +always @(*) begin + soc_litedramcore_phaseinjector2_command_issue_re = 1'd0; + soc_litedramcore_phaseinjector2_command_issue_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + soc_litedramcore_phaseinjector2_command_issue_re = interface2_bank_bus_we; + soc_litedramcore_phaseinjector2_command_issue_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi2_address_r = interface2_bank_bus_dat_w[14:0]; +always @(*) begin + csrbank2_dfii_pi2_address_re = 1'd0; + csrbank2_dfii_pi2_address_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi2_address_re = interface2_bank_bus_we; + csrbank2_dfii_pi2_address_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi2_baddress_r = interface2_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank2_dfii_pi2_baddress_re = 1'd0; + csrbank2_dfii_pi2_baddress_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi2_baddress_re = interface2_bank_bus_we; + csrbank2_dfii_pi2_baddress_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi2_wrdata_r = interface2_bank_bus_dat_w; +always @(*) begin + csrbank2_dfii_pi2_wrdata_re = 1'd0; + csrbank2_dfii_pi2_wrdata_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin + csrbank2_dfii_pi2_wrdata_re = interface2_bank_bus_we; + csrbank2_dfii_pi2_wrdata_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w; +always @(*) begin + csrbank2_dfii_pi2_rddata_re = 1'd0; + csrbank2_dfii_pi2_rddata_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin + csrbank2_dfii_pi2_rddata_re = interface2_bank_bus_we; + csrbank2_dfii_pi2_rddata_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi3_command_r = interface2_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank2_dfii_pi3_command_re = 1'd0; + csrbank2_dfii_pi3_command_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin + csrbank2_dfii_pi3_command_re = interface2_bank_bus_we; + csrbank2_dfii_pi3_command_we = interface2_bank_bus_re; + end +end +assign soc_litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; +always @(*) begin + soc_litedramcore_phaseinjector3_command_issue_re = 1'd0; + soc_litedramcore_phaseinjector3_command_issue_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin + soc_litedramcore_phaseinjector3_command_issue_re = interface2_bank_bus_we; + soc_litedramcore_phaseinjector3_command_issue_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi3_address_r = interface2_bank_bus_dat_w[14:0]; +always @(*) begin + csrbank2_dfii_pi3_address_re = 1'd0; + csrbank2_dfii_pi3_address_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin + csrbank2_dfii_pi3_address_re = interface2_bank_bus_we; + csrbank2_dfii_pi3_address_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi3_baddress_r = interface2_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank2_dfii_pi3_baddress_re = 1'd0; + csrbank2_dfii_pi3_baddress_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin + csrbank2_dfii_pi3_baddress_re = interface2_bank_bus_we; + csrbank2_dfii_pi3_baddress_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi3_wrdata_r = interface2_bank_bus_dat_w; +always @(*) begin + csrbank2_dfii_pi3_wrdata_re = 1'd0; + csrbank2_dfii_pi3_wrdata_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin + csrbank2_dfii_pi3_wrdata_re = interface2_bank_bus_we; + csrbank2_dfii_pi3_wrdata_we = interface2_bank_bus_re; + end +end +assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w; +always @(*) begin + csrbank2_dfii_pi3_rddata_re = 1'd0; + csrbank2_dfii_pi3_rddata_we = 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin + csrbank2_dfii_pi3_rddata_re = interface2_bank_bus_we; + csrbank2_dfii_pi3_rddata_we = interface2_bank_bus_re; + end +end +assign soc_litedramcore_sel = soc_litedramcore_storage[0]; +assign soc_litedramcore_cke = soc_litedramcore_storage[1]; +assign soc_litedramcore_odt = soc_litedramcore_storage[2]; +assign soc_litedramcore_reset_n = soc_litedramcore_storage[3]; +assign csrbank2_dfii_control_w = soc_litedramcore_storage; +assign soc_litedramcore_phaseinjector0_cs = soc_litedramcore_phaseinjector0_command_storage[0]; +assign soc_litedramcore_phaseinjector0_we = soc_litedramcore_phaseinjector0_command_storage[1]; +assign soc_litedramcore_phaseinjector0_cas = soc_litedramcore_phaseinjector0_command_storage[2]; +assign soc_litedramcore_phaseinjector0_ras = soc_litedramcore_phaseinjector0_command_storage[3]; +assign soc_litedramcore_phaseinjector0_wren = soc_litedramcore_phaseinjector0_command_storage[4]; +assign soc_litedramcore_phaseinjector0_rden = soc_litedramcore_phaseinjector0_command_storage[5]; +assign soc_litedramcore_phaseinjector0_cs_top = soc_litedramcore_phaseinjector0_command_storage[6]; +assign soc_litedramcore_phaseinjector0_cs_bottom = soc_litedramcore_phaseinjector0_command_storage[7]; +assign csrbank2_dfii_pi0_command_w = soc_litedramcore_phaseinjector0_command_storage; +assign csrbank2_dfii_pi0_address_w = soc_litedramcore_phaseinjector0_address_storage; +assign csrbank2_dfii_pi0_baddress_w = soc_litedramcore_phaseinjector0_baddress_storage; +assign csrbank2_dfii_pi0_wrdata_w = soc_litedramcore_phaseinjector0_wrdata_storage; +assign csrbank2_dfii_pi0_rddata_w = soc_litedramcore_phaseinjector0_rddata_status; +assign soc_litedramcore_phaseinjector0_rddata_rd_stb = csrbank2_dfii_pi0_rddata_we; +assign soc_litedramcore_phaseinjector1_cs = soc_litedramcore_phaseinjector1_command_storage[0]; +assign soc_litedramcore_phaseinjector1_we = soc_litedramcore_phaseinjector1_command_storage[1]; +assign soc_litedramcore_phaseinjector1_cas = soc_litedramcore_phaseinjector1_command_storage[2]; +assign soc_litedramcore_phaseinjector1_ras = soc_litedramcore_phaseinjector1_command_storage[3]; +assign soc_litedramcore_phaseinjector1_wren = soc_litedramcore_phaseinjector1_command_storage[4]; +assign soc_litedramcore_phaseinjector1_rden = soc_litedramcore_phaseinjector1_command_storage[5]; +assign soc_litedramcore_phaseinjector1_cs_top = soc_litedramcore_phaseinjector1_command_storage[6]; +assign soc_litedramcore_phaseinjector1_cs_bottom = soc_litedramcore_phaseinjector1_command_storage[7]; +assign csrbank2_dfii_pi1_command_w = soc_litedramcore_phaseinjector1_command_storage; +assign csrbank2_dfii_pi1_address_w = soc_litedramcore_phaseinjector1_address_storage; +assign csrbank2_dfii_pi1_baddress_w = soc_litedramcore_phaseinjector1_baddress_storage; +assign csrbank2_dfii_pi1_wrdata_w = soc_litedramcore_phaseinjector1_wrdata_storage; +assign csrbank2_dfii_pi1_rddata_w = soc_litedramcore_phaseinjector1_rddata_status; +assign soc_litedramcore_phaseinjector1_rddata_rd_stb = csrbank2_dfii_pi1_rddata_we; +assign soc_litedramcore_phaseinjector2_cs = soc_litedramcore_phaseinjector2_command_storage[0]; +assign soc_litedramcore_phaseinjector2_we = soc_litedramcore_phaseinjector2_command_storage[1]; +assign soc_litedramcore_phaseinjector2_cas = soc_litedramcore_phaseinjector2_command_storage[2]; +assign soc_litedramcore_phaseinjector2_ras = soc_litedramcore_phaseinjector2_command_storage[3]; +assign soc_litedramcore_phaseinjector2_wren = soc_litedramcore_phaseinjector2_command_storage[4]; +assign soc_litedramcore_phaseinjector2_rden = soc_litedramcore_phaseinjector2_command_storage[5]; +assign soc_litedramcore_phaseinjector2_cs_top = soc_litedramcore_phaseinjector2_command_storage[6]; +assign soc_litedramcore_phaseinjector2_cs_bottom = soc_litedramcore_phaseinjector2_command_storage[7]; +assign csrbank2_dfii_pi2_command_w = soc_litedramcore_phaseinjector2_command_storage; +assign csrbank2_dfii_pi2_address_w = soc_litedramcore_phaseinjector2_address_storage; +assign csrbank2_dfii_pi2_baddress_w = soc_litedramcore_phaseinjector2_baddress_storage; +assign csrbank2_dfii_pi2_wrdata_w = soc_litedramcore_phaseinjector2_wrdata_storage; +assign csrbank2_dfii_pi2_rddata_w = soc_litedramcore_phaseinjector2_rddata_status; +assign soc_litedramcore_phaseinjector2_rddata_rd_stb = csrbank2_dfii_pi2_rddata_we; +assign soc_litedramcore_phaseinjector3_cs = soc_litedramcore_phaseinjector3_command_storage[0]; +assign soc_litedramcore_phaseinjector3_we = soc_litedramcore_phaseinjector3_command_storage[1]; +assign soc_litedramcore_phaseinjector3_cas = soc_litedramcore_phaseinjector3_command_storage[2]; +assign soc_litedramcore_phaseinjector3_ras = soc_litedramcore_phaseinjector3_command_storage[3]; +assign soc_litedramcore_phaseinjector3_wren = soc_litedramcore_phaseinjector3_command_storage[4]; +assign soc_litedramcore_phaseinjector3_rden = soc_litedramcore_phaseinjector3_command_storage[5]; +assign soc_litedramcore_phaseinjector3_cs_top = soc_litedramcore_phaseinjector3_command_storage[6]; +assign soc_litedramcore_phaseinjector3_cs_bottom = soc_litedramcore_phaseinjector3_command_storage[7]; +assign csrbank2_dfii_pi3_command_w = soc_litedramcore_phaseinjector3_command_storage; +assign csrbank2_dfii_pi3_address_w = soc_litedramcore_phaseinjector3_address_storage; +assign csrbank2_dfii_pi3_baddress_w = soc_litedramcore_phaseinjector3_baddress_storage; +assign csrbank2_dfii_pi3_wrdata_w = soc_litedramcore_phaseinjector3_wrdata_storage; +assign csrbank2_dfii_pi3_rddata_w = soc_litedramcore_phaseinjector3_rddata_status; +assign soc_litedramcore_phaseinjector3_rddata_rd_stb = csrbank2_dfii_pi3_rddata_we; +assign adr = interface1_adr; +assign re = interface1_re; +assign we = interface1_we; +assign dat_w = interface1_dat_w; +assign interface1_dat_r = dat_r; +assign interface0_bank_bus_adr = adr; +assign interface1_bank_bus_adr = adr; +assign interface2_bank_bus_adr = adr; +assign interface0_bank_bus_re = re; +assign interface1_bank_bus_re = re; +assign interface2_bank_bus_re = re; +assign interface0_bank_bus_we = we; +assign interface1_bank_bus_we = we; +assign interface2_bank_bus_we = we; +assign interface0_bank_bus_dat_w = dat_w; +assign interface1_bank_bus_dat_w = dat_w; +assign interface2_bank_bus_dat_w = dat_w; +assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); +assign slice_proxy0 = ((soc_ddrphy_bankmodel0_row * 11'h400) | soc_ddrphy_bankmodel0_write_col); +assign slice_proxy1 = ((soc_ddrphy_bankmodel0_row * 11'h400) | soc_ddrphy_bankmodel0_read_col); +assign slice_proxy2 = ((soc_ddrphy_bankmodel1_row * 11'h400) | soc_ddrphy_bankmodel1_write_col); +assign slice_proxy3 = ((soc_ddrphy_bankmodel1_row * 11'h400) | soc_ddrphy_bankmodel1_read_col); +assign slice_proxy4 = ((soc_ddrphy_bankmodel2_row * 11'h400) | soc_ddrphy_bankmodel2_write_col); +assign slice_proxy5 = ((soc_ddrphy_bankmodel2_row * 11'h400) | soc_ddrphy_bankmodel2_read_col); +assign slice_proxy6 = ((soc_ddrphy_bankmodel3_row * 11'h400) | soc_ddrphy_bankmodel3_write_col); +assign slice_proxy7 = ((soc_ddrphy_bankmodel3_row * 11'h400) | soc_ddrphy_bankmodel3_read_col); +assign slice_proxy8 = ((soc_ddrphy_bankmodel4_row * 11'h400) | soc_ddrphy_bankmodel4_write_col); +assign slice_proxy9 = ((soc_ddrphy_bankmodel4_row * 11'h400) | soc_ddrphy_bankmodel4_read_col); +assign slice_proxy10 = ((soc_ddrphy_bankmodel5_row * 11'h400) | soc_ddrphy_bankmodel5_write_col); +assign slice_proxy11 = ((soc_ddrphy_bankmodel5_row * 11'h400) | soc_ddrphy_bankmodel5_read_col); +assign slice_proxy12 = ((soc_ddrphy_bankmodel6_row * 11'h400) | soc_ddrphy_bankmodel6_write_col); +assign slice_proxy13 = ((soc_ddrphy_bankmodel6_row * 11'h400) | soc_ddrphy_bankmodel6_read_col); +assign slice_proxy14 = ((soc_ddrphy_bankmodel7_row * 11'h400) | soc_ddrphy_bankmodel7_write_col); +assign slice_proxy15 = ((soc_ddrphy_bankmodel7_row * 11'h400) | soc_ddrphy_bankmodel7_read_col); +always @(*) begin + rhs_self0 = 30'd0; + case (grant) + default: begin + rhs_self0 = soc_wb_bus_adr; + end + endcase +end +always @(*) begin + rhs_self1 = 32'd0; + case (grant) + default: begin + rhs_self1 = soc_wb_bus_dat_w; + end + endcase +end +always @(*) begin + rhs_self2 = 4'd0; + case (grant) + default: begin + rhs_self2 = soc_wb_bus_sel; + end + endcase +end +always @(*) begin + rhs_self3 = 1'd0; + case (grant) + default: begin + rhs_self3 = soc_wb_bus_cyc; + end + endcase +end +always @(*) begin + rhs_self4 = 1'd0; + case (grant) + default: begin + rhs_self4 = soc_wb_bus_stb; + end + endcase +end +always @(*) begin + rhs_self5 = 1'd0; + case (grant) + default: begin + rhs_self5 = soc_wb_bus_we; + end + endcase +end +always @(*) begin + rhs_self6 = 3'd0; + case (grant) + default: begin + rhs_self6 = soc_wb_bus_cti; + end + endcase +end +always @(*) begin + rhs_self7 = 2'd0; + case (grant) + default: begin + rhs_self7 = soc_wb_bus_bte; + end + endcase +end +always @(*) begin + rhs_self8 = 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self8 = soc_litedramcore_choose_cmd_valids[0]; + end + 1'd1: begin + rhs_self8 = soc_litedramcore_choose_cmd_valids[1]; + end + 2'd2: begin + rhs_self8 = soc_litedramcore_choose_cmd_valids[2]; + end + 2'd3: begin + rhs_self8 = soc_litedramcore_choose_cmd_valids[3]; + end + 3'd4: begin + rhs_self8 = soc_litedramcore_choose_cmd_valids[4]; + end + 3'd5: begin + rhs_self8 = soc_litedramcore_choose_cmd_valids[5]; + end + 3'd6: begin + rhs_self8 = soc_litedramcore_choose_cmd_valids[6]; + end + default: begin + rhs_self8 = soc_litedramcore_choose_cmd_valids[7]; + end + endcase +end +always @(*) begin + rhs_self9 = 15'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self9 = soc_litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_self9 = soc_litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_self9 = soc_litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_self9 = soc_litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_self9 = soc_litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_self9 = soc_litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_self9 = soc_litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_self9 = soc_litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_self10 = 3'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self10 = soc_litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_self10 = soc_litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_self10 = soc_litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_self10 = soc_litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_self10 = soc_litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_self10 = soc_litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_self10 = soc_litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_self10 = soc_litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_self11 = 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self11 = soc_litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_self11 = soc_litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_self11 = soc_litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_self11 = soc_litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_self11 = soc_litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_self11 = soc_litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_self11 = soc_litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_self11 = soc_litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_self12 = 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self12 = soc_litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_self12 = soc_litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_self12 = soc_litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_self12 = soc_litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_self12 = soc_litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_self12 = soc_litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_self12 = soc_litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_self12 = soc_litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_self13 = 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self13 = soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_self13 = soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_self13 = soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_self13 = soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_self13 = soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_self13 = soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_self13 = soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_self13 = soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_self0 = 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + t_self0 = soc_litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_self0 = soc_litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_self0 = soc_litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_self0 = soc_litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_self0 = soc_litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_self0 = soc_litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_self0 = soc_litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_self0 = soc_litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_self1 = 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + t_self1 = soc_litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_self1 = soc_litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_self1 = soc_litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_self1 = soc_litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_self1 = soc_litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_self1 = soc_litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_self1 = soc_litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_self1 = soc_litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_self2 = 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + t_self2 = soc_litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_self2 = soc_litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_self2 = soc_litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_self2 = soc_litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_self2 = soc_litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_self2 = soc_litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_self2 = soc_litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_self2 = soc_litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self14 = 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + rhs_self14 = soc_litedramcore_choose_req_valids[0]; + end + 1'd1: begin + rhs_self14 = soc_litedramcore_choose_req_valids[1]; + end + 2'd2: begin + rhs_self14 = soc_litedramcore_choose_req_valids[2]; + end + 2'd3: begin + rhs_self14 = soc_litedramcore_choose_req_valids[3]; + end + 3'd4: begin + rhs_self14 = soc_litedramcore_choose_req_valids[4]; + end + 3'd5: begin + rhs_self14 = soc_litedramcore_choose_req_valids[5]; + end + 3'd6: begin + rhs_self14 = soc_litedramcore_choose_req_valids[6]; + end + default: begin + rhs_self14 = soc_litedramcore_choose_req_valids[7]; + end + endcase +end +always @(*) begin + rhs_self15 = 15'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + rhs_self15 = soc_litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_self15 = soc_litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_self15 = soc_litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_self15 = soc_litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_self15 = soc_litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_self15 = soc_litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_self15 = soc_litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_self15 = soc_litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_self16 = 3'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + rhs_self16 = soc_litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_self16 = soc_litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_self16 = soc_litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_self16 = soc_litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_self16 = soc_litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_self16 = soc_litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_self16 = soc_litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_self16 = soc_litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_self17 = 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + rhs_self17 = soc_litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_self17 = soc_litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_self17 = soc_litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_self17 = soc_litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_self17 = soc_litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_self17 = soc_litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_self17 = soc_litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_self17 = soc_litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_self18 = 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + rhs_self18 = soc_litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_self18 = soc_litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_self18 = soc_litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_self18 = soc_litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_self18 = soc_litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_self18 = soc_litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_self18 = soc_litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_self18 = soc_litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_self19 = 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + rhs_self19 = soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_self19 = soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_self19 = soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_self19 = soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_self19 = soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_self19 = soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_self19 = soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_self19 = soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_self3 = 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + t_self3 = soc_litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_self3 = soc_litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_self3 = soc_litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_self3 = soc_litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_self3 = soc_litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_self3 = soc_litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_self3 = soc_litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_self3 = soc_litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_self4 = 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + t_self4 = soc_litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_self4 = soc_litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_self4 = soc_litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_self4 = soc_litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_self4 = soc_litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_self4 = soc_litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_self4 = soc_litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_self4 = soc_litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_self5 = 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + t_self5 = soc_litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_self5 = soc_litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_self5 = soc_litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_self5 = soc_litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_self5 = soc_litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_self5 = soc_litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_self5 = soc_litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_self5 = soc_litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self20 = 22'd0; + case (roundrobin0_grant) + default: begin + rhs_self20 = {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self21 = 1'd0; + case (roundrobin0_grant) + default: begin + rhs_self21 = soc_user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self22 = 1'd0; + case (roundrobin0_grant) + default: begin + rhs_self22 = (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self23 = 22'd0; + case (roundrobin1_grant) + default: begin + rhs_self23 = {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self24 = 1'd0; + case (roundrobin1_grant) + default: begin + rhs_self24 = soc_user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self25 = 1'd0; + case (roundrobin1_grant) + default: begin + rhs_self25 = (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self26 = 22'd0; + case (roundrobin2_grant) + default: begin + rhs_self26 = {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self27 = 1'd0; + case (roundrobin2_grant) + default: begin + rhs_self27 = soc_user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self28 = 1'd0; + case (roundrobin2_grant) + default: begin + rhs_self28 = (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self29 = 22'd0; + case (roundrobin3_grant) + default: begin + rhs_self29 = {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self30 = 1'd0; + case (roundrobin3_grant) + default: begin + rhs_self30 = soc_user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self31 = 1'd0; + case (roundrobin3_grant) + default: begin + rhs_self31 = (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self32 = 22'd0; + case (roundrobin4_grant) + default: begin + rhs_self32 = {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self33 = 1'd0; + case (roundrobin4_grant) + default: begin + rhs_self33 = soc_user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self34 = 1'd0; + case (roundrobin4_grant) + default: begin + rhs_self34 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self35 = 22'd0; + case (roundrobin5_grant) + default: begin + rhs_self35 = {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self36 = 1'd0; + case (roundrobin5_grant) + default: begin + rhs_self36 = soc_user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self37 = 1'd0; + case (roundrobin5_grant) + default: begin + rhs_self37 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self38 = 22'd0; + case (roundrobin6_grant) + default: begin + rhs_self38 = {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self39 = 1'd0; + case (roundrobin6_grant) + default: begin + rhs_self39 = soc_user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self40 = 1'd0; + case (roundrobin6_grant) + default: begin + rhs_self40 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self41 = 22'd0; + case (roundrobin7_grant) + default: begin + rhs_self41 = {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self42 = 1'd0; + case (roundrobin7_grant) + default: begin + rhs_self42 = soc_user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self43 = 1'd0; + case (roundrobin7_grant) + default: begin + rhs_self43 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +end +always @(*) begin + cases_self = 32'd0; + case (csr_data_width) + default: begin + cases_self = interface0_dat_w; + end + endcase +end +always @(*) begin + self0 = 3'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + self0 = soc_litedramcore_nop_ba; + end + 1'd1: begin + self0 = soc_litedramcore_choose_cmd_cmd_payload_ba; + end + 2'd2: begin + self0 = soc_litedramcore_choose_req_cmd_payload_ba; + end + default: begin + self0 = soc_litedramcore_cmd_payload_ba; + end + endcase +end +always @(*) begin + self1 = 15'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + self1 = soc_litedramcore_nop_a; + end + 1'd1: begin + self1 = soc_litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + self1 = soc_litedramcore_choose_req_cmd_payload_a; + end + default: begin + self1 = soc_litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + self2 = 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + self2 = 1'd0; + end + 1'd1: begin + self2 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + self2 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + end + default: begin + self2 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + self3 = 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + self3 = 1'd0; + end + 1'd1: begin + self3 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + self3 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + end + default: begin + self3 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + self4 = 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + self4 = 1'd0; + end + 1'd1: begin + self4 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + self4 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + end + default: begin + self4 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + self5 = 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + self5 = 1'd0; + end + 1'd1: begin + self5 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + self5 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + self5 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + self6 = 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + self6 = 1'd0; + end + 1'd1: begin + self6 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + self6 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + self6 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + self7 = 3'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + self7 = soc_litedramcore_nop_ba; + end + 1'd1: begin + self7 = soc_litedramcore_choose_cmd_cmd_payload_ba; + end + 2'd2: begin + self7 = soc_litedramcore_choose_req_cmd_payload_ba; + end + default: begin + self7 = soc_litedramcore_cmd_payload_ba; + end + endcase +end +always @(*) begin + self8 = 15'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + self8 = soc_litedramcore_nop_a; + end + 1'd1: begin + self8 = soc_litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + self8 = soc_litedramcore_choose_req_cmd_payload_a; + end + default: begin + self8 = soc_litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + self9 = 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + self9 = 1'd0; + end + 1'd1: begin + self9 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + self9 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + end + default: begin + self9 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + self10 = 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + self10 = 1'd0; + end + 1'd1: begin + self10 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + self10 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + end + default: begin + self10 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + self11 = 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + self11 = 1'd0; + end + 1'd1: begin + self11 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + self11 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + end + default: begin + self11 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + self12 = 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + self12 = 1'd0; + end + 1'd1: begin + self12 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + self12 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + self12 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + self13 = 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + self13 = 1'd0; + end + 1'd1: begin + self13 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + self13 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + self13 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + self14 = 3'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + self14 = soc_litedramcore_nop_ba; + end + 1'd1: begin + self14 = soc_litedramcore_choose_cmd_cmd_payload_ba; + end + 2'd2: begin + self14 = soc_litedramcore_choose_req_cmd_payload_ba; + end + default: begin + self14 = soc_litedramcore_cmd_payload_ba; + end + endcase +end +always @(*) begin + self15 = 15'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + self15 = soc_litedramcore_nop_a; + end + 1'd1: begin + self15 = soc_litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + self15 = soc_litedramcore_choose_req_cmd_payload_a; + end + default: begin + self15 = soc_litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + self16 = 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + self16 = 1'd0; + end + 1'd1: begin + self16 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + self16 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + end + default: begin + self16 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + self17 = 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + self17 = 1'd0; + end + 1'd1: begin + self17 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + self17 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + end + default: begin + self17 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + self18 = 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + self18 = 1'd0; + end + 1'd1: begin + self18 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + self18 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + end + default: begin + self18 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + self19 = 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + self19 = 1'd0; + end + 1'd1: begin + self19 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + self19 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + self19 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + self20 = 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + self20 = 1'd0; + end + 1'd1: begin + self20 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + self20 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + self20 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + self21 = 3'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + self21 = soc_litedramcore_nop_ba; + end + 1'd1: begin + self21 = soc_litedramcore_choose_cmd_cmd_payload_ba; + end + 2'd2: begin + self21 = soc_litedramcore_choose_req_cmd_payload_ba; + end + default: begin + self21 = soc_litedramcore_cmd_payload_ba; + end + endcase +end +always @(*) begin + self22 = 15'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + self22 = soc_litedramcore_nop_a; + end + 1'd1: begin + self22 = soc_litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + self22 = soc_litedramcore_choose_req_cmd_payload_a; + end + default: begin + self22 = soc_litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + self23 = 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + self23 = 1'd0; + end + 1'd1: begin + self23 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + self23 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + end + default: begin + self23 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + self24 = 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + self24 = 1'd0; + end + 1'd1: begin + self24 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + self24 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + end + default: begin + self24 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + self25 = 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + self25 = 1'd0; + end + 1'd1: begin + self25 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + self25 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + end + default: begin + self25 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + self26 = 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + self26 = 1'd0; + end + 1'd1: begin + self26 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + self26 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + self26 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + self27 = 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + self27 = 1'd0; + end + 1'd1: begin + self27 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + self27 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + self27 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + end + endcase +end + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge por_clk) begin + soc_int_rst <= 1'd0; +end + +always @(posedge sys_clk) begin + soc_user_enable <= (soc_init_done_storage & (~soc_init_error_storage)); + slaves <= master; + if (wait_1) begin + if ((~done)) begin + count <= (count - 1'd1); + end + end else begin + count <= 20'd1000000; + end + soc_ddrphy_new_bank_write0 <= soc_ddrphy_bank_write0; + soc_ddrphy_new_bank_write_col0 <= soc_ddrphy_bank_write_col0; + soc_ddrphy_new_bank_write1 <= soc_ddrphy_bank_write1; + soc_ddrphy_new_bank_write_col1 <= soc_ddrphy_bank_write_col1; + soc_ddrphy_new_bank_write2 <= soc_ddrphy_bank_write2; + soc_ddrphy_new_bank_write_col2 <= soc_ddrphy_bank_write_col2; + soc_ddrphy_new_bank_write3 <= soc_ddrphy_bank_write3; + soc_ddrphy_new_bank_write_col3 <= soc_ddrphy_bank_write_col3; + soc_ddrphy_new_bank_write4 <= soc_ddrphy_bank_write4; + soc_ddrphy_new_bank_write_col4 <= soc_ddrphy_bank_write_col4; + soc_ddrphy_new_bank_write5 <= soc_ddrphy_bank_write5; + soc_ddrphy_new_bank_write_col5 <= soc_ddrphy_bank_write_col5; + soc_ddrphy_new_bank_write6 <= soc_ddrphy_bank_write6; + soc_ddrphy_new_bank_write_col6 <= soc_ddrphy_bank_write_col6; + soc_ddrphy_new_bank_write7 <= soc_ddrphy_bank_write7; + soc_ddrphy_new_bank_write_col7 <= soc_ddrphy_bank_write_col7; + soc_ddrphy_new_banks_read0 <= soc_ddrphy_banks_read; + soc_ddrphy_new_banks_read_data0 <= soc_ddrphy_banks_read_data; + soc_ddrphy_new_banks_read1 <= soc_ddrphy_new_banks_read0; + soc_ddrphy_new_banks_read_data1 <= soc_ddrphy_new_banks_read_data0; + soc_ddrphy_new_banks_read2 <= soc_ddrphy_new_banks_read1; + soc_ddrphy_new_banks_read_data2 <= soc_ddrphy_new_banks_read_data1; + soc_ddrphy_new_banks_read3 <= soc_ddrphy_new_banks_read2; + soc_ddrphy_new_banks_read_data3 <= soc_ddrphy_new_banks_read_data2; + soc_ddrphy_new_banks_read4 <= soc_ddrphy_new_banks_read3; + soc_ddrphy_new_banks_read_data4 <= soc_ddrphy_new_banks_read_data3; + soc_ddrphy_new_banks_read5 <= soc_ddrphy_new_banks_read4; + soc_ddrphy_new_banks_read_data5 <= soc_ddrphy_new_banks_read_data4; + soc_ddrphy_new_banks_read6 <= soc_ddrphy_new_banks_read5; + soc_ddrphy_new_banks_read_data6 <= soc_ddrphy_new_banks_read_data5; + soc_ddrphy_new_banks_read7 <= soc_ddrphy_new_banks_read6; + soc_ddrphy_new_banks_read_data7 <= soc_ddrphy_new_banks_read_data6; + if (soc_ddrphy_bankmodel0_precharge) begin + soc_ddrphy_bankmodel0_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel0_activate) begin + soc_ddrphy_bankmodel0_active <= 1'd1; + soc_ddrphy_bankmodel0_row <= soc_ddrphy_bankmodel0_activate_row; + end + end + if (soc_ddrphy_bankmodel1_precharge) begin + soc_ddrphy_bankmodel1_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel1_activate) begin + soc_ddrphy_bankmodel1_active <= 1'd1; + soc_ddrphy_bankmodel1_row <= soc_ddrphy_bankmodel1_activate_row; + end + end + if (soc_ddrphy_bankmodel2_precharge) begin + soc_ddrphy_bankmodel2_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel2_activate) begin + soc_ddrphy_bankmodel2_active <= 1'd1; + soc_ddrphy_bankmodel2_row <= soc_ddrphy_bankmodel2_activate_row; + end + end + if (soc_ddrphy_bankmodel3_precharge) begin + soc_ddrphy_bankmodel3_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel3_activate) begin + soc_ddrphy_bankmodel3_active <= 1'd1; + soc_ddrphy_bankmodel3_row <= soc_ddrphy_bankmodel3_activate_row; + end + end + if (soc_ddrphy_bankmodel4_precharge) begin + soc_ddrphy_bankmodel4_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel4_activate) begin + soc_ddrphy_bankmodel4_active <= 1'd1; + soc_ddrphy_bankmodel4_row <= soc_ddrphy_bankmodel4_activate_row; + end + end + if (soc_ddrphy_bankmodel5_precharge) begin + soc_ddrphy_bankmodel5_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel5_activate) begin + soc_ddrphy_bankmodel5_active <= 1'd1; + soc_ddrphy_bankmodel5_row <= soc_ddrphy_bankmodel5_activate_row; + end + end + if (soc_ddrphy_bankmodel6_precharge) begin + soc_ddrphy_bankmodel6_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel6_activate) begin + soc_ddrphy_bankmodel6_active <= 1'd1; + soc_ddrphy_bankmodel6_row <= soc_ddrphy_bankmodel6_activate_row; + end + end + if (soc_ddrphy_bankmodel7_precharge) begin + soc_ddrphy_bankmodel7_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel7_activate) begin + soc_ddrphy_bankmodel7_active <= 1'd1; + soc_ddrphy_bankmodel7_row <= soc_ddrphy_bankmodel7_activate_row; + end + end + if (soc_litedramcore_csr_dfi_p0_rddata_valid) begin + soc_litedramcore_phaseinjector0_rddata_status <= soc_litedramcore_csr_dfi_p0_rddata; + end + if (soc_litedramcore_csr_dfi_p1_rddata_valid) begin + soc_litedramcore_phaseinjector1_rddata_status <= soc_litedramcore_csr_dfi_p1_rddata; + end + if (soc_litedramcore_csr_dfi_p2_rddata_valid) begin + soc_litedramcore_phaseinjector2_rddata_status <= soc_litedramcore_csr_dfi_p2_rddata; + end + if (soc_litedramcore_csr_dfi_p3_rddata_valid) begin + soc_litedramcore_phaseinjector3_rddata_status <= soc_litedramcore_csr_dfi_p3_rddata; + end + if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin + soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1); + end else begin + soc_litedramcore_timer_count1 <= 10'd585; + end + soc_litedramcore_postponer_req_o <= 1'd0; + if (soc_litedramcore_postponer_req_i) begin + soc_litedramcore_postponer_count <= (soc_litedramcore_postponer_count - 1'd1); + if ((soc_litedramcore_postponer_count == 1'd0)) begin + soc_litedramcore_postponer_count <= 1'd0; + soc_litedramcore_postponer_req_o <= 1'd1; + end + end + if (soc_litedramcore_sequencer_start0) begin + soc_litedramcore_sequencer_count <= 1'd0; + end else begin + if (soc_litedramcore_sequencer_done1) begin + if ((soc_litedramcore_sequencer_count != 1'd0)) begin + soc_litedramcore_sequencer_count <= (soc_litedramcore_sequencer_count - 1'd1); + end + end + end + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_sequencer_done1 <= 1'd0; + if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_trigger == 1'd0))) begin + soc_litedramcore_cmd_payload_a <= 11'h400; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd1; + soc_litedramcore_cmd_payload_we <= 1'd1; + end + if ((soc_litedramcore_sequencer_trigger == 2'd2)) begin + soc_litedramcore_cmd_payload_a <= 11'h400; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd1; + soc_litedramcore_cmd_payload_ras <= 1'd1; + soc_litedramcore_cmd_payload_we <= 1'd0; + end + if ((soc_litedramcore_sequencer_trigger == 6'd54)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_sequencer_done1 <= 1'd1; + end + if ((soc_litedramcore_sequencer_trigger == 6'd54)) begin + soc_litedramcore_sequencer_trigger <= 1'd0; + end else begin + if ((soc_litedramcore_sequencer_trigger != 1'd0)) begin + soc_litedramcore_sequencer_trigger <= (soc_litedramcore_sequencer_trigger + 1'd1); + end else begin + if (soc_litedramcore_sequencer_start1) begin + soc_litedramcore_sequencer_trigger <= 1'd1; + end + end + end + if ((soc_litedramcore_zqcs_timer_wait & (~soc_litedramcore_zqcs_timer_done0))) begin + soc_litedramcore_zqcs_timer_count1 <= (soc_litedramcore_zqcs_timer_count1 - 1'd1); + end else begin + soc_litedramcore_zqcs_timer_count1 <= 27'd74999999; + end + soc_litedramcore_zqcs_executer_done <= 1'd0; + if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_trigger == 1'd0))) begin + soc_litedramcore_cmd_payload_a <= 11'h400; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd1; + soc_litedramcore_cmd_payload_we <= 1'd1; + end + if ((soc_litedramcore_zqcs_executer_trigger == 2'd2)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd1; + end + if ((soc_litedramcore_zqcs_executer_trigger == 5'd18)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_zqcs_executer_done <= 1'd1; + end + if ((soc_litedramcore_zqcs_executer_trigger == 5'd18)) begin + soc_litedramcore_zqcs_executer_trigger <= 1'd0; + end else begin + if ((soc_litedramcore_zqcs_executer_trigger != 1'd0)) begin + soc_litedramcore_zqcs_executer_trigger <= (soc_litedramcore_zqcs_executer_trigger + 1'd1); + end else begin + if (soc_litedramcore_zqcs_executer_start) begin + soc_litedramcore_zqcs_executer_trigger <= 1'd1; + end + end + end + refresher_state <= refresher_next_state; + if (soc_litedramcore_bankmachine0_row_close) begin + soc_litedramcore_bankmachine0_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine0_row_open) begin + soc_litedramcore_bankmachine0_row_opened <= 1'd1; + soc_litedramcore_bankmachine0_row <= soc_litedramcore_bankmachine0_source_source_payload_addr[21:7]; + end + end + if (((soc_litedramcore_bankmachine0_syncfifo0_we & soc_litedramcore_bankmachine0_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_replace))) begin + soc_litedramcore_bankmachine0_produce <= (soc_litedramcore_bankmachine0_produce + 1'd1); + end + if (soc_litedramcore_bankmachine0_do_read) begin + soc_litedramcore_bankmachine0_consume <= (soc_litedramcore_bankmachine0_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine0_syncfifo0_we & soc_litedramcore_bankmachine0_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_replace))) begin + if ((~soc_litedramcore_bankmachine0_do_read)) begin + soc_litedramcore_bankmachine0_level <= (soc_litedramcore_bankmachine0_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine0_do_read) begin + soc_litedramcore_bankmachine0_level <= (soc_litedramcore_bankmachine0_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine0_pipe_valid_source_valid) | soc_litedramcore_bankmachine0_pipe_valid_source_ready)) begin + soc_litedramcore_bankmachine0_pipe_valid_source_valid <= soc_litedramcore_bankmachine0_pipe_valid_sink_valid; + soc_litedramcore_bankmachine0_pipe_valid_source_first <= soc_litedramcore_bankmachine0_pipe_valid_sink_first; + soc_litedramcore_bankmachine0_pipe_valid_source_last <= soc_litedramcore_bankmachine0_pipe_valid_sink_last; + soc_litedramcore_bankmachine0_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine0_pipe_valid_sink_payload_we; + soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine0_pipe_valid_sink_payload_addr; + end + if (soc_litedramcore_bankmachine0_twtpcon_valid) begin + soc_litedramcore_bankmachine0_twtpcon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine0_twtpcon_ready)) begin + soc_litedramcore_bankmachine0_twtpcon_count <= (soc_litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine0_trccon_valid) begin + soc_litedramcore_bankmachine0_trccon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine0_trccon_ready)) begin + soc_litedramcore_bankmachine0_trccon_count <= (soc_litedramcore_bankmachine0_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine0_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine0_trascon_valid) begin + soc_litedramcore_bankmachine0_trascon_count <= 2'd3; + if (1'd0) begin + soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_trascon_count <= (soc_litedramcore_bankmachine0_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine0_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; + end + end + end + bankmachine0_state <= bankmachine0_next_state; + if (soc_litedramcore_bankmachine1_row_close) begin + soc_litedramcore_bankmachine1_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine1_row_open) begin + soc_litedramcore_bankmachine1_row_opened <= 1'd1; + soc_litedramcore_bankmachine1_row <= soc_litedramcore_bankmachine1_source_source_payload_addr[21:7]; + end + end + if (((soc_litedramcore_bankmachine1_syncfifo1_we & soc_litedramcore_bankmachine1_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_replace))) begin + soc_litedramcore_bankmachine1_produce <= (soc_litedramcore_bankmachine1_produce + 1'd1); + end + if (soc_litedramcore_bankmachine1_do_read) begin + soc_litedramcore_bankmachine1_consume <= (soc_litedramcore_bankmachine1_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine1_syncfifo1_we & soc_litedramcore_bankmachine1_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_replace))) begin + if ((~soc_litedramcore_bankmachine1_do_read)) begin + soc_litedramcore_bankmachine1_level <= (soc_litedramcore_bankmachine1_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine1_do_read) begin + soc_litedramcore_bankmachine1_level <= (soc_litedramcore_bankmachine1_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine1_pipe_valid_source_valid) | soc_litedramcore_bankmachine1_pipe_valid_source_ready)) begin + soc_litedramcore_bankmachine1_pipe_valid_source_valid <= soc_litedramcore_bankmachine1_pipe_valid_sink_valid; + soc_litedramcore_bankmachine1_pipe_valid_source_first <= soc_litedramcore_bankmachine1_pipe_valid_sink_first; + soc_litedramcore_bankmachine1_pipe_valid_source_last <= soc_litedramcore_bankmachine1_pipe_valid_sink_last; + soc_litedramcore_bankmachine1_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine1_pipe_valid_sink_payload_we; + soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine1_pipe_valid_sink_payload_addr; + end + if (soc_litedramcore_bankmachine1_twtpcon_valid) begin + soc_litedramcore_bankmachine1_twtpcon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine1_twtpcon_ready)) begin + soc_litedramcore_bankmachine1_twtpcon_count <= (soc_litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine1_trccon_valid) begin + soc_litedramcore_bankmachine1_trccon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine1_trccon_ready)) begin + soc_litedramcore_bankmachine1_trccon_count <= (soc_litedramcore_bankmachine1_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine1_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine1_trascon_valid) begin + soc_litedramcore_bankmachine1_trascon_count <= 2'd3; + if (1'd0) begin + soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_trascon_count <= (soc_litedramcore_bankmachine1_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine1_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; + end + end + end + bankmachine1_state <= bankmachine1_next_state; + if (soc_litedramcore_bankmachine2_row_close) begin + soc_litedramcore_bankmachine2_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine2_row_open) begin + soc_litedramcore_bankmachine2_row_opened <= 1'd1; + soc_litedramcore_bankmachine2_row <= soc_litedramcore_bankmachine2_source_source_payload_addr[21:7]; + end + end + if (((soc_litedramcore_bankmachine2_syncfifo2_we & soc_litedramcore_bankmachine2_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_replace))) begin + soc_litedramcore_bankmachine2_produce <= (soc_litedramcore_bankmachine2_produce + 1'd1); + end + if (soc_litedramcore_bankmachine2_do_read) begin + soc_litedramcore_bankmachine2_consume <= (soc_litedramcore_bankmachine2_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine2_syncfifo2_we & soc_litedramcore_bankmachine2_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_replace))) begin + if ((~soc_litedramcore_bankmachine2_do_read)) begin + soc_litedramcore_bankmachine2_level <= (soc_litedramcore_bankmachine2_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine2_do_read) begin + soc_litedramcore_bankmachine2_level <= (soc_litedramcore_bankmachine2_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine2_pipe_valid_source_valid) | soc_litedramcore_bankmachine2_pipe_valid_source_ready)) begin + soc_litedramcore_bankmachine2_pipe_valid_source_valid <= soc_litedramcore_bankmachine2_pipe_valid_sink_valid; + soc_litedramcore_bankmachine2_pipe_valid_source_first <= soc_litedramcore_bankmachine2_pipe_valid_sink_first; + soc_litedramcore_bankmachine2_pipe_valid_source_last <= soc_litedramcore_bankmachine2_pipe_valid_sink_last; + soc_litedramcore_bankmachine2_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine2_pipe_valid_sink_payload_we; + soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine2_pipe_valid_sink_payload_addr; + end + if (soc_litedramcore_bankmachine2_twtpcon_valid) begin + soc_litedramcore_bankmachine2_twtpcon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine2_twtpcon_ready)) begin + soc_litedramcore_bankmachine2_twtpcon_count <= (soc_litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine2_trccon_valid) begin + soc_litedramcore_bankmachine2_trccon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine2_trccon_ready)) begin + soc_litedramcore_bankmachine2_trccon_count <= (soc_litedramcore_bankmachine2_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine2_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine2_trascon_valid) begin + soc_litedramcore_bankmachine2_trascon_count <= 2'd3; + if (1'd0) begin + soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_trascon_count <= (soc_litedramcore_bankmachine2_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine2_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; + end + end + end + bankmachine2_state <= bankmachine2_next_state; + if (soc_litedramcore_bankmachine3_row_close) begin + soc_litedramcore_bankmachine3_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine3_row_open) begin + soc_litedramcore_bankmachine3_row_opened <= 1'd1; + soc_litedramcore_bankmachine3_row <= soc_litedramcore_bankmachine3_source_source_payload_addr[21:7]; + end + end + if (((soc_litedramcore_bankmachine3_syncfifo3_we & soc_litedramcore_bankmachine3_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_replace))) begin + soc_litedramcore_bankmachine3_produce <= (soc_litedramcore_bankmachine3_produce + 1'd1); + end + if (soc_litedramcore_bankmachine3_do_read) begin + soc_litedramcore_bankmachine3_consume <= (soc_litedramcore_bankmachine3_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine3_syncfifo3_we & soc_litedramcore_bankmachine3_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_replace))) begin + if ((~soc_litedramcore_bankmachine3_do_read)) begin + soc_litedramcore_bankmachine3_level <= (soc_litedramcore_bankmachine3_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine3_do_read) begin + soc_litedramcore_bankmachine3_level <= (soc_litedramcore_bankmachine3_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine3_pipe_valid_source_valid) | soc_litedramcore_bankmachine3_pipe_valid_source_ready)) begin + soc_litedramcore_bankmachine3_pipe_valid_source_valid <= soc_litedramcore_bankmachine3_pipe_valid_sink_valid; + soc_litedramcore_bankmachine3_pipe_valid_source_first <= soc_litedramcore_bankmachine3_pipe_valid_sink_first; + soc_litedramcore_bankmachine3_pipe_valid_source_last <= soc_litedramcore_bankmachine3_pipe_valid_sink_last; + soc_litedramcore_bankmachine3_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine3_pipe_valid_sink_payload_we; + soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine3_pipe_valid_sink_payload_addr; + end + if (soc_litedramcore_bankmachine3_twtpcon_valid) begin + soc_litedramcore_bankmachine3_twtpcon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine3_twtpcon_ready)) begin + soc_litedramcore_bankmachine3_twtpcon_count <= (soc_litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine3_trccon_valid) begin + soc_litedramcore_bankmachine3_trccon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine3_trccon_ready)) begin + soc_litedramcore_bankmachine3_trccon_count <= (soc_litedramcore_bankmachine3_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine3_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine3_trascon_valid) begin + soc_litedramcore_bankmachine3_trascon_count <= 2'd3; + if (1'd0) begin + soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_trascon_count <= (soc_litedramcore_bankmachine3_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine3_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; + end + end + end + bankmachine3_state <= bankmachine3_next_state; + if (soc_litedramcore_bankmachine4_row_close) begin + soc_litedramcore_bankmachine4_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine4_row_open) begin + soc_litedramcore_bankmachine4_row_opened <= 1'd1; + soc_litedramcore_bankmachine4_row <= soc_litedramcore_bankmachine4_source_source_payload_addr[21:7]; + end + end + if (((soc_litedramcore_bankmachine4_syncfifo4_we & soc_litedramcore_bankmachine4_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_replace))) begin + soc_litedramcore_bankmachine4_produce <= (soc_litedramcore_bankmachine4_produce + 1'd1); + end + if (soc_litedramcore_bankmachine4_do_read) begin + soc_litedramcore_bankmachine4_consume <= (soc_litedramcore_bankmachine4_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine4_syncfifo4_we & soc_litedramcore_bankmachine4_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_replace))) begin + if ((~soc_litedramcore_bankmachine4_do_read)) begin + soc_litedramcore_bankmachine4_level <= (soc_litedramcore_bankmachine4_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine4_do_read) begin + soc_litedramcore_bankmachine4_level <= (soc_litedramcore_bankmachine4_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine4_pipe_valid_source_valid) | soc_litedramcore_bankmachine4_pipe_valid_source_ready)) begin + soc_litedramcore_bankmachine4_pipe_valid_source_valid <= soc_litedramcore_bankmachine4_pipe_valid_sink_valid; + soc_litedramcore_bankmachine4_pipe_valid_source_first <= soc_litedramcore_bankmachine4_pipe_valid_sink_first; + soc_litedramcore_bankmachine4_pipe_valid_source_last <= soc_litedramcore_bankmachine4_pipe_valid_sink_last; + soc_litedramcore_bankmachine4_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine4_pipe_valid_sink_payload_we; + soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine4_pipe_valid_sink_payload_addr; + end + if (soc_litedramcore_bankmachine4_twtpcon_valid) begin + soc_litedramcore_bankmachine4_twtpcon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine4_twtpcon_ready)) begin + soc_litedramcore_bankmachine4_twtpcon_count <= (soc_litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine4_trccon_valid) begin + soc_litedramcore_bankmachine4_trccon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine4_trccon_ready)) begin + soc_litedramcore_bankmachine4_trccon_count <= (soc_litedramcore_bankmachine4_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine4_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine4_trascon_valid) begin + soc_litedramcore_bankmachine4_trascon_count <= 2'd3; + if (1'd0) begin + soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_trascon_count <= (soc_litedramcore_bankmachine4_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine4_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; + end + end + end + bankmachine4_state <= bankmachine4_next_state; + if (soc_litedramcore_bankmachine5_row_close) begin + soc_litedramcore_bankmachine5_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine5_row_open) begin + soc_litedramcore_bankmachine5_row_opened <= 1'd1; + soc_litedramcore_bankmachine5_row <= soc_litedramcore_bankmachine5_source_source_payload_addr[21:7]; + end + end + if (((soc_litedramcore_bankmachine5_syncfifo5_we & soc_litedramcore_bankmachine5_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_replace))) begin + soc_litedramcore_bankmachine5_produce <= (soc_litedramcore_bankmachine5_produce + 1'd1); + end + if (soc_litedramcore_bankmachine5_do_read) begin + soc_litedramcore_bankmachine5_consume <= (soc_litedramcore_bankmachine5_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine5_syncfifo5_we & soc_litedramcore_bankmachine5_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_replace))) begin + if ((~soc_litedramcore_bankmachine5_do_read)) begin + soc_litedramcore_bankmachine5_level <= (soc_litedramcore_bankmachine5_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine5_do_read) begin + soc_litedramcore_bankmachine5_level <= (soc_litedramcore_bankmachine5_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine5_pipe_valid_source_valid) | soc_litedramcore_bankmachine5_pipe_valid_source_ready)) begin + soc_litedramcore_bankmachine5_pipe_valid_source_valid <= soc_litedramcore_bankmachine5_pipe_valid_sink_valid; + soc_litedramcore_bankmachine5_pipe_valid_source_first <= soc_litedramcore_bankmachine5_pipe_valid_sink_first; + soc_litedramcore_bankmachine5_pipe_valid_source_last <= soc_litedramcore_bankmachine5_pipe_valid_sink_last; + soc_litedramcore_bankmachine5_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine5_pipe_valid_sink_payload_we; + soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine5_pipe_valid_sink_payload_addr; + end + if (soc_litedramcore_bankmachine5_twtpcon_valid) begin + soc_litedramcore_bankmachine5_twtpcon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine5_twtpcon_ready)) begin + soc_litedramcore_bankmachine5_twtpcon_count <= (soc_litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine5_trccon_valid) begin + soc_litedramcore_bankmachine5_trccon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine5_trccon_ready)) begin + soc_litedramcore_bankmachine5_trccon_count <= (soc_litedramcore_bankmachine5_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine5_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine5_trascon_valid) begin + soc_litedramcore_bankmachine5_trascon_count <= 2'd3; + if (1'd0) begin + soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_trascon_count <= (soc_litedramcore_bankmachine5_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine5_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; + end + end + end + bankmachine5_state <= bankmachine5_next_state; + if (soc_litedramcore_bankmachine6_row_close) begin + soc_litedramcore_bankmachine6_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine6_row_open) begin + soc_litedramcore_bankmachine6_row_opened <= 1'd1; + soc_litedramcore_bankmachine6_row <= soc_litedramcore_bankmachine6_source_source_payload_addr[21:7]; + end + end + if (((soc_litedramcore_bankmachine6_syncfifo6_we & soc_litedramcore_bankmachine6_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_replace))) begin + soc_litedramcore_bankmachine6_produce <= (soc_litedramcore_bankmachine6_produce + 1'd1); + end + if (soc_litedramcore_bankmachine6_do_read) begin + soc_litedramcore_bankmachine6_consume <= (soc_litedramcore_bankmachine6_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine6_syncfifo6_we & soc_litedramcore_bankmachine6_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_replace))) begin + if ((~soc_litedramcore_bankmachine6_do_read)) begin + soc_litedramcore_bankmachine6_level <= (soc_litedramcore_bankmachine6_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine6_do_read) begin + soc_litedramcore_bankmachine6_level <= (soc_litedramcore_bankmachine6_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine6_pipe_valid_source_valid) | soc_litedramcore_bankmachine6_pipe_valid_source_ready)) begin + soc_litedramcore_bankmachine6_pipe_valid_source_valid <= soc_litedramcore_bankmachine6_pipe_valid_sink_valid; + soc_litedramcore_bankmachine6_pipe_valid_source_first <= soc_litedramcore_bankmachine6_pipe_valid_sink_first; + soc_litedramcore_bankmachine6_pipe_valid_source_last <= soc_litedramcore_bankmachine6_pipe_valid_sink_last; + soc_litedramcore_bankmachine6_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we; + soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine6_pipe_valid_sink_payload_addr; + end + if (soc_litedramcore_bankmachine6_twtpcon_valid) begin + soc_litedramcore_bankmachine6_twtpcon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine6_twtpcon_ready)) begin + soc_litedramcore_bankmachine6_twtpcon_count <= (soc_litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine6_trccon_valid) begin + soc_litedramcore_bankmachine6_trccon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine6_trccon_ready)) begin + soc_litedramcore_bankmachine6_trccon_count <= (soc_litedramcore_bankmachine6_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine6_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine6_trascon_valid) begin + soc_litedramcore_bankmachine6_trascon_count <= 2'd3; + if (1'd0) begin + soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_trascon_count <= (soc_litedramcore_bankmachine6_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine6_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; + end + end + end + bankmachine6_state <= bankmachine6_next_state; + if (soc_litedramcore_bankmachine7_row_close) begin + soc_litedramcore_bankmachine7_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine7_row_open) begin + soc_litedramcore_bankmachine7_row_opened <= 1'd1; + soc_litedramcore_bankmachine7_row <= soc_litedramcore_bankmachine7_source_source_payload_addr[21:7]; + end + end + if (((soc_litedramcore_bankmachine7_syncfifo7_we & soc_litedramcore_bankmachine7_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_replace))) begin + soc_litedramcore_bankmachine7_produce <= (soc_litedramcore_bankmachine7_produce + 1'd1); + end + if (soc_litedramcore_bankmachine7_do_read) begin + soc_litedramcore_bankmachine7_consume <= (soc_litedramcore_bankmachine7_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine7_syncfifo7_we & soc_litedramcore_bankmachine7_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_replace))) begin + if ((~soc_litedramcore_bankmachine7_do_read)) begin + soc_litedramcore_bankmachine7_level <= (soc_litedramcore_bankmachine7_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine7_do_read) begin + soc_litedramcore_bankmachine7_level <= (soc_litedramcore_bankmachine7_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine7_pipe_valid_source_valid) | soc_litedramcore_bankmachine7_pipe_valid_source_ready)) begin + soc_litedramcore_bankmachine7_pipe_valid_source_valid <= soc_litedramcore_bankmachine7_pipe_valid_sink_valid; + soc_litedramcore_bankmachine7_pipe_valid_source_first <= soc_litedramcore_bankmachine7_pipe_valid_sink_first; + soc_litedramcore_bankmachine7_pipe_valid_source_last <= soc_litedramcore_bankmachine7_pipe_valid_sink_last; + soc_litedramcore_bankmachine7_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine7_pipe_valid_sink_payload_we; + soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine7_pipe_valid_sink_payload_addr; + end + if (soc_litedramcore_bankmachine7_twtpcon_valid) begin + soc_litedramcore_bankmachine7_twtpcon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine7_twtpcon_ready)) begin + soc_litedramcore_bankmachine7_twtpcon_count <= (soc_litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine7_trccon_valid) begin + soc_litedramcore_bankmachine7_trccon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine7_trccon_ready)) begin + soc_litedramcore_bankmachine7_trccon_count <= (soc_litedramcore_bankmachine7_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine7_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine7_trascon_valid) begin + soc_litedramcore_bankmachine7_trascon_count <= 2'd3; + if (1'd0) begin + soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_trascon_count <= (soc_litedramcore_bankmachine7_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine7_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; + end + end + end + bankmachine7_state <= bankmachine7_next_state; + if ((~soc_litedramcore_en0)) begin + soc_litedramcore_time0 <= 5'd31; + end else begin + if ((~soc_litedramcore_max_time0)) begin + soc_litedramcore_time0 <= (soc_litedramcore_time0 - 1'd1); + end + end + if ((~soc_litedramcore_en1)) begin + soc_litedramcore_time1 <= 4'd15; + end else begin + if ((~soc_litedramcore_max_time1)) begin + soc_litedramcore_time1 <= (soc_litedramcore_time1 - 1'd1); + end + end + if (soc_litedramcore_choose_cmd_ce) begin + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (soc_litedramcore_choose_req_ce) begin + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + soc_litedramcore_dfi_p0_cs_n <= 1'd0; + soc_litedramcore_dfi_p0_bank <= self0; + soc_litedramcore_dfi_p0_address <= self1; + soc_litedramcore_dfi_p0_cas_n <= (~self2); + soc_litedramcore_dfi_p0_ras_n <= (~self3); + soc_litedramcore_dfi_p0_we_n <= (~self4); + soc_litedramcore_dfi_p0_rddata_en <= self5; + soc_litedramcore_dfi_p0_wrdata_en <= self6; + soc_litedramcore_dfi_p1_cs_n <= 1'd0; + soc_litedramcore_dfi_p1_bank <= self7; + soc_litedramcore_dfi_p1_address <= self8; + soc_litedramcore_dfi_p1_cas_n <= (~self9); + soc_litedramcore_dfi_p1_ras_n <= (~self10); + soc_litedramcore_dfi_p1_we_n <= (~self11); + soc_litedramcore_dfi_p1_rddata_en <= self12; + soc_litedramcore_dfi_p1_wrdata_en <= self13; + soc_litedramcore_dfi_p2_cs_n <= 1'd0; + soc_litedramcore_dfi_p2_bank <= self14; + soc_litedramcore_dfi_p2_address <= self15; + soc_litedramcore_dfi_p2_cas_n <= (~self16); + soc_litedramcore_dfi_p2_ras_n <= (~self17); + soc_litedramcore_dfi_p2_we_n <= (~self18); + soc_litedramcore_dfi_p2_rddata_en <= self19; + soc_litedramcore_dfi_p2_wrdata_en <= self20; + soc_litedramcore_dfi_p3_cs_n <= 1'd0; + soc_litedramcore_dfi_p3_bank <= self21; + soc_litedramcore_dfi_p3_address <= self22; + soc_litedramcore_dfi_p3_cas_n <= (~self23); + soc_litedramcore_dfi_p3_ras_n <= (~self24); + soc_litedramcore_dfi_p3_we_n <= (~self25); + soc_litedramcore_dfi_p3_rddata_en <= self26; + soc_litedramcore_dfi_p3_wrdata_en <= self27; + if (soc_litedramcore_trrdcon_valid) begin + soc_litedramcore_trrdcon_count <= 1'd1; + if (1'd0) begin + soc_litedramcore_trrdcon_ready <= 1'd1; + end else begin + soc_litedramcore_trrdcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_trrdcon_ready)) begin + soc_litedramcore_trrdcon_count <= (soc_litedramcore_trrdcon_count - 1'd1); + if ((soc_litedramcore_trrdcon_count == 1'd1)) begin + soc_litedramcore_trrdcon_ready <= 1'd1; + end + end + end + soc_litedramcore_tfawcon_window <= {soc_litedramcore_tfawcon_window, soc_litedramcore_tfawcon_valid}; + if ((soc_litedramcore_tfawcon_count < 3'd4)) begin + if ((soc_litedramcore_tfawcon_count == 2'd3)) begin + soc_litedramcore_tfawcon_ready <= (~soc_litedramcore_tfawcon_valid); + end else begin + soc_litedramcore_tfawcon_ready <= 1'd1; + end + end + if (soc_litedramcore_tccdcon_valid) begin + soc_litedramcore_tccdcon_count <= 1'd0; + if (1'd1) begin + soc_litedramcore_tccdcon_ready <= 1'd1; + end else begin + soc_litedramcore_tccdcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_tccdcon_ready)) begin + soc_litedramcore_tccdcon_count <= (soc_litedramcore_tccdcon_count - 1'd1); + if ((soc_litedramcore_tccdcon_count == 1'd1)) begin + soc_litedramcore_tccdcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_twtrcon_valid) begin + soc_litedramcore_twtrcon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_twtrcon_ready <= 1'd1; + end else begin + soc_litedramcore_twtrcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_twtrcon_ready)) begin + soc_litedramcore_twtrcon_count <= (soc_litedramcore_twtrcon_count - 1'd1); + if ((soc_litedramcore_twtrcon_count == 1'd1)) begin + soc_litedramcore_twtrcon_ready <= 1'd1; + end + end + end + multiplexer_state <= multiplexer_next_state; + new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready)); + new_master_wdata_ready1 <= new_master_wdata_ready0; + new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid)); + new_master_rdata_valid1 <= new_master_rdata_valid0; + new_master_rdata_valid2 <= new_master_rdata_valid1; + new_master_rdata_valid3 <= new_master_rdata_valid2; + new_master_rdata_valid4 <= new_master_rdata_valid3; + new_master_rdata_valid5 <= new_master_rdata_valid4; + new_master_rdata_valid6 <= new_master_rdata_valid5; + new_master_rdata_valid7 <= new_master_rdata_valid6; + new_master_rdata_valid8 <= new_master_rdata_valid7; + state <= next_state; + if (interface1_dat_w_next_value_ce0) begin + interface1_dat_w <= interface1_dat_w_next_value0; + end + if (selected_r_next_value_ce1) begin + selected_r <= selected_r_next_value1; + end + if (interface1_adr_next_value_ce2) begin + interface1_adr <= interface1_adr_next_value2; + end + if (interface1_re_next_value_ce3) begin + interface1_re <= interface1_re_next_value3; + end + if (interface1_we_next_value_ce4) begin + interface1_we <= interface1_we_next_value4; + end + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) + 1'd0: begin + interface0_bank_bus_dat_r <= csrbank0_init_done_w; + end + 1'd1: begin + interface0_bank_bus_dat_r <= csrbank0_init_error_w; + end + endcase + end + if (csrbank0_init_done_re) begin + soc_init_done_storage <= csrbank0_init_done_r; + end + soc_init_done_wr_stb <= csrbank0_init_done_re; + if (csrbank0_init_error_re) begin + soc_init_error_storage <= csrbank0_init_error_r; + end + soc_init_error_wr_stb <= csrbank0_init_error_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= reserved_w; + end + endcase + end + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) + 1'd0: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_control_w; + end + 1'd1: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command_w; + end + 2'd2: begin + interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w; + end + 2'd3: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address_w; + end + 3'd4: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress_w; + end + 3'd5: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata_w; + end + 3'd6: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; + end + 3'd7: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command_w; + end + 4'd8: begin + interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w; + end + 4'd9: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address_w; + end + 4'd10: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress_w; + end + 4'd11: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata_w; + end + 4'd12: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; + end + 4'd13: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command_w; + end + 4'd14: begin + interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w; + end + 4'd15: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address_w; + end + 5'd16: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress_w; + end + 5'd17: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata_w; + end + 5'd18: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; + end + 5'd19: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command_w; + end + 5'd20: begin + interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w; + end + 5'd21: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address_w; + end + 5'd22: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress_w; + end + 5'd23: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata_w; + end + 5'd24: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; + end + endcase + end + if (csrbank2_dfii_control_re) begin + soc_litedramcore_storage <= csrbank2_dfii_control_r; + end + soc_litedramcore_wr_stb <= csrbank2_dfii_control_re; + if (csrbank2_dfii_pi0_command_re) begin + soc_litedramcore_phaseinjector0_command_storage <= csrbank2_dfii_pi0_command_r; + end + soc_litedramcore_phaseinjector0_command_wr_stb <= csrbank2_dfii_pi0_command_re; + if (csrbank2_dfii_pi0_address_re) begin + soc_litedramcore_phaseinjector0_address_storage <= csrbank2_dfii_pi0_address_r; + end + soc_litedramcore_phaseinjector0_address_wr_stb <= csrbank2_dfii_pi0_address_re; + if (csrbank2_dfii_pi0_baddress_re) begin + soc_litedramcore_phaseinjector0_baddress_storage <= csrbank2_dfii_pi0_baddress_r; + end + soc_litedramcore_phaseinjector0_baddress_wr_stb <= csrbank2_dfii_pi0_baddress_re; + if (csrbank2_dfii_pi0_wrdata_re) begin + soc_litedramcore_phaseinjector0_wrdata_storage <= csrbank2_dfii_pi0_wrdata_r; + end + soc_litedramcore_phaseinjector0_wrdata_wr_stb <= csrbank2_dfii_pi0_wrdata_re; + soc_litedramcore_phaseinjector0_rddata_wr_stb <= csrbank2_dfii_pi0_rddata_re; + if (csrbank2_dfii_pi1_command_re) begin + soc_litedramcore_phaseinjector1_command_storage <= csrbank2_dfii_pi1_command_r; + end + soc_litedramcore_phaseinjector1_command_wr_stb <= csrbank2_dfii_pi1_command_re; + if (csrbank2_dfii_pi1_address_re) begin + soc_litedramcore_phaseinjector1_address_storage <= csrbank2_dfii_pi1_address_r; + end + soc_litedramcore_phaseinjector1_address_wr_stb <= csrbank2_dfii_pi1_address_re; + if (csrbank2_dfii_pi1_baddress_re) begin + soc_litedramcore_phaseinjector1_baddress_storage <= csrbank2_dfii_pi1_baddress_r; + end + soc_litedramcore_phaseinjector1_baddress_wr_stb <= csrbank2_dfii_pi1_baddress_re; + if (csrbank2_dfii_pi1_wrdata_re) begin + soc_litedramcore_phaseinjector1_wrdata_storage <= csrbank2_dfii_pi1_wrdata_r; + end + soc_litedramcore_phaseinjector1_wrdata_wr_stb <= csrbank2_dfii_pi1_wrdata_re; + soc_litedramcore_phaseinjector1_rddata_wr_stb <= csrbank2_dfii_pi1_rddata_re; + if (csrbank2_dfii_pi2_command_re) begin + soc_litedramcore_phaseinjector2_command_storage <= csrbank2_dfii_pi2_command_r; + end + soc_litedramcore_phaseinjector2_command_wr_stb <= csrbank2_dfii_pi2_command_re; + if (csrbank2_dfii_pi2_address_re) begin + soc_litedramcore_phaseinjector2_address_storage <= csrbank2_dfii_pi2_address_r; + end + soc_litedramcore_phaseinjector2_address_wr_stb <= csrbank2_dfii_pi2_address_re; + if (csrbank2_dfii_pi2_baddress_re) begin + soc_litedramcore_phaseinjector2_baddress_storage <= csrbank2_dfii_pi2_baddress_r; + end + soc_litedramcore_phaseinjector2_baddress_wr_stb <= csrbank2_dfii_pi2_baddress_re; + if (csrbank2_dfii_pi2_wrdata_re) begin + soc_litedramcore_phaseinjector2_wrdata_storage <= csrbank2_dfii_pi2_wrdata_r; + end + soc_litedramcore_phaseinjector2_wrdata_wr_stb <= csrbank2_dfii_pi2_wrdata_re; + soc_litedramcore_phaseinjector2_rddata_wr_stb <= csrbank2_dfii_pi2_rddata_re; + if (csrbank2_dfii_pi3_command_re) begin + soc_litedramcore_phaseinjector3_command_storage <= csrbank2_dfii_pi3_command_r; + end + soc_litedramcore_phaseinjector3_command_wr_stb <= csrbank2_dfii_pi3_command_re; + if (csrbank2_dfii_pi3_address_re) begin + soc_litedramcore_phaseinjector3_address_storage <= csrbank2_dfii_pi3_address_r; + end + soc_litedramcore_phaseinjector3_address_wr_stb <= csrbank2_dfii_pi3_address_re; + if (csrbank2_dfii_pi3_baddress_re) begin + soc_litedramcore_phaseinjector3_baddress_storage <= csrbank2_dfii_pi3_baddress_r; + end + soc_litedramcore_phaseinjector3_baddress_wr_stb <= csrbank2_dfii_pi3_baddress_re; + if (csrbank2_dfii_pi3_wrdata_re) begin + soc_litedramcore_phaseinjector3_wrdata_storage <= csrbank2_dfii_pi3_wrdata_r; + end + soc_litedramcore_phaseinjector3_wrdata_wr_stb <= csrbank2_dfii_pi3_wrdata_re; + soc_litedramcore_phaseinjector3_rddata_wr_stb <= csrbank2_dfii_pi3_rddata_re; + if (sys_rst) begin + soc_ddrphy_bankmodel0_active <= 1'd0; + soc_ddrphy_bankmodel0_row <= 15'd0; + soc_ddrphy_bankmodel1_active <= 1'd0; + soc_ddrphy_bankmodel1_row <= 15'd0; + soc_ddrphy_bankmodel2_active <= 1'd0; + soc_ddrphy_bankmodel2_row <= 15'd0; + soc_ddrphy_bankmodel3_active <= 1'd0; + soc_ddrphy_bankmodel3_row <= 15'd0; + soc_ddrphy_bankmodel4_active <= 1'd0; + soc_ddrphy_bankmodel4_row <= 15'd0; + soc_ddrphy_bankmodel5_active <= 1'd0; + soc_ddrphy_bankmodel5_row <= 15'd0; + soc_ddrphy_bankmodel6_active <= 1'd0; + soc_ddrphy_bankmodel6_row <= 15'd0; + soc_ddrphy_bankmodel7_active <= 1'd0; + soc_ddrphy_bankmodel7_row <= 15'd0; + soc_ddrphy_new_bank_write0 <= 1'd0; + soc_ddrphy_new_bank_write_col0 <= 10'd0; + soc_ddrphy_new_bank_write1 <= 1'd0; + soc_ddrphy_new_bank_write_col1 <= 10'd0; + soc_ddrphy_new_bank_write2 <= 1'd0; + soc_ddrphy_new_bank_write_col2 <= 10'd0; + soc_ddrphy_new_bank_write3 <= 1'd0; + soc_ddrphy_new_bank_write_col3 <= 10'd0; + soc_ddrphy_new_bank_write4 <= 1'd0; + soc_ddrphy_new_bank_write_col4 <= 10'd0; + soc_ddrphy_new_bank_write5 <= 1'd0; + soc_ddrphy_new_bank_write_col5 <= 10'd0; + soc_ddrphy_new_bank_write6 <= 1'd0; + soc_ddrphy_new_bank_write_col6 <= 10'd0; + soc_ddrphy_new_bank_write7 <= 1'd0; + soc_ddrphy_new_bank_write_col7 <= 10'd0; + soc_ddrphy_new_banks_read0 <= 1'd0; + soc_ddrphy_new_banks_read_data0 <= 128'd0; + soc_ddrphy_new_banks_read1 <= 1'd0; + soc_ddrphy_new_banks_read_data1 <= 128'd0; + soc_ddrphy_new_banks_read2 <= 1'd0; + soc_ddrphy_new_banks_read_data2 <= 128'd0; + soc_ddrphy_new_banks_read3 <= 1'd0; + soc_ddrphy_new_banks_read_data3 <= 128'd0; + soc_ddrphy_new_banks_read4 <= 1'd0; + soc_ddrphy_new_banks_read_data4 <= 128'd0; + soc_ddrphy_new_banks_read5 <= 1'd0; + soc_ddrphy_new_banks_read_data5 <= 128'd0; + soc_ddrphy_new_banks_read6 <= 1'd0; + soc_ddrphy_new_banks_read_data6 <= 128'd0; + soc_ddrphy_new_banks_read7 <= 1'd0; + soc_ddrphy_new_banks_read_data7 <= 128'd0; + soc_litedramcore_storage <= 4'd1; + soc_litedramcore_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector0_command_storage <= 8'd0; + soc_litedramcore_phaseinjector0_command_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector0_address_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector0_baddress_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector0_wrdata_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector0_rddata_status <= 32'd0; + soc_litedramcore_phaseinjector0_rddata_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector1_command_storage <= 8'd0; + soc_litedramcore_phaseinjector1_command_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector1_address_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector1_baddress_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector1_wrdata_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector1_rddata_status <= 32'd0; + soc_litedramcore_phaseinjector1_rddata_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector2_command_storage <= 8'd0; + soc_litedramcore_phaseinjector2_command_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector2_address_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector2_baddress_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector2_wrdata_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector2_rddata_status <= 32'd0; + soc_litedramcore_phaseinjector2_rddata_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector3_command_storage <= 8'd0; + soc_litedramcore_phaseinjector3_command_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector3_address_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector3_baddress_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector3_wrdata_wr_stb <= 1'd0; + soc_litedramcore_phaseinjector3_rddata_status <= 32'd0; + soc_litedramcore_phaseinjector3_rddata_wr_stb <= 1'd0; + soc_litedramcore_dfi_p0_address <= 15'd0; + soc_litedramcore_dfi_p0_bank <= 3'd0; + soc_litedramcore_dfi_p0_cas_n <= 1'd1; + soc_litedramcore_dfi_p0_cs_n <= 1'd1; + soc_litedramcore_dfi_p0_ras_n <= 1'd1; + soc_litedramcore_dfi_p0_we_n <= 1'd1; + soc_litedramcore_dfi_p0_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p0_rddata_en <= 1'd0; + soc_litedramcore_dfi_p1_address <= 15'd0; + soc_litedramcore_dfi_p1_bank <= 3'd0; + soc_litedramcore_dfi_p1_cas_n <= 1'd1; + soc_litedramcore_dfi_p1_cs_n <= 1'd1; + soc_litedramcore_dfi_p1_ras_n <= 1'd1; + soc_litedramcore_dfi_p1_we_n <= 1'd1; + soc_litedramcore_dfi_p1_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p1_rddata_en <= 1'd0; + soc_litedramcore_dfi_p2_address <= 15'd0; + soc_litedramcore_dfi_p2_bank <= 3'd0; + soc_litedramcore_dfi_p2_cas_n <= 1'd1; + soc_litedramcore_dfi_p2_cs_n <= 1'd1; + soc_litedramcore_dfi_p2_ras_n <= 1'd1; + soc_litedramcore_dfi_p2_we_n <= 1'd1; + soc_litedramcore_dfi_p2_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p2_rddata_en <= 1'd0; + soc_litedramcore_dfi_p3_address <= 15'd0; + soc_litedramcore_dfi_p3_bank <= 3'd0; + soc_litedramcore_dfi_p3_cas_n <= 1'd1; + soc_litedramcore_dfi_p3_cs_n <= 1'd1; + soc_litedramcore_dfi_p3_ras_n <= 1'd1; + soc_litedramcore_dfi_p3_we_n <= 1'd1; + soc_litedramcore_dfi_p3_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p3_rddata_en <= 1'd0; + soc_litedramcore_timer_count1 <= 10'd585; + soc_litedramcore_postponer_req_o <= 1'd0; + soc_litedramcore_postponer_count <= 1'd0; + soc_litedramcore_sequencer_done1 <= 1'd0; + soc_litedramcore_sequencer_trigger <= 6'd0; + soc_litedramcore_sequencer_count <= 1'd0; + soc_litedramcore_zqcs_timer_count1 <= 27'd74999999; + soc_litedramcore_zqcs_executer_done <= 1'd0; + soc_litedramcore_zqcs_executer_trigger <= 5'd0; + soc_litedramcore_bankmachine0_level <= 4'd0; + soc_litedramcore_bankmachine0_produce <= 3'd0; + soc_litedramcore_bankmachine0_consume <= 3'd0; + soc_litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; + soc_litedramcore_bankmachine0_row <= 15'd0; + soc_litedramcore_bankmachine0_row_opened <= 1'd0; + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine0_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine0_trccon_count <= 3'd0; + soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine0_trascon_count <= 2'd0; + soc_litedramcore_bankmachine1_level <= 4'd0; + soc_litedramcore_bankmachine1_produce <= 3'd0; + soc_litedramcore_bankmachine1_consume <= 3'd0; + soc_litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; + soc_litedramcore_bankmachine1_row <= 15'd0; + soc_litedramcore_bankmachine1_row_opened <= 1'd0; + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine1_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine1_trccon_count <= 3'd0; + soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine1_trascon_count <= 2'd0; + soc_litedramcore_bankmachine2_level <= 4'd0; + soc_litedramcore_bankmachine2_produce <= 3'd0; + soc_litedramcore_bankmachine2_consume <= 3'd0; + soc_litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; + soc_litedramcore_bankmachine2_row <= 15'd0; + soc_litedramcore_bankmachine2_row_opened <= 1'd0; + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine2_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine2_trccon_count <= 3'd0; + soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine2_trascon_count <= 2'd0; + soc_litedramcore_bankmachine3_level <= 4'd0; + soc_litedramcore_bankmachine3_produce <= 3'd0; + soc_litedramcore_bankmachine3_consume <= 3'd0; + soc_litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; + soc_litedramcore_bankmachine3_row <= 15'd0; + soc_litedramcore_bankmachine3_row_opened <= 1'd0; + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine3_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine3_trccon_count <= 3'd0; + soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine3_trascon_count <= 2'd0; + soc_litedramcore_bankmachine4_level <= 4'd0; + soc_litedramcore_bankmachine4_produce <= 3'd0; + soc_litedramcore_bankmachine4_consume <= 3'd0; + soc_litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; + soc_litedramcore_bankmachine4_row <= 15'd0; + soc_litedramcore_bankmachine4_row_opened <= 1'd0; + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine4_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine4_trccon_count <= 3'd0; + soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine4_trascon_count <= 2'd0; + soc_litedramcore_bankmachine5_level <= 4'd0; + soc_litedramcore_bankmachine5_produce <= 3'd0; + soc_litedramcore_bankmachine5_consume <= 3'd0; + soc_litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; + soc_litedramcore_bankmachine5_row <= 15'd0; + soc_litedramcore_bankmachine5_row_opened <= 1'd0; + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine5_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine5_trccon_count <= 3'd0; + soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine5_trascon_count <= 2'd0; + soc_litedramcore_bankmachine6_level <= 4'd0; + soc_litedramcore_bankmachine6_produce <= 3'd0; + soc_litedramcore_bankmachine6_consume <= 3'd0; + soc_litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; + soc_litedramcore_bankmachine6_row <= 15'd0; + soc_litedramcore_bankmachine6_row_opened <= 1'd0; + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine6_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine6_trccon_count <= 3'd0; + soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine6_trascon_count <= 2'd0; + soc_litedramcore_bankmachine7_level <= 4'd0; + soc_litedramcore_bankmachine7_produce <= 3'd0; + soc_litedramcore_bankmachine7_consume <= 3'd0; + soc_litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; + soc_litedramcore_bankmachine7_row <= 15'd0; + soc_litedramcore_bankmachine7_row_opened <= 1'd0; + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine7_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine7_trccon_count <= 3'd0; + soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine7_trascon_count <= 2'd0; + soc_litedramcore_choose_cmd_grant <= 3'd0; + soc_litedramcore_choose_req_grant <= 3'd0; + soc_litedramcore_trrdcon_ready <= 1'd0; + soc_litedramcore_trrdcon_count <= 1'd0; + soc_litedramcore_tfawcon_ready <= 1'd1; + soc_litedramcore_tfawcon_window <= 4'd0; + soc_litedramcore_tccdcon_ready <= 1'd0; + soc_litedramcore_tccdcon_count <= 1'd0; + soc_litedramcore_twtrcon_ready <= 1'd0; + soc_litedramcore_twtrcon_count <= 3'd0; + soc_litedramcore_time0 <= 5'd0; + soc_litedramcore_time1 <= 4'd0; + soc_init_done_storage <= 1'd0; + soc_init_done_wr_stb <= 1'd0; + soc_init_error_storage <= 1'd0; + soc_init_error_wr_stb <= 1'd0; + soc_user_enable <= 1'd0; + interface1_re <= 1'd0; + interface1_we <= 1'd0; + selected_r <= 1'd0; + slaves <= 1'd0; + count <= 20'd1000000; + refresher_state <= 2'd0; + bankmachine0_state <= 3'd0; + bankmachine1_state <= 3'd0; + bankmachine2_state <= 3'd0; + bankmachine3_state <= 3'd0; + bankmachine4_state <= 3'd0; + bankmachine5_state <= 3'd0; + bankmachine6_state <= 3'd0; + bankmachine7_state <= 3'd0; + multiplexer_state <= 4'd0; + new_master_wdata_ready0 <= 1'd0; + new_master_wdata_ready1 <= 1'd0; + new_master_rdata_valid0 <= 1'd0; + new_master_rdata_valid1 <= 1'd0; + new_master_rdata_valid2 <= 1'd0; + new_master_rdata_valid3 <= 1'd0; + new_master_rdata_valid4 <= 1'd0; + new_master_rdata_valid5 <= 1'd0; + new_master_rdata_valid6 <= 1'd0; + new_master_rdata_valid7 <= 1'd0; + new_master_rdata_valid8 <= 1'd0; + state <= 2'd0; + end +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Memory mem: 4194304-words x 128-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +// Port 1 | Read: Async | Write: ---- | +reg [127:0] mem[0:4194303]; +reg [21:0] mem_adr0; +always @(posedge sys_clk) begin : mem_write_block + integer we_index; + for(we_index = 0; we_index < 16; we_index=we_index+1) + if (soc_ddrphy_bankmodel0_write_port_we[we_index]) + mem[soc_ddrphy_bankmodel0_write_port_adr][we_index*8 +: 8] <= soc_ddrphy_bankmodel0_write_port_dat_w[we_index*8 +: 8]; + mem_adr0 <= soc_ddrphy_bankmodel0_write_port_adr; +end +always @(posedge sys_clk) begin +end +assign soc_ddrphy_bankmodel0_write_port_dat_r = mem[mem_adr0]; +assign soc_ddrphy_bankmodel0_read_port_dat_r = mem[soc_ddrphy_bankmodel0_read_port_adr]; + + +//------------------------------------------------------------------------------ +// Memory mem_1: 4194304-words x 128-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +// Port 1 | Read: Async | Write: ---- | +reg [127:0] mem_1[0:4194303]; +reg [21:0] mem_1_adr0; +always @(posedge sys_clk) begin : mem_write_block_1 + integer we_index_1; + for(we_index_1 = 0; we_index_1 < 16; we_index_1=we_index_1+1) + if (soc_ddrphy_bankmodel1_write_port_we[we_index_1]) + mem_1[soc_ddrphy_bankmodel1_write_port_adr][we_index_1*8 +: 8] <= soc_ddrphy_bankmodel1_write_port_dat_w[we_index_1*8 +: 8]; + mem_1_adr0 <= soc_ddrphy_bankmodel1_write_port_adr; +end +always @(posedge sys_clk) begin +end +assign soc_ddrphy_bankmodel1_write_port_dat_r = mem_1[mem_1_adr0]; +assign soc_ddrphy_bankmodel1_read_port_dat_r = mem_1[soc_ddrphy_bankmodel1_read_port_adr]; + + +//------------------------------------------------------------------------------ +// Memory mem_2: 4194304-words x 128-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +// Port 1 | Read: Async | Write: ---- | +reg [127:0] mem_2[0:4194303]; +reg [21:0] mem_2_adr0; +always @(posedge sys_clk) begin : mem_write_block_2 + integer we_index_2; + for(we_index_2 = 0; we_index_2 < 16; we_index_2=we_index_2+1) + if (soc_ddrphy_bankmodel2_write_port_we[we_index_2]) + mem_2[soc_ddrphy_bankmodel2_write_port_adr][we_index_2*8 +: 8] <= soc_ddrphy_bankmodel2_write_port_dat_w[we_index_2*8 +: 8]; + mem_2_adr0 <= soc_ddrphy_bankmodel2_write_port_adr; +end +always @(posedge sys_clk) begin +end +assign soc_ddrphy_bankmodel2_write_port_dat_r = mem_2[mem_2_adr0]; +assign soc_ddrphy_bankmodel2_read_port_dat_r = mem_2[soc_ddrphy_bankmodel2_read_port_adr]; + + +//------------------------------------------------------------------------------ +// Memory mem_3: 4194304-words x 128-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +// Port 1 | Read: Async | Write: ---- | +reg [127:0] mem_3[0:4194303]; +reg [21:0] mem_3_adr0; +always @(posedge sys_clk) begin : mem_write_block_3 + integer we_index_3; + for(we_index_3 = 0; we_index_3 < 16; we_index_3=we_index_3+1) + if (soc_ddrphy_bankmodel3_write_port_we[we_index_3]) + mem_3[soc_ddrphy_bankmodel3_write_port_adr][we_index_3*8 +: 8] <= soc_ddrphy_bankmodel3_write_port_dat_w[we_index_3*8 +: 8]; + mem_3_adr0 <= soc_ddrphy_bankmodel3_write_port_adr; +end +always @(posedge sys_clk) begin +end +assign soc_ddrphy_bankmodel3_write_port_dat_r = mem_3[mem_3_adr0]; +assign soc_ddrphy_bankmodel3_read_port_dat_r = mem_3[soc_ddrphy_bankmodel3_read_port_adr]; + + +//------------------------------------------------------------------------------ +// Memory mem_4: 4194304-words x 128-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +// Port 1 | Read: Async | Write: ---- | +reg [127:0] mem_4[0:4194303]; +reg [21:0] mem_4_adr0; +always @(posedge sys_clk) begin : mem_write_block_4 + integer we_index_4; + for(we_index_4 = 0; we_index_4 < 16; we_index_4=we_index_4+1) + if (soc_ddrphy_bankmodel4_write_port_we[we_index_4]) + mem_4[soc_ddrphy_bankmodel4_write_port_adr][we_index_4*8 +: 8] <= soc_ddrphy_bankmodel4_write_port_dat_w[we_index_4*8 +: 8]; + mem_4_adr0 <= soc_ddrphy_bankmodel4_write_port_adr; +end +always @(posedge sys_clk) begin +end +assign soc_ddrphy_bankmodel4_write_port_dat_r = mem_4[mem_4_adr0]; +assign soc_ddrphy_bankmodel4_read_port_dat_r = mem_4[soc_ddrphy_bankmodel4_read_port_adr]; + + +//------------------------------------------------------------------------------ +// Memory mem_5: 4194304-words x 128-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +// Port 1 | Read: Async | Write: ---- | +reg [127:0] mem_5[0:4194303]; +reg [21:0] mem_5_adr0; +always @(posedge sys_clk) begin : mem_write_block_5 + integer we_index_5; + for(we_index_5 = 0; we_index_5 < 16; we_index_5=we_index_5+1) + if (soc_ddrphy_bankmodel5_write_port_we[we_index_5]) + mem_5[soc_ddrphy_bankmodel5_write_port_adr][we_index_5*8 +: 8] <= soc_ddrphy_bankmodel5_write_port_dat_w[we_index_5*8 +: 8]; + mem_5_adr0 <= soc_ddrphy_bankmodel5_write_port_adr; +end +always @(posedge sys_clk) begin +end +assign soc_ddrphy_bankmodel5_write_port_dat_r = mem_5[mem_5_adr0]; +assign soc_ddrphy_bankmodel5_read_port_dat_r = mem_5[soc_ddrphy_bankmodel5_read_port_adr]; + + +//------------------------------------------------------------------------------ +// Memory mem_6: 4194304-words x 128-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +// Port 1 | Read: Async | Write: ---- | +reg [127:0] mem_6[0:4194303]; +reg [21:0] mem_6_adr0; +always @(posedge sys_clk) begin : mem_write_block_6 + integer we_index_6; + for(we_index_6 = 0; we_index_6 < 16; we_index_6=we_index_6+1) + if (soc_ddrphy_bankmodel6_write_port_we[we_index_6]) + mem_6[soc_ddrphy_bankmodel6_write_port_adr][we_index_6*8 +: 8] <= soc_ddrphy_bankmodel6_write_port_dat_w[we_index_6*8 +: 8]; + mem_6_adr0 <= soc_ddrphy_bankmodel6_write_port_adr; +end +always @(posedge sys_clk) begin +end +assign soc_ddrphy_bankmodel6_write_port_dat_r = mem_6[mem_6_adr0]; +assign soc_ddrphy_bankmodel6_read_port_dat_r = mem_6[soc_ddrphy_bankmodel6_read_port_adr]; + + +//------------------------------------------------------------------------------ +// Memory mem_7: 4194304-words x 128-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +// Port 1 | Read: Async | Write: ---- | +reg [127:0] mem_7[0:4194303]; +reg [21:0] mem_7_adr0; +always @(posedge sys_clk) begin : mem_write_block_7 + integer we_index_7; + for(we_index_7 = 0; we_index_7 < 16; we_index_7=we_index_7+1) + if (soc_ddrphy_bankmodel7_write_port_we[we_index_7]) + mem_7[soc_ddrphy_bankmodel7_write_port_adr][we_index_7*8 +: 8] <= soc_ddrphy_bankmodel7_write_port_dat_w[we_index_7*8 +: 8]; + mem_7_adr0 <= soc_ddrphy_bankmodel7_write_port_adr; +end +always @(posedge sys_clk) begin +end +assign soc_ddrphy_bankmodel7_write_port_dat_r = mem_7[mem_7_adr0]; +assign soc_ddrphy_bankmodel7_read_port_dat_r = mem_7[soc_ddrphy_bankmodel7_read_port_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage: 8-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage[0:7]; +reg [24:0] storage_dat0; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine0_wrport_we) + storage[soc_litedramcore_bankmachine0_wrport_adr] <= soc_litedramcore_bankmachine0_wrport_dat_w; + storage_dat0 <= storage[soc_litedramcore_bankmachine0_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign soc_litedramcore_bankmachine0_wrport_dat_r = storage_dat0; +assign soc_litedramcore_bankmachine0_rdport_dat_r = storage[soc_litedramcore_bankmachine0_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 8-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_1[0:7]; +reg [24:0] storage_1_dat0; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine1_wrport_we) + storage_1[soc_litedramcore_bankmachine1_wrport_adr] <= soc_litedramcore_bankmachine1_wrport_dat_w; + storage_1_dat0 <= storage_1[soc_litedramcore_bankmachine1_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign soc_litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; +assign soc_litedramcore_bankmachine1_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_2: 8-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_2[0:7]; +reg [24:0] storage_2_dat0; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine2_wrport_we) + storage_2[soc_litedramcore_bankmachine2_wrport_adr] <= soc_litedramcore_bankmachine2_wrport_dat_w; + storage_2_dat0 <= storage_2[soc_litedramcore_bankmachine2_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign soc_litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; +assign soc_litedramcore_bankmachine2_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_3: 8-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_3[0:7]; +reg [24:0] storage_3_dat0; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine3_wrport_we) + storage_3[soc_litedramcore_bankmachine3_wrport_adr] <= soc_litedramcore_bankmachine3_wrport_dat_w; + storage_3_dat0 <= storage_3[soc_litedramcore_bankmachine3_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign soc_litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; +assign soc_litedramcore_bankmachine3_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_4: 8-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_4[0:7]; +reg [24:0] storage_4_dat0; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine4_wrport_we) + storage_4[soc_litedramcore_bankmachine4_wrport_adr] <= soc_litedramcore_bankmachine4_wrport_dat_w; + storage_4_dat0 <= storage_4[soc_litedramcore_bankmachine4_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign soc_litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; +assign soc_litedramcore_bankmachine4_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_5: 8-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_5[0:7]; +reg [24:0] storage_5_dat0; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine5_wrport_we) + storage_5[soc_litedramcore_bankmachine5_wrport_adr] <= soc_litedramcore_bankmachine5_wrport_dat_w; + storage_5_dat0 <= storage_5[soc_litedramcore_bankmachine5_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign soc_litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; +assign soc_litedramcore_bankmachine5_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_6: 8-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_6[0:7]; +reg [24:0] storage_6_dat0; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine6_wrport_we) + storage_6[soc_litedramcore_bankmachine6_wrport_adr] <= soc_litedramcore_bankmachine6_wrport_dat_w; + storage_6_dat0 <= storage_6[soc_litedramcore_bankmachine6_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign soc_litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; +assign soc_litedramcore_bankmachine6_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_7: 8-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_7[0:7]; +reg [24:0] storage_7_dat0; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine7_wrport_we) + storage_7[soc_litedramcore_bankmachine7_wrport_adr] <= soc_litedramcore_bankmachine7_wrport_dat_w; + storage_7_dat0 <= storage_7[soc_litedramcore_bankmachine7_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign soc_litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; +assign soc_litedramcore_bankmachine7_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_rdport_adr]; + + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2026-09-16 08:16:25. +//------------------------------------------------------------------------------ diff --git a/hardware/v2/ddr3/tb_litedram_bandwidth.v b/hardware/v2/ddr3/tb_litedram_bandwidth.v new file mode 100644 index 0000000..e2f586b --- /dev/null +++ b/hardware/v2/ddr3/tb_litedram_bandwidth.v @@ -0,0 +1,164 @@ +`timescale 1ns/1ps + +// ============================================================ +// DDR3 exploration -- real measured sustained bandwidth of the +// generated litedram_core_sim.v (LiteDRAM standalone core, ECP5DDRPHY, +// DDR3 MT41K256M16 x16/512MB, sys_clk_freq=75MHz -- config in +// hardware/v2/ddr3/litedram_gen/ecp5_85f_ddr3_mt41k256m16.yml, the +// SAME real chip+clock the real ECPIX-5 board ships with, not a +// tuned/optimistic guess). +// +// Drives the native port (cmd/wdata/rdata, standard LiteX stream +// handshake -- see litedram/common.py's own cmd_description/ +// wdata_description/rdata_description) directly, in strict lockstep +// per transaction (issue cmd, wait ready, push/pull the matching data +// phase, wait ready) -- this is a conservative lower bound on +// achievable bandwidth (no command pipelining attempted), reported as +// such, not claimed as the ceiling. +// +// N_TRANSACTIONS sequential 128-bit (16-byte) writes, then the same +// addresses read back and checked bit-exact against the write +// pattern, with real cycle counts converted to real MB/s using the +// declared sys_clk_freq. +// ============================================================ +module tb; + localparam ADDR_WIDTH = 25; + localparam DATA_WIDTH = 128; + localparam WE_WIDTH = DATA_WIDTH/8; + localparam real SYS_CLK_FREQ_MHZ = 75.0; + localparam real CLK_PERIOD_NS = 1000.0/SYS_CLK_FREQ_MHZ; + + reg clk = 0; + always #(CLK_PERIOD_NS/2.0) clk = ~clk; + + integer cyc; + always @(posedge clk) cyc <= cyc + 1; + + wire init_done, init_error, user_clk, user_rst; + reg [ADDR_WIDTH-1:0] cmd_addr; + wire cmd_ready; + reg cmd_valid, cmd_we; + wire [DATA_WIDTH-1:0] rdata_data; + reg rdata_ready; + wire rdata_valid; + reg [DATA_WIDTH-1:0] wdata_data; + wire wdata_ready; + reg wdata_valid; + reg [WE_WIDTH-1:0] wdata_we; + + // wb_ctrl_* left disconnected (tied off) -- this benchmark drives + // the native port only, no CSR/wishbone control path needed. + wire wb_ctrl_ack, wb_ctrl_err; + wire [31:0] wb_ctrl_dat_r; + + litedram_core_sim dut ( + .clk(clk), + .init_done(init_done), .init_error(init_error), + .sim_trace(1'b0), + .user_clk(user_clk), .user_rst(user_rst), + .user_port_native_0_cmd_addr(cmd_addr), + .user_port_native_0_cmd_ready(cmd_ready), + .user_port_native_0_cmd_valid(cmd_valid), + .user_port_native_0_cmd_we(cmd_we), + .user_port_native_0_rdata_data(rdata_data), + .user_port_native_0_rdata_ready(rdata_ready), + .user_port_native_0_rdata_valid(rdata_valid), + .user_port_native_0_wdata_data(wdata_data), + .user_port_native_0_wdata_ready(wdata_ready), + .user_port_native_0_wdata_valid(wdata_valid), + .user_port_native_0_wdata_we(wdata_we), + .wb_ctrl_ack(wb_ctrl_ack), .wb_ctrl_adr(30'h0), .wb_ctrl_bte(2'h0), + .wb_ctrl_cti(3'h0), .wb_ctrl_cyc(1'b0), .wb_ctrl_dat_r(wb_ctrl_dat_r), + .wb_ctrl_dat_w(32'h0), .wb_ctrl_err(wb_ctrl_err), .wb_ctrl_sel(4'h0), + .wb_ctrl_stb(1'b0), .wb_ctrl_we(1'b0) + ); + + task automatic do_write(input [ADDR_WIDTH-1:0] a, input [DATA_WIDTH-1:0] d); + begin + cmd_valid = 1'b1; cmd_we = 1'b1; cmd_addr = a; + @(posedge clk); + while (!cmd_ready) @(posedge clk); + cmd_valid = 1'b0; + wdata_valid = 1'b1; wdata_data = d; wdata_we = {WE_WIDTH{1'b1}}; + @(posedge clk); + while (!wdata_ready) @(posedge clk); + wdata_valid = 1'b0; + end + endtask + + task automatic do_read(input [ADDR_WIDTH-1:0] a, output [DATA_WIDTH-1:0] d); + begin + cmd_valid = 1'b1; cmd_we = 1'b0; cmd_addr = a; + @(posedge clk); + while (!cmd_ready) @(posedge clk); + cmd_valid = 1'b0; + rdata_ready = 1'b1; + while (!rdata_valid) @(posedge clk); + d = rdata_data; + @(posedge clk); + rdata_ready = 1'b0; + end + endtask + + localparam N_TRANSACTIONS = 256; + integer i, t0, t1, write_cycles, read_cycles, errors; + reg [DATA_WIDTH-1:0] got; + real write_mb_s, read_mb_s; + + initial begin + cmd_valid = 0; cmd_we = 0; cmd_addr = 0; + wdata_valid = 0; wdata_data = 0; wdata_we = 0; + rdata_ready = 0; + errors = 0; cyc = 0; + + // NOTE: this is a CPU-less standalone core (cpu: None) -- init_done + // is normally driven by BIOS software over the wishbone CSR bus + // (real litedram known behavior, see enjoy-digital/litedram + // issue #106 / PR #286: "enable the user port unconditionally in + // CPU-less cases"). With no CPU attached, init_done never + // asserts on its own -- the user port is intentionally usable + // without waiting for it in this configuration. Give the + // power-on reset counters real time to settle, then proceed. + $display("=== CPU-less core: not gating on init_done (see litedram issue #106) -- settling power-on reset ==="); + repeat(2000) @(posedge clk); + $display(" init_done=%b init_error=%b at cycle %0d (%0.2f us) -- proceeding regardless (informational only)", + init_done, init_error, cyc, cyc*CLK_PERIOD_NS/1000.0); + + $display("=== WRITE: %0d sequential 128-bit transactions ===", N_TRANSACTIONS); + t0 = cyc; + for (i = 0; i < N_TRANSACTIONS; i = i + 1) + do_write(i, {8{16'(16'hA000 + i)}}); + t1 = cyc; + write_cycles = t1 - t0; + write_mb_s = (N_TRANSACTIONS * (DATA_WIDTH/8)) / (write_cycles * CLK_PERIOD_NS / 1000.0) / 1.0e6 * 1.0e6; + // (bytes) / (seconds) -> bytes/s; convert to MB/s + write_mb_s = (N_TRANSACTIONS * (DATA_WIDTH/8) * 1.0) / (write_cycles * CLK_PERIOD_NS * 1.0e-9) / 1.0e6; + $display(" %0d cycles, %00.3f us, REAL measured write bandwidth = %0.2f MB/s", + write_cycles, write_cycles*CLK_PERIOD_NS/1000.0, write_mb_s); + + $display("=== READ: %0d sequential 128-bit transactions, bit-exact check ===", N_TRANSACTIONS); + t0 = cyc; + for (i = 0; i < N_TRANSACTIONS; i = i + 1) begin + do_read(i, got); + if (got !== {8{16'(16'hA000 + i)}}) begin + $display("FAIL addr=%0d got=%h", i, got); + errors = errors + 1; + end + end + t1 = cyc; + read_cycles = t1 - t0; + read_mb_s = (N_TRANSACTIONS * (DATA_WIDTH/8) * 1.0) / (read_cycles * CLK_PERIOD_NS * 1.0e-9) / 1.0e6; + $display(" %0d cycles, %0.3f us, REAL measured read bandwidth = %0.2f MB/s", + read_cycles, read_cycles*CLK_PERIOD_NS/1000.0, read_mb_s); + + $display("=== %0d/%0d bit-exact, %0d errors ===", N_TRANSACTIONS-errors, N_TRANSACTIONS, errors); + if (errors == 0) $display("ALL DATA BIT-EXACT (tb_litedram_bandwidth)"); + $finish; + end + + initial begin + #2000000; // 2ms real-time safety watchdog + $display("WATCHDOG TIMEOUT -- init_done never asserted or benchmark hung"); + $finish; + end +endmodule diff --git a/hardware/v2/logs/experiments.log b/hardware/v2/logs/experiments.log index 11cd548..18ecbfd 100644 --- a/hardware/v2/logs/experiments.log +++ b/hardware/v2/logs/experiments.log @@ -3345,3 +3345,140 @@ hardware/v2/nms/sim/tb_sdram_cdc_bridge_openrow.v, hardware/v2/nms/sim/tb_nms_dstress_sdram_combined.v, hardware/v2/nms/sim/tb_nms_dstress_sdram_openrow.v, hardware/v2/nms/sim/tb_nms_dstress_sdram_cdc.v. + +EXP-0056 -- N_SLOTS=16 timing closure on LFE5U-85F: two real fixes, +one didn't matter, one did (2026-09-16) + +DATE: 2026-09-16 +CONTEXT: EXP-0055 (open-row backend, real board top) promoted to a +candidate but never checked at N_SLOTS=16 -- real 8-seed P&R baseline +(EXP-0049/0050-era numbers) never covered N=16 either. Real synthesis ++ nextpnr-ecp5 --85k (LFE5U-85F, same CABGA381 package/pinout as the +real board's v2_board_top.lpf -- confirmed pin-compatible) at +N_SLOTS=16: worst 23.52-24.64MHz across two independent seeds, FAIL at +the real 64MHz target. DSP fit confirmed fine (128/156 MULT18X18D, +82%) -- this is a timing-closure problem, not a resource problem. + +HYPOTHESIS 1 (wrong, but real work, kept as a disclosed negative +result): dependency_manager.v's own first_ready_idx scan (serial +for-loop over up to N_NODES=1024, same architectural anti-pattern +already fixed twice elsewhere -- ERR-0027/ERR-0028/ERR-0029). Built +priority_encoder_lsb.v (generic recursive binary-tree lowest-set-bit +encoder, O(log2(WIDTH)) depth) + dependency_manager_fast.v (fork, +swaps in the encoder). Isolated: 65536/65536 exhaustive at WIDTH=16, +76562/76562 at WIDTH=1024. Bit-exact equivalence vs the original +module: 20000/20000 cycles matched under random stimulus +(tb_dependency_manager_fast.v), plus the original hand-crafted DAG +testbench, both 100%. Integrated (N_SLOTS=16, LFE5U-85F): worst +24.26MHz -- ESSENTIALLY UNCHANGED from the pre-fix 23.52-24.64MHz. +CONCLUSION: dependency_manager.v was not the real N=16 bottleneck. +Kept as a real, verified, low-risk correctness-neutral improvement +(shorter combinational depth is never worse), just not the fix that +mattered here. + +HYPOTHESIS 2 (real root cause, found from the actual nextpnr critical- +path report on the Hypothesis-1 run): nms_activation_fill_ctrl_v3.v's +own balanced max-tree (a real fix from an EARLIER session, its own +header says so explicitly) was hand-coded ONLY for N_SLOTS in +{1,2,4,8} -- any other value, INCLUDING N_SLOTS=16, falls through to +GEN_MAXTREE_FALLBACK, the exact same flat N_SLOTS-wide sequential +scan/carry-chain that earlier fix was written to eliminate. Never +extended to cover 16. Real critical path (nextpnr's own report, +Hypothesis-1 run): a long CCU2C COUT/CIN carry chain inside +nms_activation_fill_ctrl_v3.v's max_n_tiles_reg comparator, confirming +this exactly. +FIX: nms_activation_fill_ctrl_v3_n16.v (fork), added the missing +N_SLOTS==16 case -- same balanced-tree pattern as the existing N==8 +case, one more level (8 pairwise compares -> 4 -> 2 -> 1, 4 levels +total). Isolated: tb_maxtree_n16.v, 10017/10017 (targeted + random) +against the same flat-scan reference the fallback path itself uses as +its own documented "correct but not optimized" baseline. +RESULT (N_SLOTS=16, LFE5U-85F, seed 1, both fixes combined -- +dependency_manager_fast + activation_fill_ctrl_v3_n16 -- in nms_ +dataflow_core_sdram_fast.v / fpga_neural_v2_top_openrow_fast.v): +worst 71.01MHz, PASS at 64MHz. 0 errors. Functional regression +unaffected: D-Stress N=16 still 256/256 bit-exact, total_cycles=47454 +(identical to the pre-fix functional baseline, as expected -- these +are pure combinational-depth fixes, not behavior changes) -- and still +confirms N=16 gives ZERO extra real throughput over N=4/N=8 on the +zero-reuse D-Stress workload (memory-bound, unrelated to this fix). +STATUS: single-seed PASS, not yet the project's own 8-seed standard. +next_action: run the full 8-seed sweep before treating N=16 as a +closed, production-ready configuration. New files (additive only, +none touch the real board top or existing production RTL): +hardware/v2/rtl/priority_encoder_lsb.v, +hardware/v2/rtl/dependency_manager_fast.v, +hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3_n16.v, +hardware/v2/nms/rtl/nms_dataflow_core_sdram_fast.v, +hardware/v2/nms/rtl/fpga_neural_v2_top_openrow_fast.v, +hardware/v2/nms/rtl/nms_neural_multiprocessor_sdram_openrow_fast.v, +hardware/v2/sim/tb_priority_encoder_lsb.v, +hardware/v2/sim/tb_dependency_manager_fast.v, +hardware/v2/sim/tb_maxtree_n16.v, +hardware/v2/nms/sim/tb_fpga_neural_v2_top_openrow_fast_smoke.v, +hardware/v2/nms/sim/tb_nms_dstress_sdram_openrow_fast.v. + +EXP-0057 -- weight-stationary layer reuse: real measured 7.16x memory- +side speedup, SAME hardware, no DDR3 (2026-09-16) + +DATE: 2026-09-16 +CONTEXT: user-driven pivot after establishing the real target +application class (generic neural accelerator for face-recognition- +style CNNs, not the zero-reuse D-Stress worst case this whole project +has been benchmarked against). D-Stress's own zero reuse means no +architecture can beat the physical bandwidth floor (established +earlier this session); a real conv-style workload has massive weight +reuse (same filter applied at every spatial position) that D-Stress +deliberately excludes -- this experiment measures that case for real, +on the SAME SDR SDRAM hardware this project already has (no DDR3, no +clock change), to answer directly whether DDR3 is even necessary for +a workload class that actually has reuse. + +METHOD: layer_weight_buffer.v (new) -- double-buffered, per-layer +resident weight scratchpad (BRAM-style, same coding idiom as nms_ +weight_packed.v). One buffer read many times (M reuses) while the +OTHER is filled in the background from SDRAM; swap is order- +independent (fill_done/consume_done latched separately, swap fires +once both have been seen since the last swap -- same req_pending-latch +discipline as sdram_unified_backend.v's own established correctness +fixes). Isolated: tb_layer_weight_buffer.v, 1540/1540, including +out-of-order fill/consume completion and a "consume_done alone must +not swap without a matching fill_done" negative check. + +tb_layer_reuse_vs_zero_reuse.v: wired layer_weight_buffer.v to the +REAL sdram_controller_openrow.v (EXP-0054) + sdram_model.v -- same +hardware, nothing new. SAME total useful-byte-consumption in both +cases (32768 bytes, matching D-Stress's own 256x128 total exactly): + REUSE case: 16 layers x 128 bytes each fetched ONCE, reused 16x + locally = 2048 bytes actually fetched from SDRAM. + ZERO-REUSE case: 16 layers x 16 reuses x 128 bytes, every reuse + fetched independently = 32768 bytes (D-Stress's + own pattern, through the identical controller). +Fair timing comparison (an earlier version of this testbench asymmetrically +added compute-side consumption cycles to only the reuse case, making it +look SLOWER -- found and fixed before trusting any number; final +version measures ONLY real SDRAM fetch cost in both cases, which is +the actual question this experiment exists to answer). + +RESULT: REUSE case data correctness 32768/32768, 0 errors, through the +real controller+model. Real measured cycles: REUSE = 3777, ZERO-REUSE += 27048 (for the identical 32768 bytes of useful data delivered) -- +**7.16x real measured speedup from weight reuse alone**, same SDR +SDRAM, same 64MHz clock, zero new hardware. Substantially larger than +any protocol-level lever measured this session (open-row +5%, dual- +bank ~9%, CDC net-negative) -- because this reduces bytes actually +moved rather than trying to move the same bytes faster. +DECISION: for workload classes with real reuse (conv-style, unlike +D-Stress), DDR3 is NOT established as necessary -- this result directly +contradicts the earlier (correct, but scope-limited-to-zero-reuse) +conclusion that only more physical bandwidth could help. DDR3 remains +relevant only if a real target model's per-layer working set exceeds +what layer-by-layer streaming + on-chip BRAM can hold, which depends +on the real model size (still not pinned down as of this entry). +next_action: integrate layer_weight_buffer.v with the real per-slot +compute path (neural_processor.v) and a real conv-shaped benchmark +(not just the synthetic byte-reuse pattern here) before calling this +production-ready. New files (additive only): +hardware/v2/rtl/layer_weight_buffer.v, +hardware/v2/sim/tb_layer_weight_buffer.v, +hardware/v2/sim/tb_layer_reuse_vs_zero_reuse.v. diff --git a/hardware/v2/nms/rtl/fpga_neural_v2_top_openrow_fast.v b/hardware/v2/nms/rtl/fpga_neural_v2_top_openrow_fast.v new file mode 100644 index 0000000..d3e188b --- /dev/null +++ b/hardware/v2/nms/rtl/fpga_neural_v2_top_openrow_fast.v @@ -0,0 +1,265 @@ +`timescale 1ns/1ps + +// ================================================================ +// FPGA-Neural V2 -- BOARD-LEVEL TOP (STEP20, real physical interface) +// +// Wraps the STEP19 frozen compute+memory design (the same submodules +// nms_neural_multiprocessor_sdram_unified.v instantiates -- that file +// itself is NOT instantiated here, since its own reg_*/N_SLOTS+1-port +// AR arbitration needs a second arbitration LEVEL added for the new +// host-raw-SDRAM-access port; this module reproduces that same +// internal wiring plus the extra level, rather than modifying the +// frozen file) with the three things a real physical board needs that +// a testbench does not: +// +// 1. A real SPI host interface (spi_host_bridge.v) in place of the +// 110-pin reg_* testbench bus -- reg_valid/reg_ready/reg_node_id/ +// etc are now DRIVEN BY THE BRIDGE, not exposed as top ports. +// 2. A real ECP5 PLL (ecp5_pll_sys_clk.v, EHXPLLL) generating the +// system clock from the board's 16MHz oscillator, instead of +// assuming an already-correct-frequency clock input. +// 3. A real reset/POR synchronizer (reset_sync.v). +// +// nms_dataflow_core_sdram.v, dependency_manager.v, neural_processor.v, +// neural_director.v, slot_mem_arbiter.v, slot_mem_arbiter_wide.v, +// sdram_unified_backend.v, sdram_controller.v are ALL byte-for-byte +// unchanged (STEP19/STEP20 standing constraint) -- this file only +// ADDS one more, already-proven, generically-parameterized +// slot_mem_arbiter instance (N_PORTS=2) to arbitrate the SPI bridge's +// raw host memory port against the existing compute-side AR stream, +// both funneling into the SAME single sdram_unified_backend/ +// sdram_controller/AS4C4M16SA-6TIN physical chain STEP19 already +// validated. No V1 RTL is instantiated (STEP19's "zero V1 files in +// the V2 compile list" property is preserved). +// ================================================================ + +module fpga_neural_v2_top_openrow_fast #( + parameter DATA_WIDTH = 8, + parameter P_IN = 8, + parameter ACC_WIDTH = 32, + parameter ADDR_WIDTH = 26, + parameter N_SLOTS = 4, + parameter N_NODES = 16, + parameter MAX_DEPS = 4, + parameter QUEUE_DEPTH = 8, + parameter MAX_TILES = 16, + parameter PREFETCH_DISTANCE = 8, + parameter CLK_FREQ_MHZ = 64 +)( + input wire osc_clk, // 16 MHz board oscillator + input wire ext_rst_n, // external POR/supervisor, active-low + + // ---- physical SPI host interface ---- + input wire spi_sclk, + input wire spi_mosi, + output wire spi_miso, + input wire spi_cs_n, + + // ---- single physical SDRAM (weights + activations + results) ---- + // sdram_clk: the real SDRAM chip's own CLK pin -- an external + // chip, it needs this driven from a real output ball, NOT just + // internal routing. Found missing entirely during this session's + // schematic review (clk_sys was purely internal, never reached a + // pad) -- added here, real free clock-capable ball (bank 6). + output wire sdram_clk, + output wire sdram_cke, + output wire sdram_cs_n, + output wire sdram_ras_n, + output wire sdram_cas_n, + output wire sdram_we_n, + output wire [1:0] sdram_ba, + output wire [12:0] sdram_a, + inout wire [15:0] sdram_dq, + output wire [1:0] sdram_dqm, + + // FPGA_DATA_READY: high once the whole registered graph has + // finished (system-idle sticky flag, self-clearing on new work) -- + // see nms_dataflow_core_sdram.v for the full design comment. + output wire data_ready, + + output wire pll_locked +); + + // ============================================================ + // CLOCK / RESET + // ============================================================ + wire clk_sys; + ecp5_pll_sys_clk u_pll ( + .clk_16mhz(osc_clk), .clk_sys(clk_sys), .locked(pll_locked) + ); + + assign sdram_clk = clk_sys; + + wire clk = clk_sys; + wire rst; + reset_sync u_reset_sync ( + .clk_sys(clk_sys), .ext_rst_n(ext_rst_n), .pll_locked(pll_locked), .rst(rst) + ); + + wire soft_rst_pulse; + wire core_rst = rst | soft_rst_pulse; + + // ============================================================ + // SPI HOST BRIDGE (replaces the 110-pin reg_* testbench bus) + // ============================================================ + wire reg_valid, reg_ready; + wire [$clog2(N_NODES)-1:0] reg_node_id; + wire [$clog2(MAX_DEPS+1)-1:0] reg_required; + wire [MAX_DEPS*$clog2(N_NODES)-1:0] reg_producer_ids; + wire [ADDR_WIDTH-1:0] reg_x_base, reg_w_base, reg_result_addr; + wire [15:0] reg_n_tiles; + + wire host_mem_req, host_mem_wr, host_mem_lb_n, host_mem_ub_n; + wire [ADDR_WIDTH-1:0] host_mem_addr; + wire [15:0] host_mem_wdata, host_mem_rdata; + wire host_mem_ready; + + spi_host_bridge #( + .ADDR_WIDTH(ADDR_WIDTH), .N_NODES(N_NODES), .MAX_DEPS(MAX_DEPS) + ) u_spi_bridge ( + .clk(clk), .rst(rst), + .sclk(spi_sclk), .mosi(spi_mosi), .miso(spi_miso), .cs_n(spi_cs_n), + .reg_valid(reg_valid), .reg_ready(reg_ready), .reg_node_id(reg_node_id), + .reg_required(reg_required), .reg_producer_ids(reg_producer_ids), + .reg_x_base(reg_x_base), .reg_w_base(reg_w_base), + .reg_n_tiles(reg_n_tiles), .reg_result_addr(reg_result_addr), + .mem_req(host_mem_req), .mem_wr(host_mem_wr), .mem_addr(host_mem_addr), + .mem_wdata(host_mem_wdata), .mem_lb_n(host_mem_lb_n), .mem_ub_n(host_mem_ub_n), + .mem_rdata(host_mem_rdata), .mem_ready(host_mem_ready), + .soft_rst_pulse(soft_rst_pulse) + ); + + // ============================================================ + // COMPUTE + MEMORY (same wiring as nms_neural_multiprocessor_ + // sdram_unified.v, plus the new host-arb level) + // ============================================================ + wire [N_SLOTS:0] slot_mem_req, slot_mem_wr; + wire [ADDR_WIDTH*(N_SLOTS+1)-1:0] slot_mem_addr; + wire [16*(N_SLOTS+1)-1:0] slot_mem_wdata, slot_mem_rdata; + wire [N_SLOTS:0] slot_mem_lb_n, slot_mem_ub_n; + wire [N_SLOTS:0] slot_mem_ready; + + wire [N_SLOTS-1:0] wide_slot_mem_req; + wire [ADDR_WIDTH*N_SLOTS-1:0] wide_slot_mem_addr; + wire [64*N_SLOTS-1:0] wide_slot_mem_rdata; + wire [N_SLOTS-1:0] wide_slot_mem_ready; + + nms_dataflow_core_sdram_fast #( + .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH), .ADDR_WIDTH(ADDR_WIDTH), + .N_SLOTS(N_SLOTS), .N_NODES(N_NODES), .MAX_DEPS(MAX_DEPS), .QUEUE_DEPTH(QUEUE_DEPTH), + .MAX_TILES(MAX_TILES), .PREFETCH_DISTANCE(PREFETCH_DISTANCE) + ) u_dataflow_core ( + .clk(clk), .rst(core_rst), + .reg_valid(reg_valid), .reg_ready(reg_ready), .reg_node_id(reg_node_id), + .reg_required(reg_required), .reg_producer_ids(reg_producer_ids), + .reg_x_base(reg_x_base), .reg_w_base(reg_w_base), .reg_n_tiles(reg_n_tiles), + .reg_result_addr(reg_result_addr), + .data_ready(data_ready), + .slot_mem_req(slot_mem_req), .slot_mem_wr(slot_mem_wr), .slot_mem_addr(slot_mem_addr), + .slot_mem_wdata(slot_mem_wdata), .slot_mem_lb_n(slot_mem_lb_n), .slot_mem_ub_n(slot_mem_ub_n), + .slot_mem_rdata(slot_mem_rdata), .slot_mem_ready(slot_mem_ready), + .wide_slot_mem_req(wide_slot_mem_req), .wide_slot_mem_addr(wide_slot_mem_addr), + .wide_slot_mem_rdata(wide_slot_mem_rdata), .wide_slot_mem_ready(wide_slot_mem_ready) + ); + + // ---- AR level 1 (unchanged): activation-fill + per-slot result + // writeback, exactly as nms_neural_multiprocessor_sdram_unified.v ---- + wire arb_m_req, arb_m_wr; + wire [ADDR_WIDTH-1:0] arb_m_addr; + wire [15:0] arb_m_wdata; + wire arb_m_lb_n, arb_m_ub_n; + wire [15:0] arb_m_rdata; + wire arb_m_ready; + + slot_mem_arbiter #( + .ADDR_WIDTH(ADDR_WIDTH), .N_PORTS(N_SLOTS+1) + ) u_arbiter ( + .clk(clk), .rst(core_rst), + .s_req(slot_mem_req), .s_wr(slot_mem_wr), .s_addr(slot_mem_addr), + .s_wdata(slot_mem_wdata), .s_lb_n(slot_mem_lb_n), .s_ub_n(slot_mem_ub_n), + .s_rdata(slot_mem_rdata), .s_ready(slot_mem_ready), + .m_req(arb_m_req), .m_wr(arb_m_wr), .m_addr(arb_m_addr), .m_wdata(arb_m_wdata), + .m_lb_n(arb_m_lb_n), .m_ub_n(arb_m_ub_n), + .m_rdata(arb_m_rdata), .m_ready(arb_m_ready) + ); + + // ---- AR level 2 (NEW, STEP20): compute-side AR stream (port0) + // vs. SPI host raw memory port (port1) -- reuses slot_mem_arbiter + // completely unchanged, just at N_PORTS=2, its own already-proven + // pending-latch discipline applying equally to a 2-port instance ---- + wire [1:0] host_arb_s_req, host_arb_s_wr, host_arb_s_lb_n, host_arb_s_ub_n, host_arb_s_ready; + wire [ADDR_WIDTH*2-1:0] host_arb_s_addr; + wire [16*2-1:0] host_arb_s_wdata, host_arb_s_rdata; + + assign host_arb_s_req = {host_mem_req, arb_m_req}; + assign host_arb_s_wr = {host_mem_wr, arb_m_wr}; + assign host_arb_s_lb_n = {host_mem_lb_n, arb_m_lb_n}; + assign host_arb_s_ub_n = {host_mem_ub_n, arb_m_ub_n}; + assign host_arb_s_addr = {host_mem_addr, arb_m_addr}; + assign host_arb_s_wdata = {host_mem_wdata, arb_m_wdata}; + assign arb_m_ready = host_arb_s_ready[0]; + assign arb_m_rdata = host_arb_s_rdata[15:0]; + assign host_mem_ready = host_arb_s_ready[1]; + assign host_mem_rdata = host_arb_s_rdata[31:16]; + + wire final_ar_req, final_ar_wr; + wire [ADDR_WIDTH-1:0] final_ar_addr; + wire [15:0] final_ar_wdata; + wire final_ar_lb_n, final_ar_ub_n; + wire [15:0] final_ar_rdata; + wire final_ar_ready; + + slot_mem_arbiter #( + .ADDR_WIDTH(ADDR_WIDTH), .N_PORTS(2) + ) u_host_arb ( + .clk(clk), .rst(core_rst), + .s_req(host_arb_s_req), .s_wr(host_arb_s_wr), .s_addr(host_arb_s_addr), + .s_wdata(host_arb_s_wdata), .s_lb_n(host_arb_s_lb_n), .s_ub_n(host_arb_s_ub_n), + .s_rdata(host_arb_s_rdata), .s_ready(host_arb_s_ready), + .m_req(final_ar_req), .m_wr(final_ar_wr), .m_addr(final_ar_addr), .m_wdata(final_ar_wdata), + .m_lb_n(final_ar_lb_n), .m_ub_n(final_ar_ub_n), + .m_rdata(final_ar_rdata), .m_ready(final_ar_ready) + ); + + // ---- W: weight fetch (unchanged) ---- + wire [N_SLOTS-1:0] wide_s_wr = {N_SLOTS{1'b0}}; + wire [64*N_SLOTS-1:0] wide_s_wdata = {(64*N_SLOTS){1'b0}}; + wire [N_SLOTS-1:0] wide_s_lb_n = {N_SLOTS{1'b0}}; + wire [N_SLOTS-1:0] wide_s_ub_n = {N_SLOTS{1'b0}}; + + wire wide_arb_m_req, wide_arb_m_wr; + wire [ADDR_WIDTH-1:0] wide_arb_m_addr; + wire [63:0] wide_arb_m_wdata; + wire wide_arb_m_lb_n, wide_arb_m_ub_n; + wire [63:0] wide_arb_m_rdata; + wire wide_arb_m_ready; + + slot_mem_arbiter_wide #( + .ADDR_WIDTH(ADDR_WIDTH), .N_PORTS(N_SLOTS), .DATA_WIDTH(64) + ) u_arbiter_wide ( + .clk(clk), .rst(core_rst), + .s_req(wide_slot_mem_req), .s_wr(wide_s_wr), .s_addr(wide_slot_mem_addr), + .s_wdata(wide_s_wdata), .s_lb_n(wide_s_lb_n), .s_ub_n(wide_s_ub_n), + .s_rdata(wide_slot_mem_rdata), .s_ready(wide_slot_mem_ready), + .m_req(wide_arb_m_req), .m_wr(wide_arb_m_wr), .m_addr(wide_arb_m_addr), .m_wdata(wide_arb_m_wdata), + .m_lb_n(wide_arb_m_lb_n), .m_ub_n(wide_arb_m_ub_n), + .m_rdata(wide_arb_m_rdata), .m_ready(wide_arb_m_ready) + ); + + // ---- ONE physical SDRAM backend, both W and (now 2-source- + // arbitrated) AR ports ---- + sdram_unified_backend_openrow #( + .ADDR_WIDTH(ADDR_WIDTH), .CLK_FREQ_MHZ(CLK_FREQ_MHZ) + ) u_sdram_backend ( + .clk(clk), .rst(core_rst), + .w_req(wide_arb_m_req), .w_addr(wide_arb_m_addr), + .w_rdata(wide_arb_m_rdata), .w_ready(wide_arb_m_ready), + .ar_req(final_ar_req), .ar_wr(final_ar_wr), .ar_addr(final_ar_addr), .ar_wdata(final_ar_wdata), + .ar_lb_n(final_ar_lb_n), .ar_ub_n(final_ar_ub_n), + .ar_rdata(final_ar_rdata), .ar_ready(final_ar_ready), + .sdram_cke(sdram_cke), .sdram_cs_n(sdram_cs_n), .sdram_ras_n(sdram_ras_n), + .sdram_cas_n(sdram_cas_n), .sdram_we_n(sdram_we_n), + .sdram_ba(sdram_ba), .sdram_a(sdram_a), .sdram_dq(sdram_dq), .sdram_dqm(sdram_dqm) + ); + +endmodule diff --git a/hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3_n16.v b/hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3_n16.v new file mode 100644 index 0000000..a81fd09 --- /dev/null +++ b/hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3_n16.v @@ -0,0 +1,310 @@ +// ============================================================ +// Neural Memory System (NMS) -- shared Activation fill controller. +// +// One instance per neural_memory_system (shared across all N_SLOTS), +// backing nms_activation_replicated.v's single broadcast-write fill +// port. Owns ONE prefetch_engine.v instance (real word-level PSRAM +// fetch, DEC-0015 convention, reused verbatim -- it is generic +// P_IN-byte-tile fetch logic, not weight-specific despite its name). +// +// Single-tag design (same honest limitation as the superseded +// hardware/v2/rtl/activation_cache.v, DEC-0016): tracks ONE resident +// x_base at a time. Refills (resident_count resets to 0, restarts +// fetching from tile 0) whenever the lowest-indexed currently-active +// slot's own x_base differs from what is resident -- correct always, +// but can thrash under interleaved, genuinely-different-x_base +// concurrent traffic; not exercised by this project's own realistic +// dense-layer workloads (shared-producer dispatch, many slots given +// the SAME x_base together). +// +// resident_count extends to the MAX n_tiles needed by any currently +// active slot that shares resident_tag (not just the reference slot +// that triggered the refill), so a later-joining slot with a deeper +// need is served without a second refill. +// ============================================================ +module nms_activation_fill_ctrl_v3_n16 #( + parameter DATA_WIDTH = 8, + parameter P_IN = 8, + parameter N_SLOTS = 4, + parameter ADDR_WIDTH = 26, + parameter MAX_TILES = 16, + // TIW indexes the SRAM fill address (0..MAX_TILES-1); CNTW is for + // resident_count, which must represent the VALUE MAX_TILES itself + // (e.g. a fully-resident 16-tile vector with MAX_TILES=16) -- one + // bit wider than TIW, same distinction/bug as + // nms_memory_manager.v's own tile_idx/wgt_fetched (see that file's + // header for the real deadlock this caused before the fix). + parameter TIW = (MAX_TILES <= 1) ? 1 : $clog2(MAX_TILES), + parameter CNTW = $clog2(MAX_TILES+1) +)( + input wire clk, + input wire rst, + + // ---- per-slot job status (levels, held while that slot's job is active) ---- + input wire [N_SLOTS-1:0] job_active, + input wire [N_SLOTS*ADDR_WIDTH-1:0] x_base_flat, + input wire [N_SLOTS*16-1:0] n_tiles_flat, + + // ---- broadcast status (every slot compares this against its own x_base) ---- + output reg [ADDR_WIDTH-1:0] resident_tag, + output reg [CNTW-1:0] resident_count, + + // ---- fill port into nms_activation_replicated.v ---- + output wire fill_we, + output wire [TIW-1:0] fill_addr, + output wire [DATA_WIDTH*P_IN-1:0] fill_data, + + // ---- real word-level PSRAM backend (arbitrated externally) ---- + output wire mem_req, + output wire mem_wr, + output wire [ADDR_WIDTH-1:0] mem_addr, + output wire [15:0] mem_wdata, + output wire mem_lb_n, + output wire mem_ub_n, + input wire [15:0] mem_rdata, + input wire mem_ready +); + + integer i; + + // ---- desired x_base: lowest-indexed currently-active slot (fixed + // priority -- simple, not fairness-critical here since this only + // decides which TAG to chase, not who gets bandwidth) ---- + reg desired_valid; + reg [ADDR_WIDTH-1:0] desired_x_base; + + always @* begin + desired_valid = 1'b0; + desired_x_base = {ADDR_WIDTH{1'b0}}; + for (i = N_SLOTS-1; i >= 0; i = i - 1) begin + if (job_active[i]) begin + desired_valid = 1'b1; + desired_x_base = x_base_flat[i*ADDR_WIDTH +: ADDR_WIDTH]; + end + end + end + + // ---- STEP14/EXP-0029->EXP-0030: max_n_tiles computation split + // into TWO pipeline stages, since registering ONLY its final use + // (v2, DEC-0026) left the computation ITSELF as the new critical + // path (EXP-0030, N=4 Fmax=72.78MHz, still FAIL@80MHz): the + // original single-cycle logic mixed, PER SLOT, a 23-bit tag + // equality check (x_base_flat[i]==resident_tag) together with an + // N_SLOTS-wide SEQUENTIALLY-CHAINED 16-bit running-max fold (each + // iteration's update depends on the previous one) -- both + // combinational, both in the same cycle as the register that + // captures the result. + // + // Stage 1 (independent per-slot work, no chain dependency between + // slots): register a per-slot "counts toward this refill" mask + // (job_active[i] && tag-match) and, gated by that mask, each + // slot's own n_tiles value (0 if it doesn't count) -- N_SLOTS + // independent 23-bit equality checks, no data dependency between + // slots, so their combined depth does not grow with N_SLOTS the + // way a sequential fold does. + // Stage 2 (the actual reduction): fold the REGISTERED, already- + // masked per-slot values into max_n_tiles_reg -- still an + // N_SLOTS-wide sequential chain (same fold as before), but now + // operating alone, without the equality check sharing the same + // cycle. + reg [15:0] n_tiles_masked [0:N_SLOTS-1]; + genvar gsi; + generate + for (gsi = 0; gsi < N_SLOTS; gsi = gsi + 1) begin : GEN_MASK + wire slot_counts = job_active[gsi] && + (x_base_flat[gsi*ADDR_WIDTH +: ADDR_WIDTH] == resident_tag); + always @(posedge clk) begin + if (rst) n_tiles_masked[gsi] <= 16'h0; + else n_tiles_masked[gsi] <= slot_counts ? n_tiles_flat[gsi*16 +: 16] : 16'h0; + end + end + endgenerate + + // Balanced binary max-tree (log2(N_SLOTS) comparison levels) + // instead of the flat N_SLOTS-wide sequential scan this file's own + // header comment above already flagged as "an N_SLOTS-wide + // sequential chain". Found and fixed this session: that chain's + // own carry-chain critical path became the DOMINANT critical path + // at N_SLOTS=8 (real nextpnr-ecp5 P&R: Fmax collapsed to ~40MHz, + // failing the 64MHz target across every measured seed). A tree + // has the SAME single-cycle combinational timing as the scan it + // replaces (max_n_tiles_reg is still registered exactly one cycle + // behind n_tiles_masked -- no FSM/latency change, purely a + // combinational-depth reduction: log2(N_SLOTS) levels instead of + // N_SLOTS). + // + // Written as explicit, uniquely-named per-level wires (NOT a + // multi-dimensional generate-indexed array) -- a first attempt + // using a shared 2D `wire max_tree[level][idx]` array triggered a + // real simulator UNOPTFLAT "circular combinational logic" warning. + // The actual dependency graph IS acyclic (level L+1 only ever + // reads level L), but that tool's array-flattening circularity + // check could not prove that for a shared 2D array; distinctly- + // named per-level wires sidestep the ambiguity entirely for both + // simulation and synthesis. N_SLOTS is a power of two for every + // real configuration this project uses (1/2/4/8); anything else + // falls back, explicitly, to the original flat scan (correct but not + // optimized) rather than silently doing the wrong thing. + reg [15:0] max_n_tiles_reg; + generate + if (N_SLOTS == 1) begin : GEN_MAXTREE_N1 + always @(posedge clk) begin + if (rst) max_n_tiles_reg <= 16'h0; + else max_n_tiles_reg <= n_tiles_masked[0]; + end + end else if (N_SLOTS == 2) begin : GEN_MAXTREE_N2 + wire [15:0] max_final = (n_tiles_masked[0] > n_tiles_masked[1]) ? n_tiles_masked[0] : n_tiles_masked[1]; + always @(posedge clk) begin + if (rst) max_n_tiles_reg <= 16'h0; + else max_n_tiles_reg <= max_final; + end + end else if (N_SLOTS == 4) begin : GEN_MAXTREE_N4 + wire [15:0] m0 = (n_tiles_masked[0] > n_tiles_masked[1]) ? n_tiles_masked[0] : n_tiles_masked[1]; + wire [15:0] m1 = (n_tiles_masked[2] > n_tiles_masked[3]) ? n_tiles_masked[2] : n_tiles_masked[3]; + wire [15:0] max_final = (m0 > m1) ? m0 : m1; + always @(posedge clk) begin + if (rst) max_n_tiles_reg <= 16'h0; + else max_n_tiles_reg <= max_final; + end + end else if (N_SLOTS == 8) begin : GEN_MAXTREE_N8 + wire [15:0] m0 = (n_tiles_masked[0] > n_tiles_masked[1]) ? n_tiles_masked[0] : n_tiles_masked[1]; + wire [15:0] m1 = (n_tiles_masked[2] > n_tiles_masked[3]) ? n_tiles_masked[2] : n_tiles_masked[3]; + wire [15:0] m2 = (n_tiles_masked[4] > n_tiles_masked[5]) ? n_tiles_masked[4] : n_tiles_masked[5]; + wire [15:0] m3 = (n_tiles_masked[6] > n_tiles_masked[7]) ? n_tiles_masked[6] : n_tiles_masked[7]; + wire [15:0] m01 = (m0 > m1) ? m0 : m1; + wire [15:0] m23 = (m2 > m3) ? m2 : m3; + wire [15:0] max_final = (m01 > m23) ? m01 : m23; + always @(posedge clk) begin + if (rst) max_n_tiles_reg <= 16'h0; + else max_n_tiles_reg <= max_final; + end + end else if (N_SLOTS == 16) begin : GEN_MAXTREE_N16 + // EXP-0056: same balanced-tree pattern as N_SLOTS==8 above, + // one more level. This is the exact case that used to fall + // through to GEN_MAXTREE_FALLBACK's own flat sequential + // scan -- the real critical path measured blocking + // N_SLOTS=16 timing closure on the LFE5U-85F (worst + // 23.52-24.64MHz vs 64MHz target across two independent + // seeds, both pre-fix; see experiments.log EXP-0056). + wire [15:0] m0 = (n_tiles_masked[0] > n_tiles_masked[1]) ? n_tiles_masked[0] : n_tiles_masked[1]; + wire [15:0] m1 = (n_tiles_masked[2] > n_tiles_masked[3]) ? n_tiles_masked[2] : n_tiles_masked[3]; + wire [15:0] m2 = (n_tiles_masked[4] > n_tiles_masked[5]) ? n_tiles_masked[4] : n_tiles_masked[5]; + wire [15:0] m3 = (n_tiles_masked[6] > n_tiles_masked[7]) ? n_tiles_masked[6] : n_tiles_masked[7]; + wire [15:0] m4 = (n_tiles_masked[8] > n_tiles_masked[9]) ? n_tiles_masked[8] : n_tiles_masked[9]; + wire [15:0] m5 = (n_tiles_masked[10] > n_tiles_masked[11]) ? n_tiles_masked[10] : n_tiles_masked[11]; + wire [15:0] m6 = (n_tiles_masked[12] > n_tiles_masked[13]) ? n_tiles_masked[12] : n_tiles_masked[13]; + wire [15:0] m7 = (n_tiles_masked[14] > n_tiles_masked[15]) ? n_tiles_masked[14] : n_tiles_masked[15]; + wire [15:0] m01 = (m0 > m1) ? m0 : m1; + wire [15:0] m23 = (m2 > m3) ? m2 : m3; + wire [15:0] m45 = (m4 > m5) ? m4 : m5; + wire [15:0] m67 = (m6 > m7) ? m6 : m7; + wire [15:0] m0123 = (m01 > m23) ? m01 : m23; + wire [15:0] m4567 = (m45 > m67) ? m45 : m67; + wire [15:0] max_final = (m0123 > m4567) ? m0123 : m4567; + always @(posedge clk) begin + if (rst) max_n_tiles_reg <= 16'h0; + else max_n_tiles_reg <= max_final; + end + end else begin : GEN_MAXTREE_FALLBACK + reg [15:0] max_n_tiles_comb_fallback; + integer j; + always @* begin + max_n_tiles_comb_fallback = 16'h0; + for (j = 0; j < N_SLOTS; j = j + 1) + if (n_tiles_masked[j] > max_n_tiles_comb_fallback) + max_n_tiles_comb_fallback = n_tiles_masked[j]; + end + always @(posedge clk) begin + if (rst) max_n_tiles_reg <= 16'h0; + else max_n_tiles_reg <= max_n_tiles_comb_fallback; + end + end + endgenerate + + localparam ST_IDLE = 1'd0; + localparam ST_FETCH = 1'd1; + reg state; + + reg pf_start; + reg [ADDR_WIDTH-1:0] pf_addr; + wire pf_busy, pf_done; + wire signed [DATA_WIDTH*P_IN-1:0] pf_tile; + + prefetch_engine #( + .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ADDR_WIDTH(ADDR_WIDTH) + ) u_pf ( + .clk(clk), .rst(rst), + .fetch_start(pf_start), .w_addr(pf_addr), + .fetch_busy(pf_busy), .fetch_done(pf_done), .tile_w(pf_tile), + .mem_req(mem_req), .mem_wr(mem_wr), .mem_addr(mem_addr), .mem_wdata(mem_wdata), + .mem_lb_n(mem_lb_n), .mem_ub_n(mem_ub_n), + .mem_rdata(mem_rdata), .mem_ready(mem_ready) + ); + + reg fill_we_reg; + reg [TIW-1:0] fill_addr_reg; + reg [DATA_WIDTH*P_IN-1:0] fill_data_reg; + assign fill_we = fill_we_reg; + assign fill_addr = fill_addr_reg; + assign fill_data = fill_data_reg; + + always @(posedge clk) begin + if (rst) begin + resident_tag <= {ADDR_WIDTH{1'b1}}; // sentinel: matches no real x_base at reset + resident_count <= {CNTW{1'b0}}; + state <= ST_IDLE; + pf_start <= 1'b0; + fill_we_reg <= 1'b0; + end else begin + pf_start <= 1'b0; + fill_we_reg <= 1'b0; + + // latch a completed fetch into the replicated activation + // memory's broadcast fill port + if (pf_done) begin + fill_we_reg <= 1'b1; + fill_addr_reg <= resident_count[TIW-1:0]; // valid: gated < max_n_tiles <= MAX_TILES + fill_data_reg <= pf_tile; + resident_count <= resident_count + 1'b1; + end + + // refill trigger: the reference slot wants a DIFFERENT tag, + // and the fetch engine is genuinely idle (never interrupt an + // in-flight fetch -- same discipline as memory_manager.v's + // own pf_pending guard, ERR-0006). Stays in ST_IDLE (not + // ST_FETCH): only updates resident_tag/resident_count here; + // the ST_IDLE case below is what actually issues pf_start, + // reading the NEW resident_tag starting next cycle -- this + // path must NOT itself jump to ST_FETCH without a matching + // pf_start, or the engine would sit in ST_FETCH forever + // waiting for a pf_done that was never triggered. + if (desired_valid && (desired_x_base != resident_tag) && !pf_busy && (state == ST_IDLE)) begin + resident_tag <= desired_x_base; + resident_count <= {CNTW{1'b0}}; + end + + case (state) + ST_IDLE: begin + // stay idle: fetching further tiles for the CURRENT + // tag (if any active slot still needs more) is + // handled below, symmetric to the refill case. + if (!pf_busy && !pf_start && (resident_count < max_n_tiles_reg) && + desired_valid && (desired_x_base == resident_tag)) begin + pf_start <= 1'b1; + pf_addr <= resident_tag + (resident_count * P_IN[ADDR_WIDTH-1:0]); + state <= ST_FETCH; + end + end + ST_FETCH: begin + if (pf_done) begin + // resident_count already bumped above this cycle; + // decide whether more remain once back in IDLE. + state <= ST_IDLE; + end + end + default: state <= ST_IDLE; + endcase + end + end + +endmodule diff --git a/hardware/v2/nms/rtl/nms_dataflow_core_sdram_fast.v b/hardware/v2/nms/rtl/nms_dataflow_core_sdram_fast.v new file mode 100644 index 0000000..33c2158 --- /dev/null +++ b/hardware/v2/nms/rtl/nms_dataflow_core_sdram_fast.v @@ -0,0 +1,325 @@ +`timescale 1ns/1ps + +// ================================================================ +// Neural Memory System (NMS) -- STEP8 full integration, mirrors +// hardware/v2/rtl/dataflow_core.v's own scope exactly (M6 Dependency +// Manager -> M5 Neural Director -> N_SLOTS x (memory manager + neural +// processor)), but replaces the M4 memory_manager.v + +// activation_cache.v cluster with the NMS's own decided pieces +// (DEC-0019/DEC-0020): +// - nms_activation_replicated.v: N_SLOTS private full-vector +// activation copies, broadcast-filled by... +// - nms_activation_fill_ctrl.v: the shared dedup/fetch controller +// (single logical tag, same honest thrash-under-interleaved- +// different-x_base limitation as the superseded activation_cache.v) +// - nms_weight_packed.v: N_SLOTS private, per-MAC-lane packed weight +// copies (never shared, no arbitration needed) +// - nms_memory_manager.v: per-slot job FSM, reads directly from the +// two SRAMs above instead of double-buffering 2 banks (the whole +// vector is resident, not just 2 tiles worth) +// +// hardware/v2/rtl/dependency_manager.v and neural_director.v are +// REUSED VERBATIM, unmodified -- the node-registration and slot- +// dispatch protocol did not change at all; only what happens between +// "job dispatched to a slot" and "job_done" changed. +// +// Memory Backend Interface: exposed N_SLOTS+1 wide exactly like +// dataflow_core.v (indices [0,N_SLOTS) = per-slot memory managers' +// own weight-fetch+result-write port, index [N_SLOTS] = the shared +// activation fill controller's own port) -- arbitrated one level up, +// reusing hardware/v2/rtl/slot_mem_arbiter.v unchanged. +// +// STEP16 Phase 5: forked from nms_dataflow_core_dual32.v (STEP15's +// own dual-chip-32-bit variant) with ONLY the wide weight-fetch port +// widened from 32 to 64 bits (MEM_DATA_WIDTH=64 in the per-slot +// nms_memory_manager_stream_wide instance below) -- the natural +// P_IN*DATA_WIDTH/16=4-word SDRAM burst identified in Phase 1 means +// ONE mem_req now fetches exactly one whole tile (WORDS_PER_TILE=1), +// same as the dual32 case fetched one whole tile per 32-bit request. +// Everything else (activation path, dependency manager, neural +// director, per-slot neural_processor) is BYTE-FOR-BYTE UNCHANGED -- +// per the governing spec's own "do not create an artificial +// benchmark" instruction, only the piece under test (weight-fetch +// physical memory) differs from the validated dual32 baseline. +// ================================================================ + +module nms_dataflow_core_sdram_fast #( + parameter DATA_WIDTH = 8, + parameter P_IN = 8, + parameter ACC_WIDTH = 32, + parameter ADDR_WIDTH = 26, + parameter N_SLOTS = 4, + parameter N_NODES = 16, + parameter MAX_DEPS = 4, + parameter QUEUE_DEPTH = 8, + parameter MAX_TILES = 16, + parameter PREFETCH_DISTANCE = 8, + parameter TIW = (MAX_TILES <= 1) ? 1 : $clog2(MAX_TILES), + // Must match nms_memory_manager.v's/nms_activation_fill_ctrl.v's + // own CNTW exactly -- this top-level wire connecting the two was + // left at the narrower TIW after those modules were widened, + // silently truncating resident_count's real value (16) back down + // to 0 right when it should have reached MAX_TILES, deadlocking + // the very last tile of any n_tiles==MAX_TILES job forever (found + // via simulation: D-Stress's real 16-tile neurons hung 1 tile + // short, act_resident_count visibly reset to 0 the exact cycle it + // should have become 16). + parameter CNTW = $clog2(MAX_TILES+1) +)( + input wire clk, + input wire rst, + + input wire reg_valid, + output wire reg_ready, + input wire [$clog2(N_NODES)-1:0] reg_node_id, + input wire [$clog2(MAX_DEPS+1)-1:0] reg_required, + input wire [MAX_DEPS*$clog2(N_NODES)-1:0] reg_producer_ids, + input wire [ADDR_WIDTH-1:0] reg_x_base, + input wire [ADDR_WIDTH-1:0] reg_w_base, + input wire [15:0] reg_n_tiles, + input wire [ADDR_WIDTH-1:0] reg_result_addr, + + // FPGA_DATA_READY: see the assignment site (below u_director) for + // the full design comment. + output wire data_ready, + + output wire [N_SLOTS:0] slot_mem_req, + output wire [N_SLOTS:0] slot_mem_wr, + output wire [ADDR_WIDTH*(N_SLOTS+1)-1:0] slot_mem_addr, + output wire [16*(N_SLOTS+1)-1:0] slot_mem_wdata, + output wire [N_SLOTS:0] slot_mem_lb_n, + output wire [N_SLOTS:0] slot_mem_ub_n, + input wire [16*(N_SLOTS+1)-1:0] slot_mem_rdata, + input wire [N_SLOTS:0] slot_mem_ready, + + // ---- STEP16 Phase 5: wide (64-bit logical) weight-fetch backend + // interface, per slot -- N_SLOTS wide (NOT N_SLOTS+1: the shared + // activation-fill controller stays on the ORIGINAL 16-bit port + // above, unchanged). Arbitrated one level up (slot_mem_arbiter_ + // wide.v, reused unchanged at DATA_WIDTH=64) down to the real + // SDRAM physical interface (sdram_weight_backend.v). ---- + output wire [N_SLOTS-1:0] wide_slot_mem_req, + output wire [ADDR_WIDTH*N_SLOTS-1:0] wide_slot_mem_addr, + input wire [64*N_SLOTS-1:0] wide_slot_mem_rdata, + input wire [N_SLOTS-1:0] wide_slot_mem_ready +); + + localparam NODE_IDW = $clog2(N_NODES); + + wire dm_ready_valid; + wire dm_ready_ready; + wire [NODE_IDW-1:0] dm_ready_node_id; + wire [ADDR_WIDTH-1:0] dm_ready_x_base, dm_ready_w_base, dm_ready_result_addr; + wire [15:0] dm_ready_n_tiles; + + wire dm_producer_done_valid; + wire [NODE_IDW-1:0] dm_producer_done_node_id; + wire dm_any_pending; + + dependency_manager_fast #( + .N_NODES(N_NODES), .MAX_DEPS(MAX_DEPS), .ADDR_WIDTH(ADDR_WIDTH) + ) u_dep_mgr ( + .clk(clk), .rst(rst), + .reg_valid(reg_valid), .reg_ready(reg_ready), .reg_node_id(reg_node_id), + .reg_required(reg_required), .reg_producer_ids(reg_producer_ids), + .reg_x_base(reg_x_base), .reg_w_base(reg_w_base), .reg_n_tiles(reg_n_tiles), + .reg_result_addr(reg_result_addr), + .producer_done_valid(dm_producer_done_valid), .producer_done_node_id(dm_producer_done_node_id), + .ready_valid(dm_ready_valid), .ready_ready(dm_ready_ready), .ready_node_id(dm_ready_node_id), + .ready_x_base(dm_ready_x_base), .ready_w_base(dm_ready_w_base), + .ready_n_tiles(dm_ready_n_tiles), .ready_result_addr(dm_ready_result_addr), + .any_pending(dm_any_pending) + ); + + wire [15:0] dm_ready_node_id_ext = {{(16-NODE_IDW){1'b0}}, dm_ready_node_id}; + + wire [N_SLOTS-1:0] dir_slot_job_start; + wire [ADDR_WIDTH*N_SLOTS-1:0] dir_slot_x_base, dir_slot_w_base, dir_slot_result_addr; + wire [16*N_SLOTS-1:0] dir_slot_n_tiles, dir_slot_node_id; + wire [N_SLOTS-1:0] dir_slot_job_done; + wire dir_job_out_done; + wire [$clog2(N_SLOTS)-1:0] dir_job_out_slot; + wire [3:0] dir_state; + wire dir_error; + wire dir_queue_empty; + + neural_director #( + .ADDR_WIDTH(ADDR_WIDTH), .N_SLOTS(N_SLOTS), .QUEUE_DEPTH(QUEUE_DEPTH) + ) u_director ( + .clk(clk), .rst(rst), + .job_in_valid(dm_ready_valid), .job_in_ready(dm_ready_ready), + .job_in_x_base(dm_ready_x_base), .job_in_w_base(dm_ready_w_base), + .job_in_n_tiles(dm_ready_n_tiles), .job_in_result_addr(dm_ready_result_addr), + .job_in_node_id(dm_ready_node_id_ext), + .slot_job_start(dir_slot_job_start), .slot_x_base(dir_slot_x_base), .slot_w_base(dir_slot_w_base), + .slot_n_tiles(dir_slot_n_tiles), .slot_result_addr(dir_slot_result_addr), + .slot_node_id(dir_slot_node_id), .slot_job_done(dir_slot_job_done), + .job_out_done(dir_job_out_done), .job_out_slot(dir_job_out_slot), + .dir_state(dir_state), .dir_error(dir_error), .queue_empty(dir_queue_empty) + ); + + // ---- FPGA_DATA_READY: system-idle detection (see decisions.log + // for the full design rationale) ---- + // sys_busy: true while ANY of {a slot is active, the director's + // dispatch queue is non-empty, dependency_manager has a node not + // yet dispatched} holds. data_ready is a sticky level that goes + // HIGH on the busy->idle falling edge (a graph just finished) and + // LOW again the instant any new work starts (registration or + // dispatch) -- self-clearing, no explicit host ACK needed. Correct + // ONLY if the host finishes registering every node of a graph + // before the first one completes (documented assumption, see + // decisions.log) -- registration (microseconds over SPI) is far + // faster than per-neuron compute (~195 real measured cycles) for + // every workload this project has characterized. + wire sys_busy = (|job_active) || (!dir_queue_empty) || dm_any_pending; + reg sys_busy_prev; + reg data_ready_reg; + always @(posedge clk) begin + if (rst) begin + sys_busy_prev <= 1'b0; + data_ready_reg <= 1'b0; + end else begin + sys_busy_prev <= sys_busy; + if (sys_busy) data_ready_reg <= 1'b0; + else if (sys_busy_prev) data_ready_reg <= 1'b1; + end + end + assign data_ready = data_ready_reg; + + wire [15:0] completed_node_id_16 = dir_slot_node_id[dir_job_out_slot*16 +: 16]; + assign dm_producer_done_valid = dir_job_out_done; + assign dm_producer_done_node_id = completed_node_id_16[NODE_IDW-1:0]; + + // ---- NMS memory: shared Activation SRAM (replicated) + private + // Weight SRAM (packed), per DEC-0019/DEC-0020 ---- + wire fill_we; + wire [TIW-1:0] fill_addr; + wire signed [DATA_WIDTH*P_IN-1:0] fill_data; + wire [ADDR_WIDTH-1:0] act_resident_tag; + wire [CNTW-1:0] act_resident_count; + + wire [N_SLOTS-1:0] act_rd_en; + wire [N_SLOTS*TIW-1:0] act_rd_addr_flat; + wire signed [DATA_WIDTH*P_IN*N_SLOTS-1:0] act_rd_data_flat; + + nms_activation_replicated #( + .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .N_SLOTS(N_SLOTS), .MAX_TILES(MAX_TILES) + ) u_act_mem ( + .clk(clk), .rst(rst), + .fill_we(fill_we), .fill_addr(fill_addr), .fill_data(fill_data), + .rd_en(act_rd_en), .rd_addr_flat(act_rd_addr_flat), .rd_data_flat(act_rd_data_flat) + ); + + wire [N_SLOTS-1:0] job_active; + wire [ADDR_WIDTH*N_SLOTS-1:0] job_x_base_flat; + wire [16*N_SLOTS-1:0] job_n_tiles_flat; + + nms_activation_fill_ctrl_v3_n16 #( + .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .N_SLOTS(N_SLOTS), .ADDR_WIDTH(ADDR_WIDTH), .MAX_TILES(MAX_TILES) + ) u_act_fill ( + .clk(clk), .rst(rst), + .job_active(job_active), .x_base_flat(job_x_base_flat), .n_tiles_flat(job_n_tiles_flat), + .resident_tag(act_resident_tag), .resident_count(act_resident_count), + .fill_we(fill_we), .fill_addr(fill_addr), .fill_data(fill_data), + .mem_req(slot_mem_req[N_SLOTS]), .mem_wr(slot_mem_wr[N_SLOTS]), + .mem_addr(slot_mem_addr[N_SLOTS*ADDR_WIDTH +: ADDR_WIDTH]), + .mem_wdata(slot_mem_wdata[N_SLOTS*16 +: 16]), + .mem_lb_n(slot_mem_lb_n[N_SLOTS]), .mem_ub_n(slot_mem_ub_n[N_SLOTS]), + .mem_rdata(slot_mem_rdata[N_SLOTS*16 +: 16]), .mem_ready(slot_mem_ready[N_SLOTS]) + ); + + wire [N_SLOTS-1:0] wgt_fill_we; + wire [N_SLOTS*TIW-1:0] wgt_fill_addr_flat; + wire signed [DATA_WIDTH*P_IN*N_SLOTS-1:0] wgt_fill_data_flat; + wire [N_SLOTS-1:0] wgt_rd_en; + wire [N_SLOTS*TIW-1:0] wgt_rd_addr_flat; + wire signed [DATA_WIDTH*P_IN*N_SLOTS-1:0] wgt_rd_data_flat; + + nms_weight_packed #( + .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .N_SLOTS(N_SLOTS), .MAX_TILES(MAX_TILES) + ) u_wgt_mem ( + .clk(clk), .rst(rst), + .fill_we(wgt_fill_we), .fill_addr_flat(wgt_fill_addr_flat), .fill_data_flat(wgt_fill_data_flat), + .rd_en(wgt_rd_en), .rd_addr_flat(wgt_rd_addr_flat), .rd_data_flat(wgt_rd_data_flat) + ); + + genvar g; + generate + for (g = 0; g < N_SLOTS; g = g + 1) begin : GEN_SLOT + + wire mm_operand_valid, mm_operand_ready; + wire signed [DATA_WIDTH*P_IN-1:0] mm_input_data, mm_weight_data; + wire mm_tile_last; + wire mm_result_valid, mm_result_ready; + wire signed [DATA_WIDTH-1:0] mm_result_data; + + nms_memory_manager_stream_wide #( + .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ADDR_WIDTH(ADDR_WIDTH), .MAX_TILES(MAX_TILES), + .PREFETCH_DISTANCE(PREFETCH_DISTANCE), .MEM_DATA_WIDTH(64) + ) u_mm ( + .clk(clk), .rst(rst), + .job_start(dir_slot_job_start[g]), + .x_base(dir_slot_x_base[g*ADDR_WIDTH +: ADDR_WIDTH]), + .w_base(dir_slot_w_base[g*ADDR_WIDTH +: ADDR_WIDTH]), + .n_tiles(dir_slot_n_tiles[g*16 +: 16]), + .result_addr(dir_slot_result_addr[g*ADDR_WIDTH +: ADDR_WIDTH]), + .job_done(dir_slot_job_done[g]), + .operand_valid(mm_operand_valid), .operand_ready(mm_operand_ready), + .input_data(mm_input_data), .weight_data(mm_weight_data), .tile_last(mm_tile_last), + .result_valid(mm_result_valid), .result_ready(mm_result_ready), .result_data(mm_result_data), + .job_active(job_active[g]), + .job_x_base(job_x_base_flat[g*ADDR_WIDTH +: ADDR_WIDTH]), + .job_n_tiles(job_n_tiles_flat[g*16 +: 16]), + .act_resident_tag(act_resident_tag), .act_resident_count(act_resident_count), + .act_rd_en(act_rd_en[g]), + .act_rd_addr(act_rd_addr_flat[g*TIW +: TIW]), + .act_rd_data(act_rd_data_flat[g*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN]), + .wgt_fill_we(wgt_fill_we[g]), + .wgt_fill_addr(wgt_fill_addr_flat[g*TIW +: TIW]), + .wgt_fill_data(wgt_fill_data_flat[g*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN]), + .wgt_rd_en(wgt_rd_en[g]), + .wgt_rd_addr(wgt_rd_addr_flat[g*TIW +: TIW]), + .wgt_rd_data(wgt_rd_data_flat[g*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN]), + .mem_req(slot_mem_req[g]), .mem_wr(slot_mem_wr[g]), + .mem_addr(slot_mem_addr[g*ADDR_WIDTH +: ADDR_WIDTH]), + .mem_wdata(slot_mem_wdata[g*16 +: 16]), + .mem_lb_n(slot_mem_lb_n[g]), .mem_ub_n(slot_mem_ub_n[g]), + .mem_rdata(slot_mem_rdata[g*16 +: 16]), .mem_ready(slot_mem_ready[g]), + .wide_mem_req(wide_slot_mem_req[g]), + .wide_mem_addr(wide_slot_mem_addr[g*ADDR_WIDTH +: ADDR_WIDTH]), + .wide_mem_rdata(wide_slot_mem_rdata[g*64 +: 64]), + .wide_mem_ready(wide_slot_mem_ready[g]) + ); + + reg job_valid_np; + wire job_ready_np; + wire result_valid_np; + wire signed [DATA_WIDTH-1:0] result_data_np; + wire [3:0] np_state; + wire np_error; + + neural_processor #( + .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH) + ) u_np ( + .clk(clk), .rst(rst), + .job_valid(job_valid_np), .job_ready(job_ready_np), + .job_node_id(16'h0), .job_bias(8'sd0), .job_activation(2'd1), + .operand_valid(mm_operand_valid), .operand_ready(mm_operand_ready), + .input_data(mm_input_data), .weight_data(mm_weight_data), .tile_last(mm_tile_last), + .result_valid(result_valid_np), .result_ready(mm_result_ready), + .result_data(result_data_np), .result_node_id(), + .np_state(np_state), .np_error(np_error) + ); + assign mm_result_valid = result_valid_np; + assign mm_result_data = result_data_np; + + always @(posedge clk) begin + if (rst) job_valid_np <= 1'b0; + else if (dir_slot_job_start[g]) job_valid_np <= 1'b1; + else if (job_valid_np && job_ready_np) job_valid_np <= 1'b0; + end + + end + endgenerate + +endmodule diff --git a/hardware/v2/nms/rtl/nms_neural_multiprocessor_sdram_openrow_fast.v b/hardware/v2/nms/rtl/nms_neural_multiprocessor_sdram_openrow_fast.v new file mode 100644 index 0000000..023c59b --- /dev/null +++ b/hardware/v2/nms/rtl/nms_neural_multiprocessor_sdram_openrow_fast.v @@ -0,0 +1,171 @@ +`timescale 1ns/1ps + +// ================================================================ +// Neural Memory System (NMS) -- STEP19 real hardware-facing top level. +// +// SINGLE EXTERNAL SDRAM ONLY. Forked from nms_neural_multiprocessor_ +// sdram_pack128.v (STEP18) with the ONE change this step's own +// governing spec mandates: the real hardware/v1/rtl/psram_controller.v +// + memory_interface.v pairing (activation-fill + result-writeback, +// 16-bit) is REMOVED from the V2 physical path entirely and replaced +// by sdram_unified_backend.v's own AR port, sharing the SAME single +// physical AS4C4M16SA-6TIN SDRAM chip and the SAME single sdram_ +// controller.v instance the weight-fetch path (W port) already uses. +// +// slot_mem_arbiter.v (16-bit, activation+result) and slot_mem_ +// arbiter_wide.v (64-bit, weight) are BOTH reused completely +// UNCHANGED -- their own downstream ports now both terminate at +// sdram_unified_backend.v instead of two separate physical chains. +// nms_dataflow_core_sdram.v, nms_activation_fill_ctrl_v3.v, nms_ +// memory_manager_stream_wide.v, weight_prefetch_engine_wide.v, and +// neural_processor.v are ALL byte-for-byte unchanged -- this is a +// pure memory-side substitution, per the governing spec's own +// explicit instruction. +// +// V1 (hardware/v1/**) is untouched -- psram_controller.v and memory_ +// interface.v simply are no longer INSTANTIATED by this top-level; +// neither file was modified, and V1's own golden-reference status is +// unaffected. +// +// Real pin count (weight+activation+result, ALL through ONE chip): +// 2(BA)+12(A)+1(CKE)+1(CS#)+1(RAS#)+1(CAS#)+1(WE#)+2(DQM)+16(DQ) = 37 +// pins total -- the SAME 37 pins the weight-only path already used in +// STEP16-18 (no NEW physical SDRAM pins are needed to add activation/ +// result traffic, since it shares the identical physical bus). +// ================================================================ + +module nms_neural_multiprocessor_sdram_openrow_fast #( + parameter DATA_WIDTH = 8, + parameter P_IN = 8, + parameter ACC_WIDTH = 32, + parameter ADDR_WIDTH = 26, + parameter N_SLOTS = 2, + parameter N_NODES = 16, + parameter MAX_DEPS = 4, + parameter QUEUE_DEPTH = 8, + parameter MAX_TILES = 16, + parameter PREFETCH_DISTANCE = 8, + parameter CLK_FREQ_MHZ = 80 +)( + input wire clk, + input wire rst, + + input wire reg_valid, + output wire reg_ready, + input wire [$clog2(N_NODES)-1:0] reg_node_id, + input wire [$clog2(MAX_DEPS+1)-1:0] reg_required, + input wire [MAX_DEPS*$clog2(N_NODES)-1:0] reg_producer_ids, + input wire [ADDR_WIDTH-1:0] reg_x_base, + input wire [ADDR_WIDTH-1:0] reg_w_base, + input wire [15:0] reg_n_tiles, + input wire [ADDR_WIDTH-1:0] reg_result_addr, + + // FPGA_DATA_READY: system-idle sticky flag, see nms_dataflow_core_sdram.v + output wire data_ready, + + // ---- STEP19: ONE physical SDRAM interface, ALL traffic + // (weights + activations + results) ---- + output wire sdram_cke, + output wire sdram_cs_n, + output wire sdram_ras_n, + output wire sdram_cas_n, + output wire sdram_we_n, + output wire [1:0] sdram_ba, + output wire [12:0] sdram_a, + inout wire [15:0] sdram_dq, + output wire [1:0] sdram_dqm +); + + wire [N_SLOTS:0] slot_mem_req, slot_mem_wr; + wire [ADDR_WIDTH*(N_SLOTS+1)-1:0] slot_mem_addr; + wire [16*(N_SLOTS+1)-1:0] slot_mem_wdata, slot_mem_rdata; + wire [N_SLOTS:0] slot_mem_lb_n, slot_mem_ub_n; + wire [N_SLOTS:0] slot_mem_ready; + + wire [N_SLOTS-1:0] wide_slot_mem_req; + wire [ADDR_WIDTH*N_SLOTS-1:0] wide_slot_mem_addr; + wire [64*N_SLOTS-1:0] wide_slot_mem_rdata; + wire [N_SLOTS-1:0] wide_slot_mem_ready; + + nms_dataflow_core_sdram_fast #( + .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH), .ADDR_WIDTH(ADDR_WIDTH), + .N_SLOTS(N_SLOTS), .N_NODES(N_NODES), .MAX_DEPS(MAX_DEPS), .QUEUE_DEPTH(QUEUE_DEPTH), + .MAX_TILES(MAX_TILES), .PREFETCH_DISTANCE(PREFETCH_DISTANCE) + ) u_dataflow_core ( + .clk(clk), .rst(rst), + .reg_valid(reg_valid), .reg_ready(reg_ready), .reg_node_id(reg_node_id), + .reg_required(reg_required), .reg_producer_ids(reg_producer_ids), + .reg_x_base(reg_x_base), .reg_w_base(reg_w_base), .reg_n_tiles(reg_n_tiles), + .reg_result_addr(reg_result_addr), + .data_ready(data_ready), + .slot_mem_req(slot_mem_req), .slot_mem_wr(slot_mem_wr), .slot_mem_addr(slot_mem_addr), + .slot_mem_wdata(slot_mem_wdata), .slot_mem_lb_n(slot_mem_lb_n), .slot_mem_ub_n(slot_mem_ub_n), + .slot_mem_rdata(slot_mem_rdata), .slot_mem_ready(slot_mem_ready), + .wide_slot_mem_req(wide_slot_mem_req), .wide_slot_mem_addr(wide_slot_mem_addr), + .wide_slot_mem_rdata(wide_slot_mem_rdata), .wide_slot_mem_ready(wide_slot_mem_ready) + ); + + // ---- AR: activation-fill (shared, 1 port) + per-slot result + // writeback (N_SLOTS ports), arbitrated exactly as before ---- + wire arb_m_req, arb_m_wr; + wire [ADDR_WIDTH-1:0] arb_m_addr; + wire [15:0] arb_m_wdata; + wire arb_m_lb_n, arb_m_ub_n; + wire [15:0] arb_m_rdata; + wire arb_m_ready; + + slot_mem_arbiter #( + .ADDR_WIDTH(ADDR_WIDTH), .N_PORTS(N_SLOTS+1) + ) u_arbiter ( + .clk(clk), .rst(rst), + .s_req(slot_mem_req), .s_wr(slot_mem_wr), .s_addr(slot_mem_addr), + .s_wdata(slot_mem_wdata), .s_lb_n(slot_mem_lb_n), .s_ub_n(slot_mem_ub_n), + .s_rdata(slot_mem_rdata), .s_ready(slot_mem_ready), + .m_req(arb_m_req), .m_wr(arb_m_wr), .m_addr(arb_m_addr), .m_wdata(arb_m_wdata), + .m_lb_n(arb_m_lb_n), .m_ub_n(arb_m_ub_n), + .m_rdata(arb_m_rdata), .m_ready(arb_m_ready) + ); + + // ---- W: weight fetch (N_SLOTS ports), arbitrated exactly as + // before -- weight fetch never writes, same tie-off convention + // as STEP16-18 ---- + wire [N_SLOTS-1:0] wide_s_wr = {N_SLOTS{1'b0}}; + wire [64*N_SLOTS-1:0] wide_s_wdata = {(64*N_SLOTS){1'b0}}; + wire [N_SLOTS-1:0] wide_s_lb_n = {N_SLOTS{1'b0}}; + wire [N_SLOTS-1:0] wide_s_ub_n = {N_SLOTS{1'b0}}; + + wire wide_arb_m_req, wide_arb_m_wr; + wire [ADDR_WIDTH-1:0] wide_arb_m_addr; + wire [63:0] wide_arb_m_wdata; + wire wide_arb_m_lb_n, wide_arb_m_ub_n; + wire [63:0] wide_arb_m_rdata; + wire wide_arb_m_ready; + + slot_mem_arbiter_wide #( + .ADDR_WIDTH(ADDR_WIDTH), .N_PORTS(N_SLOTS), .DATA_WIDTH(64) + ) u_arbiter_wide ( + .clk(clk), .rst(rst), + .s_req(wide_slot_mem_req), .s_wr(wide_s_wr), .s_addr(wide_slot_mem_addr), + .s_wdata(wide_s_wdata), .s_lb_n(wide_s_lb_n), .s_ub_n(wide_s_ub_n), + .s_rdata(wide_slot_mem_rdata), .s_ready(wide_slot_mem_ready), + .m_req(wide_arb_m_req), .m_wr(wide_arb_m_wr), .m_addr(wide_arb_m_addr), .m_wdata(wide_arb_m_wdata), + .m_lb_n(wide_arb_m_lb_n), .m_ub_n(wide_arb_m_ub_n), + .m_rdata(wide_arb_m_rdata), .m_ready(wide_arb_m_ready) + ); + + // ---- STEP19: ONE physical SDRAM backend, both W and AR ports ---- + sdram_unified_backend_openrow #( + .ADDR_WIDTH(ADDR_WIDTH), .CLK_FREQ_MHZ(CLK_FREQ_MHZ) + ) u_sdram_backend ( + .clk(clk), .rst(rst), + .w_req(wide_arb_m_req), .w_addr(wide_arb_m_addr), + .w_rdata(wide_arb_m_rdata), .w_ready(wide_arb_m_ready), + .ar_req(arb_m_req), .ar_wr(arb_m_wr), .ar_addr(arb_m_addr), .ar_wdata(arb_m_wdata), + .ar_lb_n(arb_m_lb_n), .ar_ub_n(arb_m_ub_n), + .ar_rdata(arb_m_rdata), .ar_ready(arb_m_ready), + .sdram_cke(sdram_cke), .sdram_cs_n(sdram_cs_n), .sdram_ras_n(sdram_ras_n), + .sdram_cas_n(sdram_cas_n), .sdram_we_n(sdram_we_n), + .sdram_ba(sdram_ba), .sdram_a(sdram_a), .sdram_dq(sdram_dq), .sdram_dqm(sdram_dqm) + ); + +endmodule diff --git a/hardware/v2/nms/sim/tb_fpga_neural_v2_top_openrow_fast_smoke.v b/hardware/v2/nms/sim/tb_fpga_neural_v2_top_openrow_fast_smoke.v new file mode 100644 index 0000000..945f439 --- /dev/null +++ b/hardware/v2/nms/sim/tb_fpga_neural_v2_top_openrow_fast_smoke.v @@ -0,0 +1,281 @@ +`timescale 1ns/1ps + +// ================================================================ +// FPGA-Neural V2 -- board-level top INTEGRATION SMOKE TEST (STEP20) +// +// Proves the NEW STEP20 wiring end-to-end: real SPI transactions (bit- +// banged, mode 0) drive job registration THROUGH spi_host_bridge.v, +// through the real compute+memory pipeline (byte-for-byte identical +// to the already-verified STEP19 nms_neural_multiprocessor_sdram_ +// unified.v internals) via the NEW 2-level host-arb AR arbitration, +// down to the SAME single sdram_unified_backend/sdram_controller/ +// AS4C4M16SA-6TIN chain -- checked against a real, backdoor-peeked +// SDRAM result. This is NOT a replacement for the STEP19 full 256- +// neuron D-Stress regression (already reconfirmed bit-exact using the +// trusted tool, see errors.log ERR-0024) -- it exists purely to +// validate the NEW pieces this step adds (SPI bridge, PLL-bypass +// clocking, reset_sync, the extra host-arb arbiter level) that +// D-Stress's own tight, back-to-back dispatch loop never exercises: +// realistic, WIDELY TIME-SEPARATED job pacing, as a real host would +// actually issue over SPI. +// +// STATUS (STEP20, ERR-0025 Part B): FIXED. Root cause: nms_weight_ +// packed.v / nms_activation_replicated.v used a REGISTERED read (one +// full extra clock of latency) while nms_memory_manager_stream_wide.v's +// own read-ahead pipeline (`rd_pending`) assumes a COMBINATIONAL read +// (issue this cycle, data valid to capture next cycle). A busy multi- +// tile job's own prefetch lead time always absorbs the extra cycle +// invisibly; an uncontested single-tile job's first (only) tile has +// zero such margin and captured stale/zero data permanently. Fixed by +// making both SRAMs' reads combinational (with an explicit same-cycle +// fill/read bypass for the one hazard a combinational read alone would +// still miss). Verified: this test now passes, AND the STEP19 D-Stress +// regression (N=2 49788 cycles, N=4 49771 cycles, both 256/256 +// bit-exact) is UNCHANGED -- cycle-for-cycle identical to before the +// fix, since D-Stress's own prefetch margin never depended on the +// extra (buggy) register cycle in the first place. +// +// Six scenarios below, using disjoint SDRAM regions so none interfere: +// A) two jobs, realistic wide SPI pacing (the original failing case) +// B) a single job dispatched alone (twice: neuron0 alone, neuron1 alone) +// C) two jobs back-to-back (minimal CS gap) +// D) two jobs with a large gap (same as A, kept as its own named case) +// G) parametric sweep across several distinct inter-job gaps, proving +// the fix does not depend on any particular cycle count +// +// Weights/activations are preloaded via the same backdoor poke +// convention already used by tb_nms_dstress_sdram_unified.v (direct +// writes into u_sdram.mem[]) -- only JOB REGISTRATION goes through the +// real, physical SPI path, since that is the actual integration +// surface under test. `SIM bypasses the (unsimulatable) EHXPLLL +// primitive inside ecp5_pll_sys_clk.v with a direct pass-through, per +// that module's own documented, declared limitation. +// ================================================================ + +`define SIM + +module tb_fpga_neural_v2_top_smoke; + + localparam ADDR_WIDTH = 26; // AS4C32M16SA memory upgrade + localparam N_SLOTS = 2; + localparam N_NODES = 16; + localparam MAX_DEPS = 4; + + reg osc_clk = 0; + // Driven at the REAL 64MHz clk_sys rate (not the board's own 16MHz + // osc_clk) -- under the `SIM PLL bypass (clk_sys = osc_clk + // directly, see ecp5_pll_sys_clk.v), this reproduces the real + // board's actual system-clock rate for this test, matching + // CLK_FREQ_MHZ(64) above (a previous draft left both this and the + // controller's own CLK_FREQ_MHZ at a stale, pre-freeze value). + always #7.8125 osc_clk = ~osc_clk; // 64MHz + + reg ext_rst_n = 0; + + reg spi_sclk = 0, spi_mosi = 0, spi_cs_n = 1; + wire spi_miso; + + wire sdram_cke, sdram_cs_n, sdram_ras_n, sdram_cas_n, sdram_we_n; + wire [1:0] sdram_ba; + wire [12:0] sdram_a; + wire [15:0] sdram_dq; + wire [1:0] sdram_dqm; + wire pll_locked; + + fpga_neural_v2_top_openrow_fast #( + .ADDR_WIDTH(ADDR_WIDTH), .N_SLOTS(N_SLOTS), .N_NODES(N_NODES), .MAX_DEPS(MAX_DEPS), + .CLK_FREQ_MHZ(64) + ) dut ( + .osc_clk(osc_clk), .ext_rst_n(ext_rst_n), + .spi_sclk(spi_sclk), .spi_mosi(spi_mosi), .spi_miso(spi_miso), .spi_cs_n(spi_cs_n), + .sdram_cke(sdram_cke), .sdram_cs_n(sdram_cs_n), .sdram_ras_n(sdram_ras_n), + .sdram_cas_n(sdram_cas_n), .sdram_we_n(sdram_we_n), + .sdram_ba(sdram_ba), .sdram_a(sdram_a), .sdram_dq(sdram_dq), .sdram_dqm(sdram_dqm), + .pll_locked(pll_locked) + ); + + sdram_model #(.CLK_FREQ_MHZ(64)) u_sdram ( + .clk(dut.clk_sys), .cke(sdram_cke), .cs_n(sdram_cs_n), .ras_n(sdram_ras_n), + .cas_n(sdram_cas_n), .we_n(sdram_we_n), .ba(sdram_ba), .a(sdram_a), + .dq(sdram_dq), .dqm(sdram_dqm) + ); + + function automatic signed [7:0] relu_sat(input signed [31:0] acc); + begin + if (acc < 0) relu_sat = 8'sd0; + else if (acc > 127) relu_sat = 8'sd127; + else relu_sat = acc[7:0]; + end + endfunction + + task poke_byte(input [ADDR_WIDTH-1:0] byte_addr, input signed [7:0] val); + reg [24:0] word_addr; + begin + word_addr = byte_addr[ADDR_WIDTH-1:1]; + if (byte_addr[0] == 1'b0) u_sdram.mem[word_addr][7:0] = val; + else u_sdram.mem[word_addr][15:8] = val; + end + endtask + + function automatic signed [7:0] peek_byte(input [ADDR_WIDTH-1:0] byte_addr); + reg [24:0] word_addr; + begin + word_addr = byte_addr[ADDR_WIDTH-1:1]; + peek_byte = (byte_addr[0] == 1'b0) ? u_sdram.mem[word_addr][7:0] : u_sdram.mem[word_addr][15:8]; + end + endfunction + + // ---- SPI master BFM (matches spi_host_bridge.v's own protocol, + // same realistic 500ns-bit-period convention as tb_spi_host_ + // bridge.v -- see that module's header on the CDC margin reason) ---- + task spi_byte(input [7:0] tx, output [7:0] rx); + integer i; + begin + rx = 8'h00; + for (i = 7; i >= 0; i = i - 1) begin + spi_mosi = tx[i]; + #200; spi_sclk = 1; #50; rx = {rx[6:0], spi_miso}; #50; spi_sclk = 0; #200; + end + end + endtask + + task write_job(input [3:0] node_id, input [2:0] required, input [15:0] producer_ids, + input [ADDR_WIDTH-1:0] x_base, input [ADDR_WIDTH-1:0] w_base, input [15:0] n_tiles, + input [ADDR_WIDTH-1:0] result_addr); + reg [7:0] rxb; + begin + spi_cs_n = 0; #20; + spi_byte(8'h10, rxb); + spi_byte({4'b0, node_id}, rxb); + spi_byte({5'b0, required}, rxb); + spi_byte(producer_ids[15:8], rxb); + spi_byte(producer_ids[7:0], rxb); + spi_byte({6'b0, x_base[25:24]}, rxb); + spi_byte(x_base[23:16], rxb); + spi_byte(x_base[15:8], rxb); + spi_byte(x_base[7:0], rxb); + spi_byte({6'b0, w_base[25:24]}, rxb); + spi_byte(w_base[23:16], rxb); + spi_byte(w_base[15:8], rxb); + spi_byte(w_base[7:0], rxb); + spi_byte(n_tiles[15:8], rxb); + spi_byte(n_tiles[7:0], rxb); + spi_byte({6'b0, result_addr[25:24]}, rxb); + spi_byte(result_addr[23:16], rxb); + spi_byte(result_addr[15:8], rxb); + spi_byte(result_addr[7:0], rxb); + // hold CS through the reg_valid/reg_ready handshake (may + // need a few extra idle clocks if the target slot is busy) + #2000; + spi_cs_n = 1; #200; + end + endtask + + integer errors, tests; + integer node_ctr; // fresh node_id per sub-test (dependency_manager never reclaims a dispatched id) + + task check_neuron(input [22:0] x_base, input [22:0] w_base, input [22:0] res_addr, + input [255:0] label); + integer k; + reg signed [31:0] acc; + reg signed [7:0] golden, real_y; + begin + acc = 0; + for (k = 0; k < 8; k = k + 1) + acc = acc + peek_byte(x_base + k) * peek_byte(w_base + k); + golden = relu_sat(acc); + real_y = peek_byte(res_addr); + tests = tests + 1; + if (real_y !== golden) begin + errors = errors + 1; + $display("FAIL %0s: real=%0d golden=%0d", label, real_y, golden); + end else begin + $display("PASS %0s: real=%0d golden=%0d", label, real_y, golden); + end + end + endtask + + // One independent, disjoint scratch region per pair-test invocation, + // so scenarios never interfere with each other's SDRAM content: + // x_base=region, w0=region+0x100, w1=region+0x110, res=region+0x200/0x201 + task run_pair(input [22:0] region, input integer gap_ns, input [255:0] label); + reg [22:0] x_base, w0, w1, res0, res1; + integer k, n; + begin + x_base = region; + w0 = region + 26'h100; + w1 = region + 26'h110; + res0 = region + 26'h200; + res1 = region + 26'h201; + + for (k = 0; k < 8; k = k + 1) poke_byte(x_base + k, k[7:0] + 1); + for (n = 0; n < 2; n = n + 1) + for (k = 0; k < 8; k = k + 1) + poke_byte((n == 0 ? w0 : w1) + k, ((n + k) % 4) + 1); + poke_byte(res0, 8'sd0); + poke_byte(res1, 8'sd0); + + write_job(node_ctr[3:0], 3'd0, 16'h0000, x_base, w0, 16'd1, res0); + node_ctr = node_ctr + 1; + if (gap_ns > 0) #gap_ns; + write_job(node_ctr[3:0], 3'd0, 16'h0000, x_base, w1, 16'd1, res1); + node_ctr = node_ctr + 1; + + repeat (3000) @(posedge dut.clk_sys); + + check_neuron(x_base, w0, res0, {label, "-A"}); + check_neuron(x_base, w1, res1, {label, "-B"}); + end + endtask + + // Single, standalone job (scenario B) -- no second job at all. + task run_single(input [22:0] region, input [255:0] label); + reg [22:0] x_base, w0, res0; + integer k; + begin + x_base = region; + w0 = region + 26'h100; + res0 = region + 26'h200; + for (k = 0; k < 8; k = k + 1) poke_byte(x_base + k, k[7:0] + 3); + for (k = 0; k < 8; k = k + 1) poke_byte(w0 + k, ((k) % 3) + 1); + poke_byte(res0, 8'sd0); + + write_job(node_ctr[3:0], 3'd0, 16'h0000, x_base, w0, 16'd1, res0); + node_ctr = node_ctr + 1; + + repeat (3000) @(posedge dut.clk_sys); + check_neuron(x_base, w0, res0, label); + end + endtask + + initial begin + errors = 0; tests = 0; node_ctr = 0; + ext_rst_n = 0; + repeat (20) @(posedge osc_clk); + ext_rst_n = 1; + repeat (10) @(posedge osc_clk); + + wait (dut.u_sdram_backend.u_sdram_ctrl.state == dut.u_sdram_backend.u_sdram_ctrl.S_IDLE); + @(posedge dut.clk_sys); + + // B) single job, alone + run_single(26'h001000, "B-single-neuron0"); + + // A/D) two jobs, realistic wide SPI pacing (~85us worth of SPI + // framing plus an explicit extra gap -- the original failing case) + run_pair(26'h004000, 20000, "A-wide-gap"); + + // C) two jobs back-to-back (minimal CS-high gap between them) + run_pair(26'h007000, 0, "C-back-to-back"); + + // G) parametric sweep across several distinct inter-job gaps + run_pair(26'h00A000, 100, "G-gap100ns"); + run_pair(26'h00D000, 5000, "G-gap5000ns"); + run_pair(26'h010000, 50000, "G-gap50000ns"); + + $display("=== tb_fpga_neural_v2_top_smoke: %0d/%0d PASS ===", tests-errors, tests); + if (errors != 0) $display("*** %0d FAILURES ***", errors); + $finish; + end + +endmodule diff --git a/hardware/v2/nms/sim/tb_nms_dstress_sdram_openrow_fast.v b/hardware/v2/nms/sim/tb_nms_dstress_sdram_openrow_fast.v new file mode 100644 index 0000000..8e25555 --- /dev/null +++ b/hardware/v2/nms/sim/tb_nms_dstress_sdram_openrow_fast.v @@ -0,0 +1,880 @@ +`timescale 1ns/1ps + +// ================================================================ +// FPGA-Neural V2 -- Final Benchmark Campaign (post-M10, real +// end-to-end characterization, docs/v2-description.md §22/§30/§32) +// +// One testbench, compiled once per N_SLOTS configuration (N_SLOTS_CFG +// parameter, overridden at Verilator invocation via -GN_SLOTS_CFG=N), +// running SIX representative workloads back-to-back through the REAL +// neural_multiprocessor.v (M8: dataflow_core + slot_mem_arbiter + the +// real, unmodified V1 PSRAM chain), with: +// - a software "golden" model replicating neural_processor.v's exact +// integer math (sum(x*w) over all tiles, ReLU + INT8 saturate -- +// dataflow_core.v hardcodes bias=0/ACT_RELU for every job, so the +// golden model only needs to replicate that one path) +// - bit-exact verification of EVERY neuron's real result against +// that golden model (peek_byte from the real psram_model backing +// array -- an oracle independent of the RTL under test) +// - real cycle-accounting instrumentation (testbench-only, no RTL +// touched): per-slot busy/idle cycles, shared PSRAM port busy/idle +// cycles, REAL tiles delivered per slot (operand_valid&& +// operand_ready pulses -- one pulse = one whole P_IN-wide tile +// consumed by neural_processor, NOT one byte), director/dependency +// bookkeeping (jobs allocated/completed, ready-queue occupancy, +// WAITING/READY/DISPATCHED node counts, producer-done wakeups) +// +// Workloads (node_id ranges are disjoint across all six so the WHOLE +// campaign runs in ONE continuous simulation -- only ONE real PSRAM +// power-up wait, no reset between phases, closer to real sustained +// operation than resetting between every workload): +// A) Small -- 16 independent neurons, 8 inputs each +// B) Medium -- 64 independent neurons, 32 inputs each +// C) Large -- 128 independent neurons, 128 inputs each +// D) Stress -- 256 independent neurons, 128 inputs each +// E) Multilayer -- 8 layer-1 neurons (RANDOM data, logged seed) feed +// a shared 8-byte hidden vector; 2 layer-2 neurons +// consume that vector (real cross-node data +// forwarding through real PSRAM, real dependency +// wake-up, "shared producer/multiple consumers") +// F) DAG -- 6-node diamond+fan-in graph (A,B independent; C +// dep on A; D dep on B; E dep on BOTH C and D +// [2-hop transitive wake-up]; F dep on A,B,C [mixed +// direct+1-hop, 3 producers]) +// +// All workloads A-D use a REALISTIC dense-layer shape: one shared +// input activation vector, N independent weight vectors (one per +// neuron) -- exactly how a real fully-connected layer's neurons share +// their layer's input. This is not an isolated synthetic microbench. +// +// Verified with Verilator (decisions.log DEC-0004). +// ================================================================ + +// ================================================================ +// STEP11 variant: identical D-Stress workload/golden-model/correctness +// criteria as tb_nms_dstress.v (STEP9's own official benchmark), but +// instantiating nms_neural_multiprocessor_pf (REAL weight prefetch +// engine, weight_prefetch_engine.v) instead of the baseline +// nms_neural_multiprocessor.v, with an added PFD_CFG (PREFETCH_DISTANCE) +// parameter, plus NEW instrumentation (testbench-only, no RTL touched) +// for the two STEP11-mandated metrics that cannot be derived from the +// STEP9 instrumentation alone: +// weight_stall_cycles = cycles a slot is otherwise ready to +// present a tile (activation resident, +// in bounds) but blocked purely because +// tile_idx >= wgt_ready_count +// prefetch_effectiveness = tiles consumed with ZERO such +// weight-blocking cycles beforehand +// (i.e. the weight was ALREADY resident +// the moment the tile became eligible) +// / total tiles consumed +// per STEP11's own explicit metric definitions. +// ================================================================ +module tb #( + parameter N_SLOTS_CFG = 2, + parameter PFD_CFG = 8 +); + + localparam ADDR_WIDTH = 26; // AS4C32M16SA: 25-bit word address + 1 byte-select bit + localparam DATA_WIDTH = 8; + localparam P_IN = 8; + localparam ACC_WIDTH = 32; + // N_NODES must exceed the HIGHEST node_id used by ANY workload + // (node_base + count - 1) -- workload D's own range alone + // (node_base=400, 256 neurons) reaches id 655. An earlier draft + // used N_NODES=512: D's ids silently wrapped (9-bit truncation) + // past id 511, colliding with workload A's already-DISPATCHED + // node 0 (dependency_manager never reclaims dispatched node slots, + // DEC-0008) and deadlocking register_node's reg_ready wait + // forever. A real consequence of DEC-0008's design choice, not an + // RTL bug -- fixed here by sizing N_NODES generously above the + // real id range used below (see decisions.log DEC-0008 and the + // final benchmark report's Limitations section). + localparam N_NODES = 1024; + localparam MAX_DEPS = 8; + localparam QUEUE_DEPTH = 8; + localparam NODE_IDW = $clog2(N_NODES); + localparam CLK_PERIOD = 12.5; // 80 MHz, matches psram_controller's CLK_FREQ_MHZ + + reg clk, rst; + initial begin clk = 1'b0; forever #(CLK_PERIOD/2.0) clk = ~clk; end + + reg reg_valid; + wire reg_ready; + reg [NODE_IDW-1:0] reg_node_id; + reg [$clog2(MAX_DEPS+1)-1:0] reg_required; + reg [MAX_DEPS*NODE_IDW-1:0] reg_producer_ids; + reg [ADDR_WIDTH-1:0] reg_x_base, reg_w_base, reg_result_addr; + reg [15:0] reg_n_tiles; + + // STEP19: ONE physical SDRAM interface. weights, activations, and + // results ALL share this single bus/chip now -- no PSRAM anywhere. + wire sdram_cke, sdram_cs_n, sdram_ras_n, sdram_cas_n, sdram_we_n; + wire [1:0] sdram_ba; + wire [12:0] sdram_a; + wire [15:0] sdram_dq; + wire [1:0] sdram_dqm; + + nms_neural_multiprocessor_sdram_openrow_fast #( + .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH), .ADDR_WIDTH(ADDR_WIDTH), + .N_SLOTS(N_SLOTS_CFG), .N_NODES(N_NODES), .MAX_DEPS(MAX_DEPS), .QUEUE_DEPTH(QUEUE_DEPTH), + .MAX_TILES(16), .PREFETCH_DISTANCE(PFD_CFG), .CLK_FREQ_MHZ(80) + ) u_nmp ( + .clk(clk), .rst(rst), + .reg_valid(reg_valid), .reg_ready(reg_ready), .reg_node_id(reg_node_id), + .reg_required(reg_required), .reg_producer_ids(reg_producer_ids), + .reg_x_base(reg_x_base), .reg_w_base(reg_w_base), .reg_n_tiles(reg_n_tiles), + .reg_result_addr(reg_result_addr), + .sdram_cke(sdram_cke), .sdram_cs_n(sdram_cs_n), .sdram_ras_n(sdram_ras_n), + .sdram_cas_n(sdram_cas_n), .sdram_we_n(sdram_we_n), + .sdram_ba(sdram_ba), .sdram_a(sdram_a), .sdram_dq(sdram_dq), .sdram_dqm(sdram_dqm) + ); + + sdram_model #(.CLK_FREQ_MHZ(80)) u_sdram ( + .clk(clk), .cke(sdram_cke), .cs_n(sdram_cs_n), .ras_n(sdram_ras_n), + .cas_n(sdram_cas_n), .we_n(sdram_we_n), .ba(sdram_ba), .a(sdram_a), + .dq(sdram_dq), .dqm(sdram_dqm) + ); + + // ============================================================ + // STEP19: byte-level backdoor access (test setup/verification + // only) -- weights, activations, AND results now ALL live on the + // single real SDRAM physical interface (u_sdram); there is no + // PSRAM anywhere in this system anymore. poke_byte/peek_byte (used + // by activation+result call sites) and poke_byte_weight/peek_byte + // _weight (used by weight call sites) are now identical in + // implementation -- kept as two names rather than merged, to avoid + // touching every one of their many existing call sites for a + // cosmetic rename; both correctly target the same u_sdram.mem + // backing array via the same byte_addr>>1 / byte_addr[0] pattern. + // ============================================================ + task automatic poke_byte(input [ADDR_WIDTH-1:0] byte_addr, input signed [7:0] val); + reg [24:0] word_addr; + begin + word_addr = byte_addr[ADDR_WIDTH-1:1]; + if (byte_addr[0] == 1'b0) u_sdram.mem[word_addr][7:0] = val; + else u_sdram.mem[word_addr][15:8] = val; + end + endtask + + function automatic signed [7:0] peek_byte(input [ADDR_WIDTH-1:0] byte_addr); + reg [24:0] word_addr; + begin + word_addr = byte_addr[ADDR_WIDTH-1:1]; + peek_byte = (byte_addr[0] == 1'b0) ? u_sdram.mem[word_addr][7:0] : u_sdram.mem[word_addr][15:8]; + end + endfunction + + // sdram_model.v's own `mem` array is flat-indexed by the 25-bit + // word address directly (bank*ROWS*COLS + row*COLS + col, which, + // given ROWS=8192/COLS=1024 are both powers of 2, is numerically + // IDENTICAL to treating the address as one flat 25-bit integer -- + // confirmed against sdram_model.v's own BANKS/ROWS/COLS localparams + // before writing this, not assumed) -- so this is the exact same + // byte_addr>>1 / byte_addr[0] pattern as the original single-chip + // poke_byte/peek_byte above, just against u_sdram.mem instead of + // u_psram.mem. + task automatic poke_byte_weight(input [ADDR_WIDTH-1:0] byte_addr, input signed [7:0] val); + reg [24:0] word_addr; + begin + word_addr = byte_addr[ADDR_WIDTH-1:1]; + if (byte_addr[0] == 1'b0) u_sdram.mem[word_addr][7:0] = val; + else u_sdram.mem[word_addr][15:8] = val; + end + endtask + + function automatic signed [7:0] peek_byte_weight(input [ADDR_WIDTH-1:0] byte_addr); + reg [24:0] word_addr; + begin + word_addr = byte_addr[ADDR_WIDTH-1:1]; + peek_byte_weight = (byte_addr[0] == 1'b0) ? u_sdram.mem[word_addr][7:0] : u_sdram.mem[word_addr][15:8]; + end + endfunction + + // Golden model: exactly replicates neural_processor.v's real path + // through dataflow_core (bias=0, ACT_RELU always -- see + // dataflow_core.v's own hardcoded job_bias/job_activation). + function automatic signed [7:0] relu_sat(input integer acc); + begin + if (acc <= 0) relu_sat = 8'sd0; + else if (acc > 127) relu_sat = 8'sd127; + else relu_sat = acc[7:0]; + end + endfunction + + // ============================================================ + // Node registration (generalized to MAX_DEPS=8 producers, passed + // as a packed array; n_producers of them are meaningful, the rest + // ignored since reg_required gates how many entries the RTL + // actually reads). + // ============================================================ + task automatic register_node( + input [NODE_IDW-1:0] nid, + input [$clog2(MAX_DEPS+1)-1:0] required, + input [MAX_DEPS*NODE_IDW-1:0] producer_ids_packed, + input [ADDR_WIDTH-1:0] xb, input [ADDR_WIDTH-1:0] wb, + input [15:0] nt, input [ADDR_WIDTH-1:0] resaddr + ); + begin + @(posedge clk); + reg_node_id = nid; + reg_required = required; + reg_producer_ids = producer_ids_packed; + reg_x_base = xb; reg_w_base = wb; reg_n_tiles = nt; reg_result_addr = resaddr; + reg_valid = 1'b1; + while (!reg_ready) @(posedge clk); + @(posedge clk); + reg_valid = 1'b0; + end + endtask + + // ============================================================ + // M10+ real cycle-accounting instrumentation (testbench-only, no + // RTL touched -- same idiom as EXP-0013). + // ============================================================ + reg measure_en; + integer total_cycles; + integer psram_busy_cycles; + integer ni; // moved up from its original later declaration point + // (STEP20 tooling-compatibility fix, zero behavior + // change -- see nms_memory_manager_stream_wide.v's own + // header note on icarus 13.0's stricter declared- + // before-use rule for procedural blocks) + genvar gi; + + reg [N_SLOTS_CFG-1:0] slot_busy_bit; // memory_manager.state != MM_IDLE, this cycle + reg [N_SLOTS_CFG-1:0] slot_tile_bit; // operand_valid && operand_ready, this cycle + integer slot_busy_cycles [0:N_SLOTS_CFG-1]; + integer slot_tiles_delivered [0:N_SLOTS_CFG-1]; + + generate + for (gi = 0; gi < N_SLOTS_CFG; gi = gi + 1) begin : GEN_SLOT_MON + always @(*) begin + slot_busy_bit[gi] = (u_nmp.u_dataflow_core.GEN_SLOT[gi].u_mm.state != 3'd0); + slot_tile_bit[gi] = u_nmp.u_dataflow_core.GEN_SLOT[gi].mm_operand_valid && + u_nmp.u_dataflow_core.GEN_SLOT[gi].mm_operand_ready; + end + end + endgenerate + + // ============================================================ + // STEP17 Part B/C: cycle-decomposition + SDRAM effectiveness + // instrumentation (testbench-only, no RTL touched). + // ============================================================ + integer active_count; // popcount(slot_busy_bit) this cycle + integer active_hist [0:4]; // cycles with exactly k active slots, k=0..4 + integer useful_mac_cycles; // sum over cycles of (#slots with slot_tile_bit this cycle) + integer first_tile_cyc; // total_cycles value at the first tile ever delivered (startup boundary) + integer last_tile_cyc; // total_cycles value at the most recent tile delivered (drain boundary) + integer any_tile_bit; + + // SDRAM controller-port instrumentation (real signals on the + // actual sdram_controller.v instance servicing all weight fetch) + integer sdram_req_count, sdram_ready_count, sdram_wr_count; + integer sdram_busy_cycles, sdram_refresh_count; + integer sdram_req_start_cyc, sdram_lat_sum, sdram_lat_min, sdram_lat_max, sdram_lat_n; + reg sdram_prev_state_is_refwait; + + initial begin + active_hist[0]=0; active_hist[1]=0; active_hist[2]=0; active_hist[3]=0; active_hist[4]=0; + useful_mac_cycles = 0; first_tile_cyc = -1; last_tile_cyc = -1; + sdram_req_count=0; sdram_ready_count=0; sdram_wr_count=0; + sdram_busy_cycles=0; sdram_refresh_count=0; + sdram_req_start_cyc=0; sdram_lat_sum=0; sdram_lat_min=999999; sdram_lat_max=0; sdram_lat_n=0; + sdram_prev_state_is_refwait=1'b0; + end + + always @(posedge clk) begin + if (measure_en) begin + active_count = slot_busy_bit[0]; + for (ni = 1; ni < N_SLOTS_CFG; ni = ni + 1) active_count = active_count + slot_busy_bit[ni]; + active_hist[active_count] <= active_hist[active_count] + 1; + + any_tile_bit = slot_tile_bit[0]; + for (ni = 1; ni < N_SLOTS_CFG; ni = ni + 1) any_tile_bit = any_tile_bit | slot_tile_bit[ni]; + for (ni = 0; ni < N_SLOTS_CFG; ni = ni + 1) + if (slot_tile_bit[ni]) useful_mac_cycles <= useful_mac_cycles + 1; + if (any_tile_bit) begin + if (first_tile_cyc < 0) first_tile_cyc <= total_cycles; + last_tile_cyc <= total_cycles; + end + + // ---- real SDRAM controller port (single physical chip, + // all weight-fetch traffic funnels through this one + // instance) ---- + if (u_nmp.u_sdram_backend.u_sdram_ctrl.req) begin + sdram_req_count <= sdram_req_count + 1; + sdram_req_start_cyc <= total_cycles; + if (u_nmp.u_sdram_backend.u_sdram_ctrl.wr) sdram_wr_count <= sdram_wr_count + 1; + end + if (u_nmp.u_sdram_backend.u_sdram_ctrl.ready) begin + sdram_ready_count <= sdram_ready_count + 1; + sdram_lat_sum <= sdram_lat_sum + (total_cycles - sdram_req_start_cyc); + sdram_lat_n <= sdram_lat_n + 1; + if ((total_cycles - sdram_req_start_cyc) < sdram_lat_min) sdram_lat_min <= (total_cycles - sdram_req_start_cyc); + if ((total_cycles - sdram_req_start_cyc) > sdram_lat_max) sdram_lat_max <= (total_cycles - sdram_req_start_cyc); + end + if (u_nmp.u_sdram_backend.u_sdram_ctrl.busy) sdram_busy_cycles <= sdram_busy_cycles + 1; + sdram_prev_state_is_refwait <= (u_nmp.u_sdram_backend.u_sdram_ctrl.state == 5'd9); + if (u_nmp.u_sdram_backend.u_sdram_ctrl.state == 5'd9 && !sdram_prev_state_is_refwait) + sdram_refresh_count <= sdram_refresh_count + 1; + end + end + + task automatic report_step17_instrumentation; + real active_pct [0:4]; + real util_pct, startup_cycles, drain_cycles; + real sdram_avg_lat, sdram_busy_pct, sdram_bytes_per_cycle; + integer kk, total_tiles_all; + begin + total_tiles_all = 0; + for (kk = 0; kk < N_SLOTS_CFG; kk = kk + 1) total_tiles_all = total_tiles_all + slot_tiles_delivered[kk]; + $display(" ---- STEP17 Part B: cycle decomposition ----"); + for (kk = 0; kk <= N_SLOTS_CFG; kk = kk + 1) begin + active_pct[kk] = (total_cycles > 0) ? (100.0*active_hist[kk]/total_cycles) : 0.0; + $display(" active_slots=%0d: %0d cycles (%0.2f%%)", kk, active_hist[kk], active_pct[kk]); + end + util_pct = (total_cycles > 0) ? (100.0*useful_mac_cycles/(total_cycles*1.0*N_SLOTS_CFG)) : 0.0; + $display(" useful_mac_cycles (slot-tile-delivery events, summed)=%0d (%0.2f%% of total_cycles*N_SLOTS)", useful_mac_cycles, util_pct); + startup_cycles = (first_tile_cyc >= 0) ? (1.0*first_tile_cyc) : 0.0; + drain_cycles = (last_tile_cyc >= 0) ? (1.0*(total_cycles - last_tile_cyc)) : 0.0; + $display(" startup (cycles before first tile delivered anywhere)=%0.0f", startup_cycles); + $display(" drain (cycles after last tile delivered, until job completion)=%0.0f", drain_cycles); + $display(" ---- STEP17 Part C: SDRAM effectiveness ----"); + sdram_avg_lat = (sdram_lat_n > 0) ? (1.0*sdram_lat_sum/sdram_lat_n) : 0.0; + sdram_busy_pct = (total_cycles > 0) ? (100.0*sdram_busy_cycles/total_cycles) : 0.0; + sdram_bytes_per_cycle = (total_cycles > 0) ? (8.0*sdram_ready_count/total_cycles) : 0.0; + $display(" sdram_req_count=%0d sdram_ready_count=%0d sdram_wr_count=%0d (real reads vs writes)", + sdram_req_count, sdram_ready_count, sdram_wr_count); + $display(" sdram_busy_cycles=%0d/%0d (%0.2f%%)", sdram_busy_cycles, total_cycles, sdram_busy_pct); + $display(" sdram_refresh_count=%0d (real AUTO REFRESH commands issued)", sdram_refresh_count); + $display(" sdram_request_latency: min=%0d max=%0d avg=%0.2f cycles (req-to-ready, single controller port)", + sdram_lat_min, sdram_lat_max, sdram_avg_lat); + $display(" sdram_avg_bytes_per_cycle (8 bytes/transaction * ready_count / total_cycles)=%0.4f", sdram_bytes_per_cycle); + end + endtask + + // ---- STEP11: weight-stall / prefetch-effectiveness instrumentation ---- + // slot_could_present_act: this slot's tile_idx is in-bounds and the + // activation operand for it is already resident -- i.e. everything + // EXCEPT the weight is ready. slot_weight_blocking: on top of that, + // the weight specifically is NOT yet ready (tile_idx>=wgt_ready_count) + // and the FSM is genuinely stalled on it (not mid-read-pipeline, not + // already holding a valid operand). + reg [N_SLOTS_CFG-1:0] slot_could_present_act; + reg [N_SLOTS_CFG-1:0] slot_weight_blocking; + reg [N_SLOTS_CFG-1:0] slot_stalled_this_tile; // sticky per current tile_idx + reg [31:0] prev_tile_idx [0:N_SLOTS_CFG-1]; + integer weight_stall_cycles [0:N_SLOTS_CFG-1]; + integer tiles_prefetched_clean [0:N_SLOTS_CFG-1]; // consumed w/ zero weight-blocking cycles + integer tiles_consumed_total [0:N_SLOTS_CFG-1]; + // plain (non-hierarchical) mirrors of each slot's tile_idx, populated + // combinationally inside the genvar-indexed generate block below -- + // a generate-block instance array (GEN_SLOT[.]) can only be indexed + // by a constant genvar, not a runtime `for` variable, so the + // sequential accumulation loop reads these plain arrays instead of + // reaching back into the hierarchy with a runtime index. + wire [31:0] slot_tile_idx_w [0:N_SLOTS_CFG-1]; + + generate + for (gi = 0; gi < N_SLOTS_CFG; gi = gi + 1) begin : GEN_SLOT_PF_MON + assign slot_tile_idx_w[gi] = {16'b0, u_nmp.u_dataflow_core.GEN_SLOT[gi].u_mm.tile_idx}; + always @(*) begin + slot_could_present_act[gi] = + ({{16{1'b0}}, u_nmp.u_dataflow_core.GEN_SLOT[gi].u_mm.tile_idx} < + {16'b0, u_nmp.u_dataflow_core.GEN_SLOT[gi].u_mm.n_tiles_reg}) && + ({{16{1'b0}}, u_nmp.u_dataflow_core.GEN_SLOT[gi].u_mm.tile_idx} < + {16'b0, u_nmp.u_dataflow_core.GEN_SLOT[gi].u_mm.usable_act}); + // nms_memory_manager_stream.v has no read_issued/ + // read_ready states (replaced by the rd_ptr/rd_pending + // read-ahead pipeline) -- the equivalent "blocked + // purely on weight readiness, nothing buffered yet" + // condition is simply: consumption pointer in bounds, + // activation ready, weight NOT ready, and no operand + // currently held in the skid buffer awaiting NP. + slot_weight_blocking[gi] = + slot_could_present_act[gi] && + !(u_nmp.u_dataflow_core.GEN_SLOT[gi].u_mm.tile_idx < + u_nmp.u_dataflow_core.GEN_SLOT[gi].u_mm.wgt_ready_count) && + !u_nmp.u_dataflow_core.GEN_SLOT[gi].u_mm.operand_valid; + end + end + endgenerate + + always @(posedge clk) begin + if (measure_en) begin + for (ni = 0; ni < N_SLOTS_CFG; ni = ni + 1) begin + if (prev_tile_idx[ni] != slot_tile_idx_w[ni]) begin + // moved on to a new tile: clear the sticky flag for it + slot_stalled_this_tile[ni] <= 1'b0; + prev_tile_idx[ni] <= slot_tile_idx_w[ni]; + end else if (slot_weight_blocking[ni]) begin + slot_stalled_this_tile[ni] <= 1'b1; + weight_stall_cycles[ni] <= weight_stall_cycles[ni] + 1; + end + if (slot_tile_bit[ni]) begin + tiles_consumed_total[ni] <= tiles_consumed_total[ni] + 1; + if (!slot_stalled_this_tile[ni]) + tiles_prefetched_clean[ni] <= tiles_prefetched_clean[ni] + 1; + end + end + end + end + + // Director/dependency bookkeeping + integer jobs_allocated, jobs_completed, wakeups; + integer waiting_sum, ready_sum, dispatched_sum, sample_count; + + // Occupancy sampling is EXPENSIVE (a full N_NODES=512 scan) and is + // only needed for the small/structural workloads (A/B/E/F), not + // for the large neuron counts (C/D) where it would dominate + // simulation wall-time for no real benefit (per-slot/PSRAM/tile + // counters below are cheap and always collected). Gated by + // sample_occupancy, set per-workload. + reg sample_occupancy; + integer scan_i; + integer waiting_now, ready_now, dispatched_now; + + always @(posedge clk) begin + if (measure_en) begin + total_cycles <= total_cycles + 1; + if (u_nmp.u_arbiter.owner != 0) psram_busy_cycles <= psram_busy_cycles + 1; + for (ni = 0; ni < N_SLOTS_CFG; ni = ni + 1) begin + if (slot_busy_bit[ni]) slot_busy_cycles[ni] <= slot_busy_cycles[ni] + 1; + if (slot_tile_bit[ni]) slot_tiles_delivered[ni] <= slot_tiles_delivered[ni] + 1; + end + if (u_nmp.u_dataflow_core.dm_ready_valid && u_nmp.u_dataflow_core.dm_ready_ready) + jobs_allocated <= jobs_allocated + 1; + if (u_nmp.u_dataflow_core.dir_job_out_done) + jobs_completed <= jobs_completed + 1; + if (u_nmp.u_dataflow_core.dm_producer_done_valid) + wakeups <= wakeups + 1; + + if (sample_occupancy) begin + waiting_now = 0; ready_now = 0; dispatched_now = 0; + for (scan_i = 0; scan_i < N_NODES; scan_i = scan_i + 1) begin + case (u_nmp.u_dataflow_core.u_dep_mgr.node_state[scan_i]) + 2'd1: waiting_now = waiting_now + 1; + 2'd2: ready_now = ready_now + 1; + 2'd3: dispatched_now = dispatched_now + 1; + default: ; + endcase + end + waiting_sum <= waiting_sum + waiting_now; + ready_sum <= ready_sum + ready_now; + dispatched_sum <= dispatched_sum + dispatched_now; + sample_count <= sample_count + 1; + end + end + end + + task automatic reset_instrumentation(input do_sample_occupancy); + integer k; + begin + active_hist[0]=0; active_hist[1]=0; active_hist[2]=0; active_hist[3]=0; active_hist[4]=0; + useful_mac_cycles = 0; first_tile_cyc = -1; last_tile_cyc = -1; + sdram_req_count=0; sdram_ready_count=0; sdram_wr_count=0; + sdram_busy_cycles=0; sdram_refresh_count=0; + sdram_req_start_cyc=0; sdram_lat_sum=0; sdram_lat_min=999999; sdram_lat_max=0; sdram_lat_n=0; + total_cycles = 0; psram_busy_cycles = 0; + jobs_allocated = 0; jobs_completed = 0; wakeups = 0; + waiting_sum = 0; ready_sum = 0; dispatched_sum = 0; sample_count = 0; + sample_occupancy = do_sample_occupancy; + for (k = 0; k < N_SLOTS_CFG; k = k + 1) begin + slot_busy_cycles[k] = 0; + slot_tiles_delivered[k] = 0; + weight_stall_cycles[k] = 0; + tiles_prefetched_clean[k] = 0; + tiles_consumed_total[k] = 0; + slot_stalled_this_tile[k] = 1'b0; + prev_tile_idx[k] = 32'hFFFFFFFF; + end + end + endtask + + task automatic report_instrumentation(input [255:0] label, input integer n_neurons_completed); + integer k, total_tiles; + integer total_weight_stall_cycles, total_tiles_consumed_all, total_tiles_prefetched_clean; + real avg_waiting, avg_ready, avg_dispatched; + real psram_util, sustained_mac_per_cycle, wallclock_us; + real processor_utilization, weight_stall_pct, prefetch_effectiveness_pct; + begin + total_tiles = 0; + for (k = 0; k < N_SLOTS_CFG; k = k + 1) total_tiles = total_tiles + slot_tiles_delivered[k]; + avg_waiting = (sample_count > 0) ? (1.0*waiting_sum/sample_count) : 0.0; + avg_ready = (sample_count > 0) ? (1.0*ready_sum/sample_count) : 0.0; + avg_dispatched = (sample_count > 0) ? (1.0*dispatched_sum/sample_count) : 0.0; + psram_util = (total_cycles > 0) ? (100.0*psram_busy_cycles/total_cycles) : 0.0; + sustained_mac_per_cycle = (total_cycles > 0) ? (1.0*total_tiles*P_IN/total_cycles) : 0.0; + wallclock_us = total_cycles * CLK_PERIOD / 1000.0; + $display("---- BENCHMARK REPORT: %0s ----", label); + $display(" total_cycles=%0d wallclock_us=%0.3f", total_cycles, wallclock_us); + $display(" neurons_completed=%0d tiles_delivered(real)=%0d", n_neurons_completed, total_tiles); + $display(" jobs_allocated=%0d jobs_completed=%0d dependency_wakeups=%0d", jobs_allocated, jobs_completed, wakeups); + $display(" shared AR (activation+result) arbiter-side utilization: %0.1f%% (%0d/%0d busy cycles)", psram_util, psram_busy_cycles, total_cycles); + for (k = 0; k < N_SLOTS_CFG; k = k + 1) + $display(" slot %0d: busy=%0d/%0d (%0.1f%%) tiles=%0d", k, slot_busy_cycles[k], total_cycles, + (total_cycles>0)?(100.0*slot_busy_cycles[k]/total_cycles):0.0, slot_tiles_delivered[k]); + if (sample_count > 0) + $display(" dependency_manager avg occupancy (sampled every measured cycle): waiting=%0.2f ready=%0.2f dispatched=%0.2f", avg_waiting, avg_ready, avg_dispatched); + else + $display(" dependency_manager occupancy: NOT SAMPLED for this workload (N_NODES scan skipped for large neuron counts to keep simulation time reasonable)"); + $display(" DERIVED: sustained end-to-end MAC/cycle = %0.4f (real tiles*%0d / real total_cycles)", sustained_mac_per_cycle, P_IN); + if (n_neurons_completed > 0) + $display(" DERIVED: cycles/neuron = %0.2f", 1.0*total_cycles/n_neurons_completed); + if (total_tiles > 0) + $display(" DERIVED: cycles/tile = %0.2f", 1.0*total_cycles/total_tiles); + + // ---- STEP11 metrics ---- + total_weight_stall_cycles = 0; total_tiles_consumed_all = 0; total_tiles_prefetched_clean = 0; + for (k = 0; k < N_SLOTS_CFG; k = k + 1) begin + total_weight_stall_cycles = total_weight_stall_cycles + weight_stall_cycles[k]; + total_tiles_consumed_all = total_tiles_consumed_all + tiles_consumed_total[k]; + total_tiles_prefetched_clean = total_tiles_prefetched_clean + tiles_prefetched_clean[k]; + end + processor_utilization = (total_cycles > 0) ? (100.0*total_tiles/(total_cycles*1.0)) : 0.0; + weight_stall_pct = (total_cycles > 0) ? (100.0*total_weight_stall_cycles/(total_cycles*N_SLOTS_CFG*1.0)) : 0.0; + prefetch_effectiveness_pct = (total_tiles_consumed_all > 0) ? + (100.0*total_tiles_prefetched_clean/(total_tiles_consumed_all*1.0)) : 0.0; + $display(" [STEP11] PFD=%0d weight_stall_cycles(sum,all slots)=%0d (%0.2f%% of total_cycles*N_SLOTS)", + PFD_CFG, total_weight_stall_cycles, weight_stall_pct); + $display(" [STEP11] tiles_consumed=%0d tiles_prefetched_clean(zero weight-block before consumption)=%0d", + total_tiles_consumed_all, total_tiles_prefetched_clean); + $display(" [STEP11] DERIVED: prefetch_effectiveness = %0.2f%%", prefetch_effectiveness_pct); + $display(" [STEP11] DERIVED: processor_utilization (tiles*P_IN-equivalent proxy, see sustained MAC/cycle) reference sustained_mac_per_cycle=%0.4f", sustained_mac_per_cycle); + end + endtask + + // ============================================================ + // Workload generators + // ============================================================ + integer errors, tests; + integer wd; + + // A/B/C/D: shared-input dense layer. Generates the shared X + // vector, then N independent (neuron, weight-vector) jobs, each + // verified bit-exact against the golden model. + task automatic run_dense_layer( + input [255:0] label, + input integer n_neurons, + input integer n_tiles_count, + input [NODE_IDW-1:0] node_base, + input [ADDR_WIDTH-1:0] x_base, + input [ADDR_WIDTH-1:0] w_base, + input [ADDR_WIDTH-1:0] res_base, + input sample_occ + ); + integer n, t, k, len, acc; + reg signed [7:0] xv, wv, golden, real_y; + reg [MAX_DEPS*NODE_IDW-1:0] no_deps; + integer completed, wd2; + begin + len = n_tiles_count * P_IN; + no_deps = {(MAX_DEPS*NODE_IDW){1'b0}}; + + // shared input vector + for (k = 0; k < len; k = k + 1) + poke_byte(x_base + k, ((k % 8) + 1)); + + reset_instrumentation(sample_occ); + measure_en = 1'b1; + + for (n = 0; n < n_neurons; n = n + 1) begin + acc = 0; + for (t = 0; t < n_tiles_count; t = t + 1) begin + for (k = 0; k < P_IN; k = k + 1) begin + xv = peek_byte(x_base + t*P_IN + k); + wv = (((n + t*P_IN + k) % 8) + 1); + poke_byte_weight(w_base + n*len + t*P_IN + k, wv); + acc = acc + xv*wv; + end + end + golden = relu_sat(acc); + poke_byte(res_base + n, 8'sd0); // poison, must NOT still be 0 after completion (unless golden IS 0 -- checked separately) + register_node(node_base + n[NODE_IDW-1:0], 0, no_deps, + x_base, w_base + n*len, n_tiles_count[15:0], res_base + n); + if ((n % 32) == 0) begin + $display(" [%0s] registered %0d/%0d", label, n+1, n_neurons); + $fflush; + end + end + $display(" [%0s] all %0d neurons registered, waiting for completion...", label, n_neurons); + $fflush; + + // wait for all n_neurons completions + completed = 0; wd2 = 0; + while (completed < n_neurons && wd2 < 2000000) begin + @(posedge clk); + wd2 = wd2 + 1; + completed = jobs_completed; + if ((wd2 % 20000) == 0) begin + $display(" [%0s] watchdog %0d: completed=%0d/%0d total_cycles=%0d", label, wd2, completed, n_neurons, total_cycles); +`ifdef STEP16_DEBUG_TRACE + $display(" slot0: mm.state=%0d tile_idx=%0d n_tiles_reg=%0d wgt_ready_count=%0d usable_act=%0d op_valid=%0d op_ready=%0d", + u_nmp.u_dataflow_core.GEN_SLOT[0].u_mm.state, + u_nmp.u_dataflow_core.GEN_SLOT[0].u_mm.tile_idx, + u_nmp.u_dataflow_core.GEN_SLOT[0].u_mm.n_tiles_reg, + u_nmp.u_dataflow_core.GEN_SLOT[0].u_mm.wgt_ready_count, + u_nmp.u_dataflow_core.GEN_SLOT[0].u_mm.usable_act, + u_nmp.u_dataflow_core.GEN_SLOT[0].mm_operand_valid, + u_nmp.u_dataflow_core.GEN_SLOT[0].mm_operand_ready); + $display(" slot1: mm.state=%0d tile_idx=%0d n_tiles_reg=%0d wgt_ready_count=%0d usable_act=%0d op_valid=%0d op_ready=%0d", + u_nmp.u_dataflow_core.GEN_SLOT[1].u_mm.state, + u_nmp.u_dataflow_core.GEN_SLOT[1].u_mm.tile_idx, + u_nmp.u_dataflow_core.GEN_SLOT[1].u_mm.n_tiles_reg, + u_nmp.u_dataflow_core.GEN_SLOT[1].u_mm.wgt_ready_count, + u_nmp.u_dataflow_core.GEN_SLOT[1].u_mm.usable_act, + u_nmp.u_dataflow_core.GEN_SLOT[1].mm_operand_valid, + u_nmp.u_dataflow_core.GEN_SLOT[1].mm_operand_ready); + $display(" sdram: req=%0d busy=%0d ready=%0d req_pending=%0d state=%0d | arb: owner=%0d pending=%0b wide_req=%0b wide_ready=%0b", + u_nmp.u_sdram_backend.u_sdram_ctrl.req, + u_nmp.u_sdram_backend.u_sdram_ctrl.busy, + u_nmp.u_sdram_backend.u_sdram_ctrl.ready, + u_nmp.u_sdram_backend.u_sdram_ctrl.req_pending, + u_nmp.u_sdram_backend.u_sdram_ctrl.state, + u_nmp.u_arbiter_wide.owner, + u_nmp.u_arbiter_wide.pending, + u_nmp.wide_slot_mem_req, + u_nmp.wide_slot_mem_ready); +`endif + $fflush; + end + end + repeat(5) @(posedge clk); + measure_en = 1'b0; + + tests = tests + 1; + if (completed < n_neurons) begin + $display("FAIL %0s: only %0d/%0d neurons completed within watchdog", label, completed, n_neurons); + errors = errors + 1; + end else begin : check_block + integer local_errors; + local_errors = 0; + for (n = 0; n < n_neurons; n = n + 1) begin + acc = 0; + for (t = 0; t < n_tiles_count; t = t + 1) + for (k = 0; k < P_IN; k = k + 1) + acc = acc + peek_byte(x_base + t*P_IN + k) * peek_byte_weight(w_base + n*len + t*P_IN + k); + golden = relu_sat(acc); + real_y = peek_byte(res_base + n); + if (real_y !== golden) begin + $display("FAIL %0s neuron %0d: real=%0d golden=%0d", label, n, real_y, golden); + local_errors = local_errors + 1; + end + end + if (local_errors == 0) + $display("PASS %0s: all %0d neurons bit-exact vs golden", label, n_neurons); + else + errors = errors + 1; + end + report_instrumentation(label, n_neurons); + report_step17_instrumentation; + end + endtask + + // E: Multilayer (8 layer-1 random neurons -> shared hidden vector + // -> 2 layer-2 neurons consuming it, real dependency wake-up + + // real cross-node data forwarding through real PSRAM). + localparam L1_N = 8; + localparam L2_N = 2; + integer rand_seed; + + task automatic run_multilayer( + input [NODE_IDW-1:0] node_base, + input [ADDR_WIDTH-1:0] l1x_base, input [ADDR_WIDTH-1:0] l1w_base, + input [ADDR_WIDTH-1:0] hidden_base, + input [ADDR_WIDTH-1:0] l2w_base, input [ADDR_WIDTH-1:0] l2res_base + ); + integer n, k, acc, completed, wd2; + reg signed [7:0] xv, wv, golden_l1 [0:L1_N-1], golden_l2, real_y; + reg [MAX_DEPS*NODE_IDW-1:0] no_deps, l2_deps; + integer local_errors; + begin + no_deps = {(MAX_DEPS*NODE_IDW){1'b0}}; + l2_deps = {(MAX_DEPS*NODE_IDW){1'b0}}; + for (n = 0; n < L1_N; n = n + 1) + l2_deps[n*NODE_IDW +: NODE_IDW] = node_base + n[NODE_IDW-1:0]; + + rand_seed = 32'hC0FFEE01; + $display("RANDOM SEED (workload E, layer-1 data) = 32'h%08h", rand_seed); + + reset_instrumentation(1'b1); + measure_en = 1'b1; + + for (n = 0; n < L1_N; n = n + 1) begin + acc = 0; + for (k = 0; k < P_IN; k = k + 1) begin + xv = $random(rand_seed) % 9; // deterministic PRNG stream, range roughly [-8,8] + wv = $random(rand_seed) % 9; + poke_byte(l1x_base + n*P_IN + k, xv); + poke_byte(l1w_base + n*P_IN + k, wv); + acc = acc + xv*wv; + end + golden_l1[n] = relu_sat(acc); + poke_byte(hidden_base + n, 8'sd0); // poison hidden slot + register_node(node_base + n[NODE_IDW-1:0], 0, no_deps, + l1x_base + n*P_IN, l1w_base + n*P_IN, 16'd1, hidden_base + n); + end + + for (n = 0; n < L2_N; n = n + 1) begin + for (k = 0; k < P_IN; k = k + 1) + poke_byte(l2w_base + n*P_IN + k, ((n + k) % 6) + 1); + register_node(node_base + L1_N[NODE_IDW-1:0] + n[NODE_IDW-1:0], L1_N[$clog2(MAX_DEPS+1)-1:0], l2_deps, + hidden_base, l2w_base + n*P_IN, 16'd1, l2res_base + n); + end + + completed = 0; wd2 = 0; + while (completed < (L1_N+L2_N) && wd2 < 2000000) begin + @(posedge clk); wd2 = wd2 + 1; completed = jobs_completed; + end + repeat(5) @(posedge clk); + measure_en = 1'b0; + + tests = tests + 1; + local_errors = 0; + if (completed < (L1_N+L2_N)) begin + $display("FAIL Multilayer: only %0d/%0d nodes completed", completed, L1_N+L2_N); + local_errors = local_errors + 1; + end else begin + for (n = 0; n < L1_N; n = n + 1) begin + real_y = peek_byte(hidden_base + n); + if (real_y !== golden_l1[n]) begin + $display("FAIL Multilayer L1 neuron %0d: real=%0d golden=%0d", n, real_y, golden_l1[n]); + local_errors = local_errors + 1; + end + end + for (n = 0; n < L2_N; n = n + 1) begin + acc = 0; + for (k = 0; k < P_IN; k = k + 1) + acc = acc + golden_l1[k] * peek_byte(l2w_base + n*P_IN + k); + golden_l2 = relu_sat(acc); + real_y = peek_byte(l2res_base + n); + if (real_y !== golden_l2) begin + $display("FAIL Multilayer L2 neuron %0d: real=%0d golden=%0d (using REAL L1 hidden values)", n, real_y, golden_l2); + local_errors = local_errors + 1; + end + end + end + if (local_errors == 0) $display("PASS Multilayer: 8 L1 (random) -> 2 L2 neurons, all bit-exact, real cross-node forwarding via real PSRAM"); + else errors = errors + 1; + report_instrumentation("E-Multilayer", L1_N+L2_N); + end + endtask + + // F: DAG diamond+fan-in (A,B indep; C dep-A; D dep-B; E dep-C&D + // [2-hop]; F dep-A,B,C [mixed, 3 producers]) + task automatic run_dag( + input [NODE_IDW-1:0] node_base, + input [ADDR_WIDTH-1:0] x_base, input [ADDR_WIDTH-1:0] w_base, input [ADDR_WIDTH-1:0] res_base + ); + integer n, k, acc, completed, wd2, local_errors; + reg signed [7:0] golden [0:5]; + reg signed [7:0] real_y; + reg [MAX_DEPS*NODE_IDW-1:0] deps; + reg [NODE_IDW-1:0] idA, idB, idC, idD, idE, idF; + begin + idA = node_base+0; idB = node_base+1; idC = node_base+2; + idD = node_base+3; idE = node_base+4; idF = node_base+5; + + // Each of the 6 nodes: its own small independent 8-input + // job (deterministic, distinct per node) -- dependencies + // here are purely about SCHEDULING/wake-up order, not + // data forwarding (workload E already covers that). + for (n = 0; n < 6; n = n + 1) begin + acc = 0; + for (k = 0; k < P_IN; k = k + 1) begin + poke_byte(x_base + n*P_IN + k, ((n+k)%4)+1); + poke_byte(w_base + n*P_IN + k, ((n+k)%5)+1); + acc = acc + peek_byte(x_base+n*P_IN+k)*peek_byte(w_base+n*P_IN+k); + end + golden[n] = relu_sat(acc); + poke_byte(res_base + n, 8'sd0); + end + + reset_instrumentation(1'b1); + measure_en = 1'b1; + + deps = {(MAX_DEPS*NODE_IDW){1'b0}}; + register_node(idA, 0, deps, x_base+0*P_IN, w_base+0*P_IN, 16'd1, res_base+0); + register_node(idB, 0, deps, x_base+1*P_IN, w_base+1*P_IN, 16'd1, res_base+1); + + deps = {(MAX_DEPS*NODE_IDW){1'b0}}; deps[0*NODE_IDW+:NODE_IDW] = idA; + register_node(idC, 1, deps, x_base+2*P_IN, w_base+2*P_IN, 16'd1, res_base+2); + + deps = {(MAX_DEPS*NODE_IDW){1'b0}}; deps[0*NODE_IDW+:NODE_IDW] = idB; + register_node(idD, 1, deps, x_base+3*P_IN, w_base+3*P_IN, 16'd1, res_base+3); + + deps = {(MAX_DEPS*NODE_IDW){1'b0}}; deps[0*NODE_IDW+:NODE_IDW] = idC; deps[1*NODE_IDW+:NODE_IDW] = idD; + register_node(idE, 2, deps, x_base+4*P_IN, w_base+4*P_IN, 16'd1, res_base+4); + + deps = {(MAX_DEPS*NODE_IDW){1'b0}}; deps[0*NODE_IDW+:NODE_IDW] = idA; deps[1*NODE_IDW+:NODE_IDW] = idB; deps[2*NODE_IDW+:NODE_IDW] = idC; + register_node(idF, 3, deps, x_base+5*P_IN, w_base+5*P_IN, 16'd1, res_base+5); + + completed = 0; wd2 = 0; + while (completed < 6 && wd2 < 2000000) begin @(posedge clk); wd2=wd2+1; completed = jobs_completed; end + repeat(5) @(posedge clk); + measure_en = 1'b0; + + tests = tests + 1; + local_errors = 0; + if (completed < 6) begin + $display("FAIL DAG: only %0d/6 nodes completed", completed); + local_errors = local_errors + 1; + end else begin + for (n = 0; n < 6; n = n + 1) begin + real_y = peek_byte(res_base+n); + if (real_y !== golden[n]) begin + $display("FAIL DAG node %0d: real=%0d golden=%0d", n, real_y, golden[n]); + local_errors = local_errors + 1; + end + end + end + if (local_errors == 0) $display("PASS DAG: 6-node diamond+fan-in (2-hop transitive wake-up, 3-producer mixed-depth dependency), all bit-exact"); + else errors = errors + 1; + report_instrumentation("F-DAG", 6); + end + endtask + + initial begin + errors = 0; tests = 0; + rst = 1; reg_valid = 0; reg_node_id = 0; reg_required = 0; reg_producer_ids = 0; + reg_x_base = 0; reg_w_base = 0; reg_n_tiles = 0; reg_result_addr = 0; + measure_en = 0; + repeat(5) @(posedge clk); + rst = 0; + + $display("========================================"); + $display("NMS D-Stress benchmark (STEP19, SINGLE SDRAM (AS4C4M16SA-6TIN) for weights+activations+results, no PSRAM anywhere) -- N_SLOTS_CFG=%0d PFD_CFG=%0d", N_SLOTS_CFG, PFD_CFG); + $display("========================================"); + + wait (u_nmp.u_sdram_backend.u_sdram_ctrl.state == u_nmp.u_sdram_backend.u_sdram_ctrl.S_IDLE); + @(posedge clk); + + // Official V2 memory map (datasheet ch.5): weights @ 0x010000, + // activations @ 0x200000, results @ 0x300000 -- non-overlapping + // 1MB-aligned regions in the single SDRAM. + run_dense_layer("D-Stress", 256, 16, 16'd400, 26'h200000, 26'h010000, 26'h300000, 1'b0); + + // FPGA_DATA_READY check: the whole graph (256 nodes) just + // finished and no new work has been registered -- data_ready + // must be asserted (system-idle sticky flag, see + // nms_dataflow_core_sdram.v). A few idle cycles for the + // busy->idle edge to settle before sampling. + repeat (4) @(posedge clk); + if (u_nmp.data_ready !== 1'b1) begin + $display("FAIL data_ready: expected 1 after graph completion, got %b", u_nmp.data_ready); + errors = errors + 1; + end else begin + $display("PASS data_ready: correctly asserted after graph completion"); + end + + $display("========================================"); + if (errors == 0) + $display("ALL %0d WORKLOAD SUITES PASSED (N_SLOTS_CFG=%0d, PFD_CFG=%0d, SINGLE SDRAM for weights+activations+results, no PSRAM)", tests, N_SLOTS_CFG, PFD_CFG); + else + $display("FAILED: %0d/%0d workload suite(s) had errors -- see messages above", errors, tests); + $display("========================================"); + $finish; + end + +endmodule diff --git a/hardware/v2/rtl/dependency_manager_fast.v b/hardware/v2/rtl/dependency_manager_fast.v new file mode 100644 index 0000000..4c7cbc9 --- /dev/null +++ b/hardware/v2/rtl/dependency_manager_fast.v @@ -0,0 +1,253 @@ +`timescale 1ns/1ps + +// ================================================================ +// EXP-0056 -- fork of dependency_manager.v: the ONLY change is +// first_ready_idx/any_ready, replaced with priority_encoder_lsb.v +// (see that computation's own inline comment for the full rationale +// and the fix-pattern precedent -- ERR-0027/ERR-0028/ERR-0029). This +// targets the real critical path found blocking N_SLOTS=16 timing +// closure on the LFE5U-85F (measured: worst 23.52MHz vs 64MHz target, +// see hardware/v2/logs/experiments.log EXP-0056). Everything else in +// this module is byte-for-byte identical to dependency_manager.v. +// +// Everything below this point is the ORIGINAL module's own header, +// preserved as-is: +// +// FPGA-Neural V2 -- Dependency Manager (M6, docs/v2-description.md §10) +// +// Holds a small table of N_NODES job descriptors, each tracking: +// node_id, state (EMPTY/WAITING/READY/DISPATCHED), +// required_dependencies, resolved_dependencies, producer_ids[MAX_DEPS] +// (§10's exact field list), plus the job descriptor fields +// (x_base/w_base/n_tiles/result_addr) needed to hand the node off to +// the Neural Director (M5) once it becomes READY. +// +// A node with required_dependencies==0 is immediately READY on +// registration (no producers to wait for -- a graph's own input +// nodes, or a fully-independent job). When a PRODUCER completes +// (producer_done_valid/producer_done_node_id, tagged by whichever +// node just finished -- fed from the Director's own job_out_done/ +// job_out_slot, resolved back to a node_id by the caller), every +// OTHER node that lists that producer among its own producer_ids +// gets its resolved_dependencies incremented -- a single producer +// can satisfy MULTIPLE waiting consumers this way (§10 "risultati +// condivisi... più consumer"), and a node depending on several +// producers accumulates resolved_dependencies across separate +// producer-done events ("dipendenze multiple"). +// +// Ready nodes are handed to the Director one at a time via a +// valid/ready producer interface (ready_valid/ready_ready), backpressure- +// safe (§10 "backpressure"): a node stays READY, occupying its table +// slot, until the consumer (Director) actually accepts it. +// +// Scope note (see hardware/v2/logs/decisions.log DEC-0008): §11's +// direct producer-to-consumer VALUE forwarding (bypassing the Result +// Buffer / external memory round-trip) is NOT implemented here -- +// this module tracks dependency COUNTS/readiness only ("has this +// node's data become available", not the data itself), which is what +// actually gates scheduling; the job descriptor's result_addr already +// points at wherever the Memory Manager (M4) wrote the producer's +// result, which is how a ready consumer finds its inputs today. Real +// zero-copy forwarding is a possible future optimization (§11 itself: +// "quando possibile"), deferred until measured to matter (§22). +// ================================================================ + +module dependency_manager_fast #( + parameter N_NODES = 16, + parameter MAX_DEPS = 4, + parameter ADDR_WIDTH = 26 +)( + input wire clk, + input wire rst, + + // ---- node registration (host / graph loader) ---- + input wire reg_valid, + output wire reg_ready, + input wire [$clog2(N_NODES)-1:0] reg_node_id, + input wire [$clog2(MAX_DEPS+1)-1:0] reg_required, + input wire [MAX_DEPS*$clog2(N_NODES)-1:0] reg_producer_ids, + input wire [ADDR_WIDTH-1:0] reg_x_base, + input wire [ADDR_WIDTH-1:0] reg_w_base, + input wire [15:0] reg_n_tiles, + input wire [ADDR_WIDTH-1:0] reg_result_addr, + + // ---- producer completion notification ---- + input wire producer_done_valid, + input wire [$clog2(N_NODES)-1:0] producer_done_node_id, + + // ---- ready job output (to neural_director.v's job_in_* port) ---- + output reg ready_valid, + input wire ready_ready, + output reg [$clog2(N_NODES)-1:0] ready_node_id, + output reg [ADDR_WIDTH-1:0] ready_x_base, + output reg [ADDR_WIDTH-1:0] ready_w_base, + output reg [15:0] ready_n_tiles, + output reg [ADDR_WIDTH-1:0] ready_result_addr, + + // FPGA_DATA_READY support: high while at least one registered node + // has not yet been handed to the Director (ST_WAITING or ST_READY -- + // ST_DISPATCHED is deliberately excluded, since dispatched work is + // tracked downstream by neural_director.v's own queue/slot state, + // not here -- see this file's own ST_DISPATCHED comment). + output wire any_pending +); + + localparam ST_EMPTY = 2'd0; + localparam ST_WAITING = 2'd1; + localparam ST_READY = 2'd2; + localparam ST_DISPATCHED = 2'd3; + + localparam NODE_IDW = $clog2(N_NODES); + localparam REQW = $clog2(MAX_DEPS+1); + + reg [1:0] node_state [0:N_NODES-1]; + reg [REQW-1:0] node_required [0:N_NODES-1]; + reg [REQW-1:0] node_resolved [0:N_NODES-1]; + reg [NODE_IDW-1:0] node_producer_ids [0:N_NODES-1][0:MAX_DEPS-1]; + reg [ADDR_WIDTH-1:0] node_x_base [0:N_NODES-1]; + reg [ADDR_WIDTH-1:0] node_w_base [0:N_NODES-1]; + reg [15:0] node_n_tiles [0:N_NODES-1]; + reg [ADDR_WIDTH-1:0] node_result_addr [0:N_NODES-1]; + + // A node id doubles as its own table slot index (§10's example + // literally addresses nodes by id: "node 37") -- N_NODES must + // therefore cover the full id range a caller intends to use. + assign reg_ready = (node_state[reg_node_id] == ST_EMPTY); + + // ---- EXP-0056: priority-encoded first READY node, via a + // recursive binary-tree lowest-set-bit encoder (O(log2(N_NODES)) + // depth) instead of the original serial for-loop scan (O(N_NODES) + // depth, the SAME architectural anti-pattern already fixed twice + // elsewhere in this project -- ERR-0027/ERR-0028/ERR-0029 -- see + // priority_encoder_lsb.v's own header for the full rationale). + // Semantically identical to the original: ready_oh's lowest set + // bit is the lowest node index currently READY, matching the + // original loop's own "last (lowest-index) match wins" behavior + // exactly -- verified bit-exact against the original module by + // tb_dependency_manager_fast.v before this fork was integrated + // anywhere. + // ============================================================ + wire [N_NODES-1:0] ready_oh; + generate + genvar gi; + for (gi = 0; gi < N_NODES; gi = gi + 1) begin : GEN_READY_OH + assign ready_oh[gi] = (node_state[gi] == ST_READY); + end + endgenerate + + wire [NODE_IDW-1:0] first_ready_idx; + wire any_ready; + priority_encoder_lsb #(.WIDTH(N_NODES)) u_ready_penc ( + .in(ready_oh), .idx(first_ready_idx), .valid(any_ready) + ); + + // ---- FPGA_DATA_READY support (see any_pending port comment above). + // Originally a combinational OR-reduce over node_state[0:N_NODES-1] + // (16-wide), which added real fan-out load onto node_state -- a + // signal this session's own real P&R critical-path traces later + // showed sitting on the SAME already-congested job_out_slot -> + // node_resolved/node_state broadcast path (routing-dominated, + // 76-84%). Replaced with a synchronous up/down counter: +1 on a + // node's own registration acceptance (reg_valid&®_ready -- + // exactly when it enters WAITING/READY), -1 on its own dispatch + // acceptance (ready_valid&&ready_ready -- exactly when it leaves + // WAITING/READY for DISPATCHED). registered-minus-dispatched is + // mathematically identical to the original OR-reduce's own + // "any node currently WAITING or READY" condition (DEC-0008: nodes + // are never reclaimed mid-run, so every node visits EMPTY -> + // {WAITING or READY} -> DISPATCHED exactly once), but reads a + // single small registered counter instead of scanning a wide array + // every cycle -- zero added fan-out on the congested signals. ---- + localparam PENDW = $clog2(N_NODES+1); + reg [PENDW-1:0] pending_count; + assign any_pending = (pending_count != {PENDW{1'b0}}); + + integer ni, di; + + always @(posedge clk) begin + if (rst) begin + for (ni = 0; ni < N_NODES; ni = ni + 1) begin + node_state[ni] <= ST_EMPTY; + node_required[ni] <= {REQW{1'b0}}; + node_resolved[ni] <= {REQW{1'b0}}; + end + ready_valid <= 1'b0; + pending_count <= {PENDW{1'b0}}; + end else begin + + // pending_count: +1 on registration acceptance, -1 on + // dispatch acceptance; a same-cycle occurrence of both is a + // net zero change (no assignment needed, old value holds). + case ({(reg_valid && reg_ready), (ready_valid && ready_ready)}) + 2'b10: pending_count <= pending_count + 1'b1; + 2'b01: pending_count <= pending_count - 1'b1; + default: ; // 00 or 11: no net change + endcase + + // ---- registration: create a new WAITING (or immediately + // READY, if required==0) node entry. ---- + if (reg_valid && reg_ready) begin + node_required[reg_node_id] <= reg_required; + node_resolved[reg_node_id] <= {REQW{1'b0}}; + node_x_base[reg_node_id] <= reg_x_base; + node_w_base[reg_node_id] <= reg_w_base; + node_n_tiles[reg_node_id] <= reg_n_tiles; + node_result_addr[reg_node_id] <= reg_result_addr; + for (di = 0; di < MAX_DEPS; di = di + 1) + node_producer_ids[reg_node_id][di] <= reg_producer_ids[di*NODE_IDW +: NODE_IDW]; + node_state[reg_node_id] <= (reg_required == {REQW{1'b0}}) ? ST_READY : ST_WAITING; + end + + // ---- wake-up: a completed producer increments + // resolved_dependencies for EVERY WAITING node that lists + // it, independent of the registration above (a node can + // be registered and immediately woken by an in-flight + // producer-done event the same cycle, since both read the + // PRE-edge node_state/node_producer_ids consistently). ---- + if (producer_done_valid) begin + for (ni = 0; ni < N_NODES; ni = ni + 1) begin + if (node_state[ni] == ST_WAITING) begin + for (di = 0; di < MAX_DEPS; di = di + 1) begin + if (di < node_required[ni] && + node_producer_ids[ni][di] == producer_done_node_id) begin + if (node_resolved[ni] + 1'b1 >= node_required[ni]) + node_state[ni] <= ST_READY; + node_resolved[ni] <= node_resolved[ni] + 1'b1; + end + end + end + end + end + + // ---- dispatch: hand the first READY node to the + // Director, one at a time, backpressure-safe. ---- + if (ready_valid && ready_ready) begin + node_state[ready_node_id] <= ST_DISPATCHED; + // ST_DISPATCHED is terminal here (M6 does not yet + // reclaim slots for re-use -- see decisions.log + // DEC-0008): a full graph run allocates N_NODES once. + ready_valid <= 1'b0; + end else if (!ready_valid && any_ready) begin + // Deliberately NOT combined with the dispatch branch + // above into "!ready_valid || (ready_valid&&ready_ready)" + // -- the scan for first_ready_idx is combinational + // over node_state's PRE-edge value, which still shows + // the about-to-be-dispatched node as READY this same + // edge; reloading in the same cycle as a dispatch + // could re-present the SAME node that is simultaneously + // transitioning to DISPATCHED. Reloading strictly the + // cycle AFTER (once ready_valid has genuinely gone + // low and node_state has committed) costs one extra + // idle cycle between consecutive dispatches but is + // unambiguously correct. + ready_valid <= 1'b1; + ready_node_id <= first_ready_idx; + ready_x_base <= node_x_base[first_ready_idx]; + ready_w_base <= node_w_base[first_ready_idx]; + ready_n_tiles <= node_n_tiles[first_ready_idx]; + ready_result_addr <= node_result_addr[first_ready_idx]; + end + end + end + +endmodule diff --git a/hardware/v2/rtl/layer_weight_buffer.v b/hardware/v2/rtl/layer_weight_buffer.v new file mode 100644 index 0000000..20767ac --- /dev/null +++ b/hardware/v2/rtl/layer_weight_buffer.v @@ -0,0 +1,93 @@ +`timescale 1ns/1ps + +// ============================================================ +// EXP-0057 -- double-buffered, per-layer resident weight scratchpad. +// +// One layer's worth of weights (up to LAYER_DEPTH entries of +// DATA_WIDTH bits, real BRAM-style array, same coding idiom as +// nms_weight_packed.v's own per-slot memories) stays resident and is +// read MANY times (once per output position that reuses it -- e.g. +// every spatial position a convolutional filter slides across), +// while the NEXT layer's weights are being fetched into the OTHER +// buffer in the background. Buffers swap only when BOTH conditions +// hold: the compute side has finished consuming the active buffer +// (consume_done) AND the fill side has finished loading the other one +// (fill_done) -- matches this project's own established discipline +// (never swap/overwrite data still in use, same spirit as +// sdram_unified_backend.v's own req_pending latch correctness fixes). +// +// This is deliberately NOT the same thing as the existing per-slot +// nms_weight_packed.v buffer: that one holds MAX_TILES tiles for ONE +// job with no reuse across neurons (D-Stress's own zero-reuse case). +// This module exists for the OPPOSITE traffic pattern -- one weight +// block read many times before being replaced -- which is what a +// convolutional filter (or any weight-stationary dataflow) needs. +// ============================================================ +module layer_weight_buffer #( + parameter DATA_WIDTH = 8, + parameter LAYER_DEPTH = 128, + parameter ADDRW = (LAYER_DEPTH <= 1) ? 1 : $clog2(LAYER_DEPTH) +)( + input wire clk, + input wire rst, + + // ---- fill side: writes into the INACTIVE buffer ---- + input wire fill_we, + input wire [ADDRW-1:0] fill_addr, + input wire [DATA_WIDTH-1:0] fill_data, + input wire fill_done, // pulse: inactive buffer fully loaded + + // ---- compute side: reads from the ACTIVE buffer, any number of + // times, any order (real conv access pattern is not necessarily + // sequential -- e.g. im2col-style window reuse) ---- + input wire [ADDRW-1:0] rd_addr, + output wire [DATA_WIDTH-1:0] rd_data, + input wire consume_done, // pulse: compute side is done with the active buffer + + // ---- swap: happens the cycle AFTER both fill_done and + // consume_done have been seen since the last swap -- order- + // independent (a pulse arriving before the other is latched, not + // dropped), matching this project's own req_pending latch idiom ---- + output reg active_sel, // which physical buffer (0/1) is active for reads + output reg swapped // pulses the cycle a swap occurs +); + reg [DATA_WIDTH-1:0] mem0 [0:LAYER_DEPTH-1]; + reg [DATA_WIDTH-1:0] mem1 [0:LAYER_DEPTH-1]; + + reg fill_done_latched, consume_done_latched; + + wire do_swap = fill_done_latched && consume_done_latched; + + always @(posedge clk) begin + if (fill_we) begin + if (active_sel == 1'b0) mem1[fill_addr] <= fill_data; // fill the INACTIVE one + else mem0[fill_addr] <= fill_data; + end + end + + // read from the ACTIVE buffer, combinational (matches + // nms_weight_packed.v's own same-cycle-bypass-free combinational + // read convention for a single-port style array read) + assign rd_data = active_sel ? mem1[rd_addr] : mem0[rd_addr]; + + always @(posedge clk) begin + if (rst) begin + active_sel <= 1'b0; + swapped <= 1'b0; + fill_done_latched <= 1'b0; + consume_done_latched <= 1'b0; + end else begin + swapped <= 1'b0; + + if (fill_done) fill_done_latched <= 1'b1; + if (consume_done) consume_done_latched <= 1'b1; + + if (do_swap) begin + active_sel <= ~active_sel; + swapped <= 1'b1; + fill_done_latched <= 1'b0; + consume_done_latched <= 1'b0; + end + end + end +endmodule diff --git a/hardware/v2/rtl/priority_encoder_lsb.v b/hardware/v2/rtl/priority_encoder_lsb.v new file mode 100644 index 0000000..448282d --- /dev/null +++ b/hardware/v2/rtl/priority_encoder_lsb.v @@ -0,0 +1,70 @@ +`timescale 1ns/1ps + +// ============================================================ +// EXP-0056 -- generic, recursive binary-tree priority encoder +// (lowest-set-bit wins), O(log2(WIDTH)) depth. +// +// MOTIVATION: dependency_manager.v's own first_ready_idx scan (a +// serial for-loop overwriting a register variable across up to +// N_NODES=1024 iterations) is the SAME architectural anti-pattern +// already found and fixed twice elsewhere in this project (ERR-0027, +// neural_director.v's free-slot scan; ERR-0028, activation_fill_ +// ctrl's max-tree; ERR-0029, sdram_unified_backend.v's W-cache hit- +// index) -- a data-dependent sequential overwrite that forces a +// SERIAL dependency chain across every iteration, even though the +// result does not logically require one. Those three fixes used a +// flat one-hot compare + single-level casez priority-encode, correct +// and efficient for their own small widths (4-8 entries). N_NODES can +// be up to 1024 in this project's own real configs -- a single flat +// casez at that width is impractical to hand-write and not guaranteed +// to synthesize as a balanced tree. This module generalizes the SAME +// underlying principle (no serial dependency chain) to arbitrary +// width via recursive halving: each half is encoded independently +// and in parallel (no dependency between them), and only the FINAL +// combine step (low_valid ? low_result : high_result) depends on +// both halves -- giving real O(log2(WIDTH)) depth instead of O(WIDTH). +// +// Semantics: idx = index of the LOWEST set bit in `in` (bit 0 has +// highest priority), valid = |in. This matches dependency_manager.v's +// own original scan exactly: it iterates ri from N_NODES-1 DOWN TO 0, +// unconditionally overwriting first_ready_idx on every match -- the +// LAST (i.e. lowest-index) match therefore wins, not the first one +// found during the loop's own execution order. +// ============================================================ +module priority_encoder_lsb #( + parameter WIDTH = 16, + parameter IDXW = (WIDTH <= 1) ? 1 : $clog2(WIDTH) +)( + input wire [WIDTH-1:0] in, + output wire [IDXW-1:0] idx, + output wire valid +); + generate + if (WIDTH <= 1) begin : GEN_BASE + assign valid = in[0]; + assign idx = {IDXW{1'b0}}; + end else begin : GEN_SPLIT + localparam LOW_W = WIDTH/2; + localparam HIGH_W = WIDTH - LOW_W; + localparam LOW_IDXW = (LOW_W <= 1) ? 1 : $clog2(LOW_W); + localparam HIGH_IDXW = (HIGH_W <= 1) ? 1 : $clog2(HIGH_W); + + wire [LOW_IDXW-1:0] low_idx; + wire low_valid; + wire [HIGH_IDXW-1:0] high_idx; + wire high_valid; + + priority_encoder_lsb #(.WIDTH(LOW_W)) u_low ( + .in(in[LOW_W-1:0]), .idx(low_idx), .valid(low_valid) + ); + priority_encoder_lsb #(.WIDTH(HIGH_W)) u_high ( + .in(in[WIDTH-1:LOW_W]), .idx(high_idx), .valid(high_valid) + ); + + assign valid = low_valid | high_valid; + assign idx = low_valid + ? {{(IDXW-LOW_IDXW){1'b0}}, low_idx} + : ({{(IDXW-HIGH_IDXW){1'b0}}, high_idx} + LOW_W[IDXW-1:0]); + end + endgenerate +endmodule diff --git a/hardware/v2/sim/tb_dependency_manager_fast.v b/hardware/v2/sim/tb_dependency_manager_fast.v new file mode 100644 index 0000000..0f353a7 --- /dev/null +++ b/hardware/v2/sim/tb_dependency_manager_fast.v @@ -0,0 +1,150 @@ +`timescale 1ns/1ps + +// ============================================================ +// EXP-0056 -- bit-exact equivalence check: dependency_manager.v +// (baseline) vs dependency_manager_fast.v (priority_encoder_lsb.v +// fix), at N_NODES=1024 -- the REAL config this project's own +// D-Stress benchmark uses, not the small hand-crafted DAG the +// original tb_dependency_manager.v exercises. Both DUTs driven by the +// IDENTICAL random stimulus every cycle (registration + producer-done +// events), every output compared cycle-by-cycle. Pure random +// (required/producer_ids need not form a realistic DAG -- this +// module's own behavior is well-defined for ANY input sequence, and +// bit-exact equivalence for ANY sequence is exactly the property that +// needs proving here). +// ============================================================ +module tb; + localparam N_NODES = 1024; + localparam MAX_DEPS = 4; + localparam ADDR_WIDTH = 26; + localparam NODE_IDW = $clog2(N_NODES); + + reg clk, rst; + initial begin clk = 0; forever #5 clk = ~clk; end + + reg reg_valid; + reg [NODE_IDW-1:0] reg_node_id; + reg [$clog2(MAX_DEPS+1)-1:0] reg_required; + reg [MAX_DEPS*NODE_IDW-1:0] reg_producer_ids; + reg [ADDR_WIDTH-1:0] reg_x_base, reg_w_base, reg_result_addr; + reg [15:0] reg_n_tiles; + + reg producer_done_valid; + reg [NODE_IDW-1:0] producer_done_node_id; + + reg ready_ready; + + wire reg_ready_a, reg_ready_b; + wire ready_valid_a, ready_valid_b; + wire [NODE_IDW-1:0] ready_node_id_a, ready_node_id_b; + wire [ADDR_WIDTH-1:0] ready_x_base_a, ready_x_base_b; + wire [ADDR_WIDTH-1:0] ready_w_base_a, ready_w_base_b; + wire [15:0] ready_n_tiles_a, ready_n_tiles_b; + wire [ADDR_WIDTH-1:0] ready_result_addr_a, ready_result_addr_b; + wire any_pending_a, any_pending_b; + + dependency_manager #( + .N_NODES(N_NODES), .MAX_DEPS(MAX_DEPS), .ADDR_WIDTH(ADDR_WIDTH) + ) dut_base ( + .clk(clk), .rst(rst), + .reg_valid(reg_valid), .reg_ready(reg_ready_a), .reg_node_id(reg_node_id), + .reg_required(reg_required), .reg_producer_ids(reg_producer_ids), + .reg_x_base(reg_x_base), .reg_w_base(reg_w_base), .reg_n_tiles(reg_n_tiles), + .reg_result_addr(reg_result_addr), + .producer_done_valid(producer_done_valid), .producer_done_node_id(producer_done_node_id), + .ready_valid(ready_valid_a), .ready_ready(ready_ready), .ready_node_id(ready_node_id_a), + .ready_x_base(ready_x_base_a), .ready_w_base(ready_w_base_a), + .ready_n_tiles(ready_n_tiles_a), .ready_result_addr(ready_result_addr_a), + .any_pending(any_pending_a) + ); + + dependency_manager_fast #( + .N_NODES(N_NODES), .MAX_DEPS(MAX_DEPS), .ADDR_WIDTH(ADDR_WIDTH) + ) dut_fast ( + .clk(clk), .rst(rst), + .reg_valid(reg_valid), .reg_ready(reg_ready_b), .reg_node_id(reg_node_id), + .reg_required(reg_required), .reg_producer_ids(reg_producer_ids), + .reg_x_base(reg_x_base), .reg_w_base(reg_w_base), .reg_n_tiles(reg_n_tiles), + .reg_result_addr(reg_result_addr), + .producer_done_valid(producer_done_valid), .producer_done_node_id(producer_done_node_id), + .ready_valid(ready_valid_b), .ready_ready(ready_ready), .ready_node_id(ready_node_id_b), + .ready_x_base(ready_x_base_b), .ready_w_base(ready_w_base_b), + .ready_n_tiles(ready_n_tiles_b), .ready_result_addr(ready_result_addr_b), + .any_pending(any_pending_b) + ); + + integer errors, tests, cyc; + integer seed, i; + integer next_id; + reg [NODE_IDW-1:0] rnd_id; + + task automatic check_equal; + begin + tests = tests + 1; + if (reg_ready_a !== reg_ready_b || ready_valid_a !== ready_valid_b || + any_pending_a !== any_pending_b || + (ready_valid_a && (ready_node_id_a !== ready_node_id_b || + ready_x_base_a !== ready_x_base_b || + ready_w_base_a !== ready_w_base_b || + ready_n_tiles_a !== ready_n_tiles_b || + ready_result_addr_a !== ready_result_addr_b))) begin + $display("FAIL @cycle %0d: base(reg_ready=%b ready_valid=%b node=%0d any_pending=%b) fast(reg_ready=%b ready_valid=%b node=%0d any_pending=%b)", + cyc, reg_ready_a, ready_valid_a, ready_node_id_a, any_pending_a, + reg_ready_b, ready_valid_b, ready_node_id_b, any_pending_b); + errors = errors + 1; + end + end + endtask + + always @(posedge clk) if (!rst) cyc <= cyc + 1; + + initial begin + errors = 0; tests = 0; cyc = 0; seed = 32'hFEEDFACE; + rst = 1; reg_valid = 0; reg_node_id = 0; reg_required = 0; reg_producer_ids = 0; + reg_x_base = 0; reg_w_base = 0; reg_n_tiles = 0; reg_result_addr = 0; + producer_done_valid = 0; producer_done_node_id = 0; + ready_ready = 1; + repeat(5) @(posedge clk); + rst = 0; + + $display("=== random stimulus, N_NODES=1024, 20000 cycles ==="); + next_id = 0; + for (i = 0; i < 20000; i = i + 1) begin + @(posedge clk); + #1; // let combinational outputs settle before sampling/comparing + + // registration: ~15% of cycles, sequential node_id (avoids + // double-registering the same id, which the module itself + // does not need to tolerate -- caller's own responsibility, + // same as the real Director/graph-loader upstream) + reg_valid = (($random(seed) % 100) < 15) && (next_id < N_NODES); + if (reg_valid) begin + reg_node_id = next_id[NODE_IDW-1:0]; + reg_required = $random(seed) % (MAX_DEPS+1); + reg_x_base = $random(seed); + reg_w_base = $random(seed); + reg_n_tiles = $random(seed); + reg_result_addr = $random(seed); + reg_producer_ids = {$random(seed), $random(seed)}; // random bits, need not be a valid/realistic producer graph + next_id = next_id + 1; + end + + // producer-done: ~10% of cycles, random already-issued id + producer_done_valid = (($random(seed) % 100) < 10) && (next_id > 0); + if (producer_done_valid) begin + rnd_id = ($random(seed) % next_id); + producer_done_node_id = rnd_id; + end + + // ready_ready: randomly withhold backpressure sometimes, + // to exercise the "ready_valid held, not yet accepted" path + ready_ready = (($random(seed) % 100) < 80); + + check_equal; + end + + $display("=== %0d/%0d cycles matched, %0d mismatches ===", tests-errors, tests, errors); + if (errors == 0) $display("ALL TESTS PASSED (tb_dependency_manager_fast, bit-exact vs baseline)"); + $finish; + end +endmodule diff --git a/hardware/v2/sim/tb_layer_reuse_vs_zero_reuse.v b/hardware/v2/sim/tb_layer_reuse_vs_zero_reuse.v new file mode 100644 index 0000000..f87520a --- /dev/null +++ b/hardware/v2/sim/tb_layer_reuse_vs_zero_reuse.v @@ -0,0 +1,260 @@ +`timescale 1ns/1ps + +// ============================================================ +// EXP-0057 -- real measured comparison: weight-stationary layer reuse +// (layer_weight_buffer.v, double-buffered, background-prefetched) +// vs the zero-reuse D-Stress-style pattern (every read is its own +// independent external fetch), BOTH driven through the SAME real, +// already-verified open-row SDR SDRAM controller (sdram_controller_ +// openrow.v, EXP-0054) and behavioral chip model (sdram_model.v) -- +// no DDR3, no clock change, the exact hardware this project already +// has. Answers directly: does weight reuse alone (no new memory +// hardware) close enough of the gap that DDR3 stops being necessary +// for a workload class that actually has reuse (e.g. a CNN layer), +// as opposed to D-Stress's own deliberately zero-reuse worst case? +// +// SAME total useful-byte-consumption for both cases (fair +// comparison): L=16 "layers" x M=16 reuses x LAYER_DEPTH=128 bytes = +// 32768 total byte-reads -- identical to D-Stress's own 256x128=32768 +// total bytes this whole project has been benchmarked against all +// session. +// REUSE case: L x LAYER_DEPTH = 2048 bytes actually fetched from +// SDRAM (each layer's weights fetched ONCE, reused +// M times from the local double buffer). +// ZERO-REUSE case: L x M x LAYER_DEPTH = 32768 bytes fetched (every +// single read is independent, matching D-Stress). +// ============================================================ +module tb; + localparam BURST_LEN = 8; + localparam ROW_BITS = 13; + localparam COL_BITS = 10; + localparam BANK_BITS = 2; + localparam ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS; + localparam ALIGN_BITS = $clog2(BURST_LEN); + localparam CLK_FREQ_MHZ = 64; + localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ; + + localparam LAYER_DEPTH = 128; // bytes/layer weight block (matches P_IN*MAX_TILES=8*16 tile convention) + localparam L = 16; // number of layers + localparam M = 16; // reuses per layer (e.g. spatial positions a filter slides across) + localparam WORDS_PER_LAYER = LAYER_DEPTH/2; // sdram_controller word=16-bit + localparam BURSTS_PER_LAYER = LAYER_DEPTH/(2*BURST_LEN); // 16-byte (8-word) transactions per layer + + reg clk = 0; + always #(CLK_PERIOD_NS/2.0) clk = ~clk; + reg rst; + + integer cyc; + always @(posedge clk) if (!rst) cyc <= cyc + 1; + + // ================= shared physical SDRAM (real open-row controller) ================= + reg ctrl_req, ctrl_wr; + reg [ADDR_WIDTH-1:0] ctrl_addr; + reg [16*BURST_LEN-1:0] ctrl_wdata; + reg [2*BURST_LEN-1:0] ctrl_wmask; + wire [16*BURST_LEN-1:0] ctrl_rdata; + wire ctrl_ready, ctrl_busy; + wire cke, cs_n, ras_n, cas_n, we_n; + wire [BANK_BITS-1:0] ba; + wire [ROW_BITS-1:0] a; + wire [15:0] dq; + wire [1:0] dqm; + + sdram_controller_openrow #( + .CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN), + .ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS) + ) u_ctrl ( + .clk(clk), .rst(rst), + .req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr), .wdata(ctrl_wdata), .wmask(ctrl_wmask), + .rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy), + .sdram_cke(cke), .sdram_cs_n(cs_n), .sdram_ras_n(ras_n), .sdram_cas_n(cas_n), .sdram_we_n(we_n), + .sdram_ba(ba), .sdram_a(a), .sdram_dq(dq), .sdram_dqm(dqm) + ); + sdram_model #( + .CLK_FREQ_MHZ(CLK_FREQ_MHZ), .ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS) + ) u_mem ( + .clk(clk), .cke(cke), .cs_n(cs_n), .ras_n(ras_n), .cas_n(cas_n), .we_n(we_n), + .ba(ba), .a(a), .dq(dq), .dqm(dqm) + ); + + task automatic sdram_write_burst(input [ADDR_WIDTH-1:0] word_addr, input [16*BURST_LEN-1:0] data); + begin + @(posedge clk); while (ctrl_busy) @(posedge clk); + ctrl_req = 1'b1; ctrl_wr = 1'b1; ctrl_addr = word_addr; ctrl_wdata = data; ctrl_wmask = {(2*BURST_LEN){1'b0}}; + @(posedge clk); ctrl_req = 1'b0; + while (!ctrl_ready) @(posedge clk); + end + endtask + task automatic sdram_read_burst(input [ADDR_WIDTH-1:0] word_addr, output [16*BURST_LEN-1:0] data); + begin + @(posedge clk); while (ctrl_busy) @(posedge clk); + ctrl_req = 1'b1; ctrl_wr = 1'b0; ctrl_addr = word_addr; ctrl_wmask = {(2*BURST_LEN){1'b0}}; + @(posedge clk); ctrl_req = 1'b0; + while (!ctrl_ready) @(posedge clk); + data = ctrl_rdata; + end + endtask + + // ================= layer_weight_buffer under test ================= + reg fill_we; + reg [$clog2(LAYER_DEPTH)-1:0] fill_addr; + reg [7:0] fill_data; + reg fill_done; + reg [$clog2(LAYER_DEPTH)-1:0] rd_addr; + wire [7:0] rd_data; + reg consume_done; + wire active_sel, swapped; + + layer_weight_buffer #(.DATA_WIDTH(8), .LAYER_DEPTH(LAYER_DEPTH)) u_lwb ( + .clk(clk), .rst(rst), + .fill_we(fill_we), .fill_addr(fill_addr), .fill_data(fill_data), .fill_done(fill_done), + .rd_addr(rd_addr), .rd_data(rd_data), .consume_done(consume_done), + .active_sel(active_sel), .swapped(swapped) + ); + + integer errors, tests; + + // pre-load SDRAM with L distinct layer patterns, at word address layer_idx*WORDS_PER_LAYER + task automatic preload_sdram_layers; + integer li, bi; + reg [16*BURST_LEN-1:0] burst_data; + integer wb; + begin + for (li = 0; li < L; li = li + 1) begin + for (bi = 0; bi < BURSTS_PER_LAYER; bi = bi + 1) begin + for (wb = 0; wb < BURST_LEN; wb = wb + 1) + burst_data[wb*16 +: 16] = {8'(8'h20+li), 8'(bi*BURST_LEN+wb)}; + sdram_write_burst((li*WORDS_PER_LAYER + bi*BURST_LEN), burst_data); + end + end + end + endtask + + // fetch layer li's weights (bulk sequential, BURSTS_PER_LAYER transactions) + // into the layer_weight_buffer's inactive side + task automatic prefetch_layer(input integer li); + integer bi, wb; + reg [16*BURST_LEN-1:0] burst_data; + begin + for (bi = 0; bi < BURSTS_PER_LAYER; bi = bi + 1) begin + sdram_read_burst((li*WORDS_PER_LAYER + bi*BURST_LEN), burst_data); + for (wb = 0; wb < BURST_LEN; wb = wb + 1) begin + @(posedge clk); + fill_we = 1'b1; + fill_addr = (bi*BURST_LEN + wb) & (2*BURST_LEN-1) | (bi*2*BURST_LEN); // byte index within layer + fill_addr = bi*(2*BURST_LEN) + wb*2; // low byte of word wb + fill_data = burst_data[wb*16 +: 8]; + @(posedge clk); + fill_addr = bi*(2*BURST_LEN) + wb*2 + 1; // high byte of word wb + fill_data = burst_data[wb*16+8 +: 8]; + end + end + @(posedge clk); fill_we = 1'b0; + fill_done = 1'b1; @(posedge clk); fill_done = 1'b0; + end + endtask + + task automatic consume_layer_check(input integer li, input integer errors_before, output integer errors_after); + integer r, k; + reg [7:0] expected; + begin + errors_after = errors_before; + for (r = 0; r < M; r = r + 1) begin + for (k = 0; k < LAYER_DEPTH; k = k + 1) begin + rd_addr = k[$clog2(LAYER_DEPTH)-1:0]; + #1; + tests = tests + 1; + expected = 8'(8'h20+li) ; // high byte of the 16-bit word pattern for even k, low byte pattern for odd k -- see preload + // preload packed {8'h20+li, byte_idx} per WORD (16-bit): low byte = byte_idx, high byte = 8'h20+li + if (k[0] == 1'b0) expected = {1'b0, k[7:1]}; // low byte of word = WORD index (bi*BURST_LEN+wb), i.e. k/2 -- see preload_sdram_layers + else expected = 8'(8'h20+li); // high byte of word = layer tag + if (rd_data !== expected) begin + $display("FAIL layer=%0d reuse=%0d k=%0d: expected %h got %h", li, r, k, expected, rd_data); + errors_after = errors_after + 1; + end + @(posedge clk); + end + end + consume_done = 1'b1; @(posedge clk); consume_done = 1'b0; + end + endtask + + integer li_i; + integer t0, total_cycles_reuse, total_cycles_zeroreuse; + + // zero-reuse baseline: L*M independent reads, each LAYER_DEPTH bytes, + // NO local buffering -- every single "reuse" goes straight to SDRAM, + // matching D-Stress's own access pattern exactly (through the SAME + // real open-row controller). + task automatic zero_reuse_baseline; + integer li, r, bi; + reg [16*BURST_LEN-1:0] junk; + begin + for (li = 0; li < L; li = li + 1) begin + for (r = 0; r < M; r = r + 1) begin + for (bi = 0; bi < BURSTS_PER_LAYER; bi = bi + 1) begin + sdram_read_burst((li*WORDS_PER_LAYER + bi*BURST_LEN), junk); + end + end + end + end + endtask + + initial begin + errors = 0; tests = 0; cyc = 0; + rst = 1; ctrl_req = 0; ctrl_wr = 0; ctrl_addr = 0; ctrl_wdata = 0; ctrl_wmask = 0; + fill_we = 0; fill_addr = 0; fill_data = 0; fill_done = 0; rd_addr = 0; consume_done = 0; + repeat(5) @(posedge clk); + rst = 0; + @(posedge clk); while (ctrl_busy) @(posedge clk); + + $display("=== preload SDRAM with %0d distinct layer patterns ===", L); + preload_sdram_layers; + + $display("=== REUSE case correctness pass: %0d layers x %0d reuses, double-buffered background prefetch (data check only, not timed) ===", L, M); + prefetch_layer(0); + consume_done = 1'b1; @(posedge clk); consume_done = 1'b0; // trigger initial swap + for (li_i = 0; li_i < L; li_i = li_i + 1) begin + fork + consume_layer_check(li_i, errors, errors); + begin + if (li_i+1 < L) prefetch_layer(li_i+1); + end + join + end + $display(" correctness: %0d/%0d, %0d errors", tests-errors, tests, errors); + + // ---- FAIR timing comparison: measure ONLY the real SDRAM + // fetch cost in each case (the actual question this benchmark + // exists to answer -- how much does reuse reduce dependence on + // external memory bandwidth). Compute-side consumption cost is + // deliberately excluded from BOTH measurements here -- it is + // identical in both cases (same neural_processor.v pipeline + // rate regardless of where weights come from) and including it + // asymmetrically was a real bug in an earlier version of this + // testbench (see EXP-0057 writeup). ---- + $display("=== REUSE case: pure SDRAM fetch time for %0d layers (%0d bytes total) ===", L, L*LAYER_DEPTH); + @(posedge clk); while (ctrl_busy) @(posedge clk); + t0 = cyc; + for (li_i = 0; li_i < L; li_i = li_i + 1) prefetch_layer(li_i); + total_cycles_reuse = cyc - t0; + $display(" REUSE: %0d cycles to fetch %0d bytes from SDRAM (each layer fetched ONCE, reused %0d x locally)", + total_cycles_reuse, L*LAYER_DEPTH, M); + + $display("=== ZERO-REUSE baseline: pure SDRAM fetch time for %0d bytes (every reuse fetched independently) ===", L*M*LAYER_DEPTH); + @(posedge clk); while (ctrl_busy) @(posedge clk); + t0 = cyc; + zero_reuse_baseline; + total_cycles_zeroreuse = cyc - t0; + $display(" ZERO-REUSE: %0d cycles to fetch %0d bytes from SDRAM", + total_cycles_zeroreuse, L*M*LAYER_DEPTH); + + $display("=== RESULT ==="); + $display(" REUSE case data correctness: %0d/%0d, %0d errors", tests-errors, tests, errors); + $display(" REAL measured speedup from weight reuse alone (SAME hardware, no DDR3, no clock change): %0f x", + total_cycles_zeroreuse * 1.0 / total_cycles_reuse); + + if (errors == 0) $display("ALL DATA CHECKS PASSED (tb_layer_reuse_vs_zero_reuse)"); + $finish; + end +endmodule diff --git a/hardware/v2/sim/tb_layer_weight_buffer.v b/hardware/v2/sim/tb_layer_weight_buffer.v new file mode 100644 index 0000000..f1cb586 --- /dev/null +++ b/hardware/v2/sim/tb_layer_weight_buffer.v @@ -0,0 +1,141 @@ +`timescale 1ns/1ps + +// ============================================================ +// EXP-0057 -- isolated correctness check for layer_weight_buffer.v: +// fill buffer A, swap, read A many times while filling B, swap again +// (order-independent: sometimes fill_done arrives first, sometimes +// consume_done does), verify data integrity and correct buffer +// selection throughout. +// ============================================================ +module tb; + localparam DATA_WIDTH = 8; + localparam LAYER_DEPTH = 128; + localparam ADDRW = $clog2(LAYER_DEPTH); + + reg clk = 0; + always #5 clk = ~clk; + reg rst; + + reg fill_we; + reg [ADDRW-1:0] fill_addr; + reg [DATA_WIDTH-1:0] fill_data; + reg fill_done; + reg [ADDRW-1:0] rd_addr; + wire [DATA_WIDTH-1:0] rd_data; + reg consume_done; + wire active_sel; + wire swapped; + + layer_weight_buffer #( + .DATA_WIDTH(DATA_WIDTH), .LAYER_DEPTH(LAYER_DEPTH) + ) dut ( + .clk(clk), .rst(rst), + .fill_we(fill_we), .fill_addr(fill_addr), .fill_data(fill_data), .fill_done(fill_done), + .rd_addr(rd_addr), .rd_data(rd_data), .consume_done(consume_done), + .active_sel(active_sel), .swapped(swapped) + ); + + integer errors, tests, i; + + task automatic fill_layer(input [7:0] pattern_base); + integer k; + begin + for (k = 0; k < LAYER_DEPTH; k = k + 1) begin + @(posedge clk); + fill_we = 1'b1; fill_addr = k[ADDRW-1:0]; fill_data = pattern_base + k[7:0]; + end + @(posedge clk); + fill_we = 1'b0; + fill_done = 1'b1; + @(posedge clk); + fill_done = 1'b0; + end + endtask + + task automatic read_and_check_layer(input [7:0] pattern_base, input integer n_reuses); + integer r, k; + begin + for (r = 0; r < n_reuses; r = r + 1) begin + for (k = 0; k < LAYER_DEPTH; k = k + 1) begin + rd_addr = k[ADDRW-1:0]; + #1; + tests = tests + 1; + if (rd_data !== (pattern_base + k[7:0])) begin + $display("FAIL reuse=%0d addr=%0d: expected %0d got %0d", r, k, pattern_base+k[7:0], rd_data); + errors = errors + 1; + end + @(posedge clk); + end + end + consume_done = 1'b1; + @(posedge clk); + consume_done = 1'b0; + end + endtask + + initial begin + errors = 0; tests = 0; + rst = 1; fill_we = 0; fill_addr = 0; fill_data = 0; fill_done = 0; + rd_addr = 0; consume_done = 0; + repeat(3) @(posedge clk); + rst = 0; + + $display("=== fill layer 0 (pattern 0x10), swap in ==="); + fill_layer(8'h10); + if (active_sel !== 1'b0) begin + $display("FAIL: expected active_sel=0 before any swap (fill alone must not swap)"); + errors = errors + 1; + end + // consume_done from reset state (never asserted yet) + fill_done just latched -> not swapped yet + // now assert consume_done once (simulating "nothing to consume yet, first layer") to trigger the swap + consume_done = 1'b1; @(posedge clk); consume_done = 1'b0; + @(posedge clk); #1; // swap logic is 2-cycle latency from the triggering pulse; let it settle + if (active_sel !== 1'b1) begin + $display("FAIL: expected active_sel=1 after first swap, got %b", active_sel); + errors = errors + 1; + end + tests = tests + 1; + + $display("=== read layer 0 (now active, 5 reuses), meanwhile fill layer 1 (pattern 0x40) ==="); + fork + read_and_check_layer(8'h10, 5); + fill_layer(8'h40); + join + @(posedge clk); #1; + if (active_sel !== 1'b0) begin + $display("FAIL: expected active_sel=0 after second swap (back to buffer 0, now holding layer1 data), got %b", active_sel); + errors = errors + 1; + end + tests = tests + 1; + + $display("=== read layer 1 (pattern 0x40, 3 reuses), meanwhile fill layer 2 (pattern 0x80) -- fill finishes FIRST this time ==="); + fork + begin + fill_layer(8'h80); + end + begin + #50; // let fill get a head start, so fill_done lands before consume_done + read_and_check_layer(8'h40, 3); + end + join + @(posedge clk); #1; + if (active_sel !== 1'b1) begin + $display("FAIL: expected active_sel=1 after third swap, got %b", active_sel); + errors = errors + 1; + end + tests = tests + 1; + + $display("=== read layer 2 (pattern 0x80, 4 reuses), verify final data ==="); + read_and_check_layer(8'h80, 4); + consume_done = 1'b1; @(posedge clk); consume_done = 1'b0; // extra pulse, no fill pending: must NOT swap without a fill_done + if (active_sel !== 1'b1) begin + $display("FAIL: consume_done alone (no matching fill_done) must not cause a swap, got active_sel=%b", active_sel); + errors = errors + 1; + end + tests = tests + 1; + + $display("=== %0d/%0d passed, %0d errors ===", tests-errors, tests, errors); + if (errors == 0) $display("ALL TESTS PASSED (tb_layer_weight_buffer)"); + $finish; + end +endmodule diff --git a/hardware/v2/sim/tb_maxtree_n16.v b/hardware/v2/sim/tb_maxtree_n16.v new file mode 100644 index 0000000..3949053 --- /dev/null +++ b/hardware/v2/sim/tb_maxtree_n16.v @@ -0,0 +1,72 @@ +`timescale 1ns/1ps + +// ============================================================ +// EXP-0056 -- isolated correctness check for the N_SLOTS==16 +// balanced max-tree added to nms_activation_fill_ctrl_v3_n16.v, +// against the SAME flat-scan reference the original module's own +// GEN_MAXTREE_FALLBACK uses (the two must always agree -- that +// fallback path is explicitly documented as "correct but not +// optimized", i.e. the golden reference for what ANY replacement +// must compute). Random 16-way max over 10000 vectors. +// ============================================================ +module tb; + reg [15:0] v [0:15]; + integer i, k, seed, errors, tests; + reg [15:0] ref_max; + + // exact mirror of nms_activation_fill_ctrl_v3_n16.v's own + // GEN_MAXTREE_N16 combinational tree + wire [15:0] m0 = (v[0] > v[1]) ? v[0] : v[1]; + wire [15:0] m1 = (v[2] > v[3]) ? v[2] : v[3]; + wire [15:0] m2 = (v[4] > v[5]) ? v[4] : v[5]; + wire [15:0] m3 = (v[6] > v[7]) ? v[6] : v[7]; + wire [15:0] m4 = (v[8] > v[9]) ? v[8] : v[9]; + wire [15:0] m5 = (v[10] > v[11]) ? v[10] : v[11]; + wire [15:0] m6 = (v[12] > v[13]) ? v[12] : v[13]; + wire [15:0] m7 = (v[14] > v[15]) ? v[14] : v[15]; + wire [15:0] m01 = (m0 > m1) ? m0 : m1; + wire [15:0] m23 = (m2 > m3) ? m2 : m3; + wire [15:0] m45 = (m4 > m5) ? m4 : m5; + wire [15:0] m67 = (m6 > m7) ? m6 : m7; + wire [15:0] m0123 = (m01 > m23) ? m01 : m23; + wire [15:0] m4567 = (m45 > m67) ? m45 : m67; + wire [15:0] max_final = (m0123 > m4567) ? m0123 : m4567; + + initial begin + errors = 0; tests = 0; seed = 32'hA5A5F00D; + + // targeted: all-zero, max at every single position + for (k = 0; k < 16; k = k + 1) v[k] = 16'h0; + #1; tests = tests + 1; + if (max_final !== 16'h0) begin + $display("FAIL all-zero: got %0d", max_final); errors = errors + 1; + end + for (i = 0; i < 16; i = i + 1) begin + for (k = 0; k < 16; k = k + 1) v[k] = 16'h1; + v[i] = 16'hFFFF; + #1; tests = tests + 1; + if (max_final !== 16'hFFFF) begin + $display("FAIL max-at-%0d: got %0d", i, max_final); errors = errors + 1; + end + end + + // random + for (i = 0; i < 10000; i = i + 1) begin + ref_max = 16'h0; + for (k = 0; k < 16; k = k + 1) begin + v[k] = $random(seed); + if (v[k] > ref_max) ref_max = v[k]; + end + #1; + tests = tests + 1; + if (max_final !== ref_max) begin + $display("FAIL random iter=%0d: expected %0d got %0d", i, ref_max, max_final); + errors = errors + 1; + end + end + + $display("=== %0d/%0d passed, %0d errors ===", tests-errors, tests, errors); + if (errors == 0) $display("ALL TESTS PASSED (tb_maxtree_n16)"); + $finish; + end +endmodule diff --git a/hardware/v2/sim/tb_priority_encoder_lsb.v b/hardware/v2/sim/tb_priority_encoder_lsb.v new file mode 100644 index 0000000..03e4240 --- /dev/null +++ b/hardware/v2/sim/tb_priority_encoder_lsb.v @@ -0,0 +1,133 @@ +`timescale 1ns/1ps + +// ============================================================ +// EXP-0056 -- isolated correctness check for priority_encoder_lsb.v +// against a trivial behavioral reference (linear scan, allowed to be +// slow since it is testbench-only), at both a small width (16, +// dependency_manager.v's own module default) and the real large width +// this fix targets (1024, the real N_NODES this project actually +// uses for D-Stress). Exhaustive at WIDTH=16 (65536 patterns), random +// at WIDTH=1024 (exhaustive is infeasible: 2^1024 patterns). +// ============================================================ +module tb; + localparam W_SMALL = 16; + localparam IDXW_SMALL = $clog2(W_SMALL); + + reg [W_SMALL-1:0] in_small; + wire [IDXW_SMALL-1:0] idx_small; + wire valid_small; + + priority_encoder_lsb #(.WIDTH(W_SMALL)) dut_small ( + .in(in_small), .idx(idx_small), .valid(valid_small) + ); + + localparam W_BIG = 1024; + localparam IDXW_BIG = $clog2(W_BIG); + + reg [W_BIG-1:0] in_big; + wire [IDXW_BIG-1:0] idx_big; + wire valid_big; + + priority_encoder_lsb #(.WIDTH(W_BIG)) dut_big ( + .in(in_big), .idx(idx_big), .valid(valid_big) + ); + + function automatic integer ref_lowest_set_bit(input [W_BIG-1:0] v, input integer width); + integer k; + begin + ref_lowest_set_bit = -1; + for (k = width-1; k >= 0; k = k - 1) + if (v[k]) ref_lowest_set_bit = k; + end + endfunction + + integer errors, tests; + integer i, ref_idx; + integer seed; + + initial begin + errors = 0; tests = 0; seed = 32'hDEC0DE; + + $display("=== TEST 1: WIDTH=16, exhaustive (65536 patterns) ==="); + for (i = 0; i < 65536; i = i + 1) begin + in_small = i[W_SMALL-1:0]; + #1; + ref_idx = ref_lowest_set_bit(i[W_BIG-1:0], W_SMALL); + tests = tests + 1; + if (ref_idx == -1) begin + if (valid_small !== 1'b0) begin + $display("FAIL pattern=%b: expected valid=0, got valid=%b", in_small, valid_small); + errors = errors + 1; + end + end else begin + if (valid_small !== 1'b1 || idx_small !== ref_idx[IDXW_SMALL-1:0]) begin + $display("FAIL pattern=%b: expected idx=%0d valid=1, got idx=%0d valid=%b", + in_small, ref_idx, idx_small, valid_small); + errors = errors + 1; + end + end + end + $display(" TEST 1: %0d/%0d passed", tests-errors, tests); + + $display("=== TEST 2: WIDTH=1024, targeted + random (10000 patterns) ==="); + // targeted: all-zero, single-bit at every position, all-ones + in_big = {W_BIG{1'b0}}; + #1; + tests = tests + 1; + if (valid_big !== 1'b0) begin + $display("FAIL all-zero: expected valid=0, got valid=%b", valid_big); + errors = errors + 1; + end + for (i = 0; i < W_BIG; i = i + 1) begin + in_big = {W_BIG{1'b0}}; + in_big[i] = 1'b1; + #1; + tests = tests + 1; + if (valid_big !== 1'b1 || idx_big !== i[IDXW_BIG-1:0]) begin + $display("FAIL single-bit@%0d: expected idx=%0d valid=1, got idx=%0d valid=%b", + i, i, idx_big, valid_big); + errors = errors + 1; + end + end + in_big = {W_BIG{1'b1}}; + #1; + ref_idx = ref_lowest_set_bit(in_big, W_BIG); + tests = tests + 1; + if (valid_big !== 1'b1 || idx_big !== ref_idx[IDXW_BIG-1:0]) begin + $display("FAIL all-ones: expected idx=%0d valid=1, got idx=%0d valid=%b", + ref_idx, idx_big, valid_big); + errors = errors + 1; + end + // random + for (i = 0; i < 10000; i = i + 1) begin + in_big = {$random(seed), $random(seed), $random(seed), $random(seed), + $random(seed), $random(seed), $random(seed), $random(seed), + $random(seed), $random(seed), $random(seed), $random(seed), + $random(seed), $random(seed), $random(seed), $random(seed), + $random(seed), $random(seed), $random(seed), $random(seed), + $random(seed), $random(seed), $random(seed), $random(seed), + $random(seed), $random(seed), $random(seed), $random(seed), + $random(seed), $random(seed), $random(seed), $random(seed)}; + #1; + ref_idx = ref_lowest_set_bit(in_big, W_BIG); + tests = tests + 1; + if (ref_idx == -1) begin + if (valid_big !== 1'b0) begin + $display("FAIL random iter=%0d: expected valid=0, got valid=%b", i, valid_big); + errors = errors + 1; + end + end else begin + if (valid_big !== 1'b1 || idx_big !== ref_idx[IDXW_BIG-1:0]) begin + $display("FAIL random iter=%0d: expected idx=%0d valid=1, got idx=%0d valid=%b", + i, ref_idx, idx_big, valid_big); + errors = errors + 1; + end + end + end + $display(" TEST 2: %0d/%0d passed", tests-errors, tests); + + $display("=== %0d/%0d total, %0d errors ===", tests-errors, tests, errors); + if (errors == 0) $display("ALL TESTS PASSED (tb_priority_encoder_lsb)"); + $finish; + end +endmodule