FPGA-Neural-Datasheet

T

micheleandClaude Sonnet 5 ffc1c7ccfc docs: reflect flash #1 removal and the N=4 8/8 timing recovery

Datasheet and pinouts.md updated to the current, real state after
today's session: flash #1 was implemented then removed (user's own
MHz-over-persistence priority call), the clock-closure table now
shows the post-revert, post-DEC-0042 numbers (N_SLOTS=4 @ 64MHz 8/8,
worst 64.55MHz/best 72.37MHz; N_SLOTS=8 deferred by explicit user
request), and the FPGA_DATA_READY any_pending formula is updated to
the real counter-based implementation (credited to the user's own
diagnosis) that fixed the last failing N=4 seed.

Compiled clean (45 pages, 0 errors).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

2026-09-07 19:20:57 +02:00

files/docs/datasheet

docs: reflect flash #1 removal and the N=4 8/8 timing recovery

2026-09-07 19:20:57 +02:00

.gitignore

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

ecp5_eval_flash_instructions.pdf

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

FPGA-EB-02017-1-3-ECP5-Evaluation-Board.pdf

docs: bring datasheet/ into the main repo under hardware/v2/docs