periscope/frontend/content/changelog.md

# Changelog

What's new in Periscope.

## 2.33.1 — 2026-09-20 — ESD/PI filters, ERROR-first sort, findings tree

PE-ESD-001 only on J* ∩ IC nets (no NC / unconnected / VSYS/GND/3V3 spam). PE-PI-001 treats any capacitor on the rail, including KiCad `/` names, as decoupling. Report API and UI sort ERROR then WARNING then INFO, then RULE > RISK > REVIEW > INFO. The report left list is an expand-on-click tree (IC → pin/net → cards), not a dump of open groups.

- [Fixed] Connector GPIO / onboard rails no longer flood PE-ESD-001.
- [Fixed] Bulk or slash-prefixed caps (C68 `/VBUS`, C71–C75 VSYS) suppress “no local cap”.
- [Changed] GET `/report` and `complete_findings` order by severity then class.
- [Changed] Findings sidebar is a collapsed tree; PCB exam cards live in the same tree.



Usable slices (not a platform): component→pin→net→block inventory, capacitor PASS/MARGIN/RISK from Vop/Vrated, RC/strap timing only with numbers, local vs bulk PI, ESD and HS return as REVIEW.

- [Fixed] `complete_finding` clamps ERROR unless `finding_class=RULE` and `provenance=MANDATORY` (LLM REVIEW cannot stay ERROR).
- [New] `hierarchy.json` + `PE-HIER-001` dangling IC pins.
- [New] Derating table `stress` PASS/MARGIN/RISK; findings `PE-DRT-001/002/003`.
- [New] `PE-TIM-001/002` skip without R/C and t_reset or Vih/Vil.
- [New] `PE-PI-001/002` local vs bulk; distance only with `layout_rules` mm.
- [New] `PE-ESD-001`, `PE-RET-001` are REVIEW, never RULE ERROR.

## 2.32.1 — 2026-09-20 — PCB Action on card + parsed geometry in AI context

Finding cards always show an **Action.** sentence (`action`, else `recommendation`, else a default). PCB AI context now includes vias under the footprint, copper thickness, nearby trace widths, courtyard, and keepout polygons from `.kicad_pcb`.

- [Fixed] Layout/AI findings no longer show an empty Action chip; the sentence is on the card.
- [Changed] PCB exam injects parsed via counts/drills, stackup thickness, pin-net widths, courtyard/keepout. Insufficient evidence only when those extracts are empty.
- [Changed] submit_review `recommendation` is required for INFO as well as ERROR/WARNING.

## 2.32.0 — 2026-09-20 — Finding engine (schema + PCB)

Same finding object on schematic analysis and PCB exam: FACT / REQUIREMENT / INFERENCE, datasheet provenance in the rule DB, RULE vs REVIEW, designer decisions, independent severity/confidence/evidence.

- [New] `docs/motore-finding.md` — engine spec. `finding_engine.py` + `decisions.json`.
- [New] Report cards show Fact / Requirement / Inference, class, provenance, insufficient evidence.
- [Changed] Recommended datasheet notes cannot stay ERROR. LLM findings are REVIEW, never RULE.
- [Changed] Schematic and PCB share `library/extracted`; PCB does not re-read the PDF.

## 2.31.0 — 2026-09-20 — Shared library PCB exam (no second PDF pass)

Schematic and PCB share `library/extracted`. PCB AI consumes that cache (pintable required; no PDF attach). Report **PCB exam** section plus power-trace/thermal checks.

- [New] Report section **PCB exam** (`source=pcb_review` and PE-PWR/THM/VIA/KEL/STCH).
- [New] `PE-PWR-001` width × copper vs I_load (IPC-2221 only with stackup + Tjmax).
- [New] `PE-THM-001` dissipation vs courtyard vias/pour; `PE-VIA-001` via share of I_load (INFO).
- [New] `PE-KEL-001` Kelvin/sense on a shared load net; `PE-STCH-001` GND stitch in a signal bbox over a pour.
- [Changed] PCB review skips ICs without library pintable (“run schematic review first”).

## 2.30.0 — 2026-09-19 — PCB review pipeline (exam, not auto-place)

Parallel `MODE=pcb` job examines an uploaded `.kicad_pcb`: domains/groups, trace inventory, deterministic layout checks, and per-IC AI datasheet review. Findings merge into the report with a Layout filter. No packing or pcbnew write-back.

- [New] `POST /api/pipeline/{id}/pcb/start` — PCB exam job (`pcb_status`).
- [New] Deterministic `PE-LAY-*`, `PE-PLC-*`, `PE-SI-001`, `PE-DRT-001` with required recommendations.
- [New] AI PCB review (same loop as schematic) with layout/domain context.
- [Changed] Schematic review no longer seeds placement/SI checks.

## 2.29.1 — 2026-09-13 — Fix sign-in /login 404 after rebrand

Landing CTAs pointed at `/login`, which did not exist (page is `/sign-in`). Added redirects, accepted legacy JWT issuer `pinscope-local`, and CORS for both Periscope and Pinscope hosts.

- [Fixed] `/login` → `/sign-in`, `/register` → `/sign-up`; marketing links updated.
- [Fixed] JWT decode accepts `pinscope-local` issuer from pre-rebrand sessions.
- [Fixed] Deploy script CORS includes both public hostnames.

## 2.29.0 — 2026-09-13 — Rebrand to Periscope

Product name, package (`periscopex`), Docker containers, deploy script, and default site URL are now **Periscope** (`https://periscope.michelebigi.it`). Deterministic finding IDs use the `PE-*` prefix. Existing project.json `pinscope_version` and browser storage keys are still read.

- [Changed] Brand Pinscope → Periscope across UI, docs, and APIs.
- [Changed] `backend/pinscopex` → `backend/periscopex`; rule IDs `PS-*` → `PE-*`.
- [Changed] Default host / update script → `periscope.michelebigi.it` / `update-periscope.sh`.

## 2.28.12 — 2026-09-13 — Antenna templates: IFA / meander / stub + .kicad_mod

Progetta antenna now returns a full parametric drawing: polyline segments (mm), SVG preview, and a downloadable KiCad footprint. Choose IFA, meander, or stub; geometry scales to the `antenna` zone when present. Still a routing template — no EM/VSWR invented.

- [New] `antenna_geometry.py` (IFA / meander / stub → segments + SVG + `.kicad_mod`).
- [Changed] `POST /antenna/design` accepts `template`; recipe includes `geometry`.
- [Changed] RF / Impedance Progetta UI: template select, SVG preview, download footprint.

## 2.28.11 — 2026-09-13 — RF / Impedance: verify antenna + design recipe

Project tab renamed **RF / Impedance**. Verify matching from IC ANT/RF pins toward an `ANT*` / `ANT_FEED` marker; Progetta returns microstrip `w` for 50 Ω (stackup or UI h/εr), optional λ/4 length from `f0`, and antenna-zone bbox. Auto-draw copper comes later — no EM/VSWR invented.

- [New] `antenna_rf.py` + `GET/POST /api/projects/{id}/antenna`.
- [New] Verify + Progetta cards on the impedance panel.
- [Changed] Sidebar label **RF / Impedance**.

## 2.28.10 — 2026-09-13 — Classify strap/bootstrap satellites; hide other

Caps on EN/BOOT/REGN/PMID and bootstrap caps between IC pins get real roles. Unclassified `other` parts are dropped from satellites and assemble_order.

- [Changed] `_role_hint` classifies GND bypass on bias/strap nets and flying bootstrap caps.
- [Changed] Assemble / IC groups omit `role_hint=other`.

## 2.28.9 — 2026-09-13 — Cleaner Domains / Power rails membership

Power rails follow primary domain only. IC satellites for decoupling/bulk/filter/pullup stay on the IC’s primary supply rail (LDO 3V3 no longer inherits VSYS input caps). Connectors/switches drop out of noisy “other” satellites.

- [Fixed] Rails view membership = domain primary rail (not transitive satellite nets).
- [Fixed] `_group_for_ic` primary-rail filter for power-role satellites; skip connector/switch “other”.

## 2.28.8 — 2026-09-13 — Stronger layout_rules extraction skill

Pintable skill now treats PCB / typical-application layout guidance as a first-class extract. Page trim keeps layout keywords; IC cache re-extracts once when `layout_rules` are empty under an older `model_version` (1.10.0+).

- [Changed] `skills/extract-pintable` — dedicated `layout_rules` step, examples, hard negatives; tighter `validate.py`.
- [Changed] Datasheet page trim includes PCB layout / decoupling / typical-application keywords.
- [Changed] Analysis IC extraction refreshes empties when `model_version` < default (1.10.0).
- [Changed] `default_model_version` → `1.10.0`.

## 2.28.7 — 2026-09-13 — Placement F2 pack skeleton (gated)

Placement pipeline can propose satellite xy only when a `.kicad_pcb` layout exists and a `decoupling_proximity` rule has numeric `max_distance_mm`. No millimetres invented; otherwise `placement_pack.json` is skipped with an explicit reason.

- [New] `placement_pack.py` + `placement_pack.json` after F1 plan.
- [New] `GET /api/pipeline/{id}/placement/pack` and Pack section on the placement page.
- [Changed] Placement stepper adds a **Pack satellites** stage.

## 2.28.6 — 2026-09-13 — Split Domains by primary supply rail

Domains no longer merge the whole board when a charger/LDO bridges VBUS→VSYS→3V3. Each IC is clustered by its primary supply rail (output for power ICs, regulated digital rail for consumers).

- [Fixed] `_build_domains` groups by primary rail instead of transitive POWER union-find.
- [Changed] Domain ids use the rail name (e.g. `domain_3V3_DIGITAL`).

## 2.28.5 — 2026-09-13 — Domains & power-rail topology views

Browse routing-first functional groups from the project sidebar: Domains (power-net islands) and Power rails, each highlighting IC groups and satellite roles.

- [New] Sidebar tabs **Domains** and **Power rails** (from `placement_plan` / `functional_groups`).
- [Changed] Analysis `graph_build` also writes `placement_plan.json`.
- [Fixed] Heal stuck Placement `queued`/`running` when the worker is dead.

## 2.28.4 — 2026-09-13 — Unstick zombie running pipelines

A finished run whose worker died before flipping meta stayed `running`, so Progress showed Review spinning forever. Heal those projects when the event log already ends with `pipeline_complete`.

- [Fixed] `heal_if_pipeline_finished` on project get / pipeline status.
- [Fixed] Progress stepper marks all stages complete on `pipeline_complete`.
- [Fixed] Admin sweeper also covers local zombies without `execution_name`.

## 2.28.3 — 2026-09-13 — Stop progress→report bounce on finished projects

Opening a finished project no longer flashes Processing and dumps you on the report. Progress only auto-opens the report after a live run on that visit.

- [Fixed] `/progress` checks project status before SSE; finished projects go to the hub.
- [Fixed] Analysis SSE ignores placement events and does not treat already-terminal status as a crash.

## 2.28.2 — 2026-09-13 — Fix project sidebar navigation

Opening a finished project no longer dumps you on the report with a stuck left menu. Hub first; Report stays in the sidebar. Leaving `/report` for BOM/tabs uses a full navigation so the page actually changes.

- [Fixed] Dashboard project cards/table open `/project/{id}` (not `/report`).
- [Fixed] Sidebar Dashboard / Library / BOM tabs escape nested report/progress/placement routes.

## 2.28.1 — 2026-09-12 — Placement pipeline (parallel)

Dedicated Placement job builds the routing-first topology plan without touching the analysis pipeline status or spending credits. No millimetres — domains, IC groups, satellites only.

- [New] `POST /api/pipeline/{id}/placement/start` (+ cancel, events SSE, get plan).
- [New] Project page **Build placement plan** → `/project/{id}/placement` progress + topology viewer.
- [New] Worker `MODE=placement` writes `placement_plan.json` (and refreshes `functional_groups.json`).

## 2.28.0 — 2026-09-12 — Layout F1 topology + crystal/NC checks

Routing-first floorplan foundation without inventing millimetres: domains and satellite role hints after graph build, plus deterministic crystal CL and NC-pin checks.

- [New] `functional_groups.json` from `graph_build` (domains, IC groups, `role_hint`, attached `layout_rules`).
- [New] `crystal_cl_check` (PS-XTAL-*) and `nc_pin_check` (PE-NC-001) in the deterministic suite.
- [Docs] Piano §0c Placement F1/F2; packing mm stays Layout F2.

## 2.27.1 — 2026-09-12 — DeepSeek roadmap integrations

Close the open P0/P2 items from the growth plan: offline smoke on `simple_project`, reviewer `shortest_path`, library promotion gate, PDF drop logging, per-stage cache hit-rate helper. IC placement stays Layout-product backlog.

- [New] `scripts/smoke_simple_project.py` + `simple_project/smoke_baseline.json`.
- [New] Graph tool `shortest_path`; `library_gate` before shared extracted/.
- [New] `cache_stats_by_stage()`; PDF truncate/omit page logs.
- [Test] `tests/test_roadmap_integrations.py`.

## 2.27.0 — 2026-09-11 — Local multi-user auth

Self-host Periscope accounts (email + password) so several people can share a project. Invite collaborators by email from the project page — same flow as cloud, without Clerk.

- [New] `AUTH_JWT_SECRET` enables register/login; first user is admin and inherits `users/local` projects.
- [New] `/sign-in` and `/sign-up`; sidebar account menu. Set `NEXT_PUBLIC_AUTH_MODE=local` on the frontend build.
- [Changed] Collaborator lookup works for local users; Clerk still used when its keys are set.

## 2.26.5 — 2026-09-11 — Prefer PCB nets for connectivity

When a `.kicad_pcb` is present, pad nets from the board drive the design graph. Schematic geometry alone was inventing swapped rails (GND↔3V3) and floating pins on good KiCad 10 designs.

- [Fixed] KiCad 10 `(net "Name")` pad form.
- [Fixed] Graph build overrides sch nets with board connectivity; `/NET` → `NET`.
- [Test] PCB nets beat a misleading schematic.

## 2.26.4 — 2026-09-11 — KiCad power nets merge

`.kicad_sch` connectivity treated every `GND` power flag as its own island (`GND_`, `GND__`…), so the reviewer invented swapped rails and floating pins on good designs.

- [Fixed] Same-name power symbols and global/local labels merge within a sheet (KiCad semantics).
- [Fixed] Pins sitting mid-wire attach to that net; `mirror x`/`y` handled correctly.
- [Test] Disconnected GND flags, local labels, mid-segment wire.

## 2.26.3 — 2026-09-11 — KiCad project zip upload

One zip (or every `.kicad_sch`) covers hierarchical sheets. If the zip has `bom.csv` and `.kicad_pcb`, those are taken too. Pipeline re-reads companions from storage.

- [New] Zip → sheets + optional BOM/PCB. Nested `Sheetfile` paths kept.
- [Test] Upload → workspace re-parse finds child sheet parts.

## 2.26.2 — 2026-09-11 — Three file boxes

New project: BOM, schematic, and PCB on the first screen. PCB is optional.

- [Changed] No extra wizard step for the board.

## 2.26.1 — 2026-09-11 — Ask for the KiCad board

The create-project wizard has a dedicated PCB step (skip still allowed). Report load errors show the API detail instead of a generic fetch failure.

- [New] Wizard step for `.kicad_pcb`. Upload later from Settings or Impedance.
- [Improved] Report page retries briefly and links back to pipeline progress when `report.json` is missing.
- [New] Drop the KiCad project folder (or a zip). Extra library junk is ignored; the board is picked up if present.

## 2.26.0 — 2026-09-11 — ImpedenceFinder Z0 on PCB nets

A pipeline run with `.kicad_pcb` + stackup samples routed **signal** nets (power/ground skipped). Extra net names can be analyzed from the Impedance tab. Z0 is ImpedenceFinder net_walk/zsolver; no invented εr.

- [New] `impedance_nets.json` after graph build. GET/POST `/api/projects/{id}/impedance/nets`.

## 2.25.0 — 2026-09-10 — Keepout courtyard

`layout_rules` `keepout` flags a foreign net whose track endpoint is inside the KiCad courtyard. Own net and missing courtyard skip. No invented analog/digital classes.

- [New] `PE-PLC-004` WARNING. Tests use `X1` / `/HFXIN` / `GND` from `simple_project`.

## 2.24.0 — 2026-09-10 — Crystal load caps and track path

Load caps on XIN/XOUT use the same `max_distance_mm` as decoupling. If the PCB has segments on the net, the limit is shortest-path length, not a guessed “loop is too big” ratio.

- [New] Crystals (`X1` / C9 / C10 on `simple_project`) run `PE-PLC-001` when `layout_rules` has millimetres.
- [New] Detour tracks: path along segments vs the same `max_distance_mm`. No segments → euclidean pad distance.

## 2.23.0 — 2026-09-10 — same_layer decoupling

If `layout_rules` sets `same_layer: true`, a decoupling cap on the opposite copper from the IC is a WARNING. A via inside the courtyard (calculated) is enough. Unset flag → skip.

- [New] `PE-PLC-003` WARNING when every placed cap on the net is on F vs B opposite the IC.

## 2.22.0 — 2026-09-10 — Thermal vias vs min_via_count

Via count is calculated inside the KiCad courtyard. The limit is the `min_via_count` parameter from `layout_rules`. No courtyard or no count → skip. No pad radius default.

- [New] `PE-PLC-002` when vias in courtyard < `min_via_count`. `simple_project` has no PCB so it stays silent.

## 2.21.0 — 2026-09-10 — Layout SI skew (datasheet mm only)

Intra-pair skew is measured on the PCB only when `layout_rules` `length_match` has a number. 3W, creepage, and CPWG are not guessed.

- [New] `PE-SI-001` ERROR when a named pair (_DP/_DM, _P/_N) exceeds that millimetre. No mm in the datasheet → skip.

## 2.20.0 — 2026-09-10 — Placement vs datasheet (PCB)

Decoupling distance is measured on the `.kicad_pcb` against `layout_rules`. No board → no `PE-PLC-001`. A null millimetre skips — no 3 mm default.

- [New] `PE-PLC-001` when a decoupling cap is farther than datasheet `max_distance_mm`. Empty `layout_rules` and missing caps skip.

## 2.19.0 — 2026-09-10 — Finding review and ECO

Findings can be accepted, marked false-positive, or wontfix with a required reason. Accepted rows export as ECO; OpenEMS-style layout SI is still not this.

- [New] Review state on the report (`open` / `accepted` / `false_positive` / `wontfix`). Empty reason is rejected except when returning to open.
- [New] ECO CSV/JSON of accepted findings only. False-positive and wontfix stay off the ECO.
- [New] Release signature: SHA-256 of findings + user + timestamp. Needs-review filter `?review=open`.

## 2.18.0 — 2026-09-10 — ImpedenceFinder calculator

The Impedance tab uses the closed-form engine from ImpedenceFinder (Hammerstad–Jensen / Cohn), not a second formula set and not OpenEMS.

- [New] Project tab Impedance: microstrip, stripline, coupled-diff Z0, stackup → 50/90/100 Ω widths, download `.kicad_dru` advice.
- [New] Vendored ImpedenceFinder core under `vendor/impedancefinder/` (no gerber2ems, no pcbnew).
- CPWG stays unimplemented — no invented number.

## 2.17.0 — 2026-09-10 — Lifecycle and datasheet extras

Distributor lifecycle is a cached check, not a review scrape. Errata and layout_rules stay structured and skip when the catalog or the PDF has no number.

- [New] `PE-LF-001` EOL, `PE-LF-002` NRND, `PE-LF-003` explicit RoHS fail. Replacement only if the distributor lists it. Active / RoHS N/A / missing cache row are silent.
- [New] `PE-ERRATA-001` when a catalogued workaround pull-up is missing. No URL → skip.
- [New] `PE-INT-001` when `internal_features.pullup_pins` has no rail resistor.
- [New] `layout_rules` closed kinds; non-numeric `max_distance_mm` is stored as null.

## 2.16.0 — 2026-09-10 — KiCad cad-bridge

Periscope writes `periscope-findings.json` next to the report so a KiCad 9/10 action plugin can pan to the symbol uuid on the right sheet.

- [New] E2 cad-bridge JSON (`version`, `ref`, `pins`, `sheet`, `uuid`, `severity`). Layout rule ids target pcbnew; others target eeschema.
- [New] `.kicad_sch` symbols keep `cad_uuid` + `cad_sheet` in `cad_index` (child sheet, not the empty root).
- [New] Action plugin in `plugins/kicad/` reads the JSON beside `.kicad_pro` / `.kicad_pcb`.

## 2.15.0 — 2026-09-10 — Power margin, sequencing, DNP enable

Schema checks now compare regulator load to Iout_max, look at PG→EN when a sequence is declared, and treat DNP as a fitted-variant graph.

- [New] `PE-PWR-001` when specified IQ+I_load exceeds Iout_max, or an explicit series R/ferrite DCR drops >5% of the rail. Missing IQ and PCB traces are not guessed.
- [New] `PE-SEQ-001` WARNING if `power_sequence` is in IC specs and upstream PG does not net to downstream EN.
- [New] BOM `DNP`/`Fitted`/`Variant` on `bom_fields`. Fitted enable with only a DNP pull is `PE-DNP-001` ERROR; no DNP column skips the check.

## 2.14.0 — 2026-09-10 — Filtri e termico schema

Deterministic checks now match RC/LC/π/T filters and estimate LDO/resistor dissipation without inventing missing numbers.

- [New] Filter topology `PE-FLT-001` (fc INFO) / `PE-FLT-002` vs `adc_sample_rate` only when that spec exists. Ferrite DCR `PE-FLT-003` only with a datasheet limit.
- [New] LDO `P = I_load×(Vin−Vout)` and `Tj = 25 + P·θJA`. Missing θJA is `PE-TH-001` INFO. `Iout_max` is not treated as load.
- [New] Resistor `I²R` vs `power_rating_w` on LED paths and shunts with known ΔV (`PE-TH-003`).

## 2.13.0 — 2026-09-10 — DC-bias C_eff stima

The derating table now shows an effective capacitance under DC bias for C0G/X7R/X5R ceramics. It is labelled *stima* — not a vendor lot curve.

- [New] `C_eff` column from an empirical V/Vrated table. Tantalum/electrolytic and unknown dielectrics are left blank.
- [Improved] C0G/NP0 stays at nominal C; X7R at 50% of rated V is about 70% of C.
- [New] Bulk C without a ~100 nF ceramic is `PE-ESR-001` INFO (no invented Z(f) target).

## 2.12.0 — 2026-09-10 — Pull-up sizing and LDO Cout

Deterministic schema checks now size I2C pull-ups, flag NRST pull-downs, and look at LDO VOUT capacitance — still WARNING, never a invented datasheet µF ERROR.

- [New] I2C pull-up value vs a wide NXP UM10204 band (`PE-I2C-002`). 4.7 kΩ is in-band; missing values are not sized.
- [New] Active-low reset with a resistor to ground is `PE-RST-002`.
- [New] Regulator VOUT needs Cout (`PE-DEC-001`); 100 nF-only on VOUT is `PE-DEC-002`. MCU VDD 100 nF is not flagged.
- [Improved] Pin-mux UART0 on the `simple_project` MSPM0 nets is covered in tests (SPI PICO/POCI already was).

## 2.11.0 — 2026-09-10 — DeepSeek V4.1 and re-analyze

Periscope now defaults to DeepSeek-V4.1-Flash (`deepseek-flash`) for every LLM stage, shows API cost in dollars, and lets you replace the BOM and netlist on an existing project without deleting it.

- [New] Default model is `deepseek-flash` (native vision). Legacy `deepseek-v4-flash` / `deepseek-v4-flash-vision-exp` names still work; they route to V4.1.
- [New] Replace BOM & netlist on a finished project and re-run the analysis. History, library cache, and prior spend stay on the same project.
- [Improved] API cost uses V4.1 Flash peak rates and is shown on the report, logs tab, and run estimate (not only credits).

## 2.10.0 — 2026-08-27 — Deeper datasheet review

Each IC review now sees more of the datasheet and starts from a structured abs-max table, so voltage, decoupling, and interface checks are less likely to stop at "Unverified".

- [Improved] Extraction pulls Absolute Maximum Ratings (supplies, pin voltages, current, temperature) alongside the pin table, and the reviewer gets those numbers in context.
- [Improved] DeepSeek ingest uses PyMuPDF text (tables survive better than pypdf) and, on vision models, renders pin / abs-max / electrical / application pages instead of always the first 24.
- [Improved] Review checklist now includes recommended operating conditions, VIH/VIL, crystal load caps, and datasheet-named external parts. Turn budget 16, more excerpt pages, three follow-ups per concern.

## 2.9.0 — 2026-08-27 — Component library

Chips and passives stay in a shared library after the first look, so the next board does not re-download datasheets or re-extract pin tables.

- [New] Library page in the sidebar: ICs (pin tables), passive series, discrete specs, and saved PDFs.
- [New] Datasheets are written to the library as soon as they are fetched or uploaded, not only after a full review.
- [Improved] The create-project wizard already skipped parts that were extracted once; that reuse now covers the PDF itself as well.

## 2.8.0 — 2026-08-27 — Automatic datasheets

Periscope now finds datasheet PDFs on its own. You can still upload a file, but you no longer need DigiKey keys for the common case.

- [New] Auto-fetch from LCSC (no API key) by manufacturer part number or LCSC code, with exact-MPN matching so a CH340E never silently becomes a CH340G.
- [New] Direct Texas Instruments datasheet URLs (`ti.com/lit/ds/symlink/…`) as a second source for TI parts.
- [New] Pipeline fallback: if a datasheet was not uploaded in the wizard, extraction and review try the same lookup before skipping the IC.
- [Improved] DigiKey remains an optional third source when `DIGIKEY_CLIENT_ID` / `DIGIKEY_CLIENT_SECRET` are set.

## 2.7.0 — 2026-08-27 — DeepSeek API

Periscope now talks to DeepSeek by default. Extraction skills run locally; datasheet PDFs are converted to text (and page images on the vision model) because DeepSeek does not accept native PDF documents.

- [New] DeepSeek provider (`deepseek-v4-flash`, `deepseek-v4-pro`, `deepseek-v4-flash-vision-exp`) via the OpenAI-compatible Chat Completions API.
- [New] Local skill runner: `skills/*/SKILL.md` is inlined and `validate.py` runs in-process — no Anthropic Console upload required.
- [New] PDF ingest for DeepSeek: pypdf text extraction plus optional PyMuPDF page renders on vision models.
- [Improved] Anthropic and Gemini remain optional fallbacks via `PROVIDER_*` / `FALLBACK_PROVIDER_*`.

## 2.6.0 — 2026-07-12 — Export Report to Excel

Download a project's findings as an Excel spreadsheet straight from the report — one click, ready to share, filter, or archive outside Periscope.

- [New] "Export Excel" button on the validation report. Every finding becomes a spreadsheet row — designator, part number, ID, severity, title, description, recommendation, and its datasheet source (page included) — sorted most-severe first.

## 2.5.1 — 2026-07-04 — More Thorough Reviews

Schematic review now works through every functional area of a component before finishing, so a part with several independent issues has all of them surfaced in one pass instead of just the first.

- [Improved] For each IC, the review covers power and decoupling, every signal interface, absolute-maximum ratings, and reset/boot/configuration and unused pins before reporting — catching multiple issues on the same component that could previously be missed.

## 2.5.0 — 2026-07-02 — Light Mode

Periscope now has a light theme. Toggle between light and dark with the sun/moon button — in the sidebar next to your account menu, or in the header on the website.

- [New] Theme toggle. Switch between light and dark mode anywhere in the app; your choice is remembered on this device. Everything defaults to dark, exactly as before, until you flip it.
- [Improved] Every status color — error, warning, and pass badges, finding cards, the progress view, billing — is tuned for both themes, so reports stay legible either way.
- [Improved] The sign-in page and account menu now follow the app theme instead of always rendering light.

## 2.4.0 — 2026-07-01 — Automatic Pin & LED Current Checks

Two datasheet-grounded checks now run on every project, independent of the schematic review — catching a swapped-peripheral pin or an over-driven LED — plus a clear list of any components that had no datasheet to review against.

- [New] Pin-function feasibility check. Periscope now flags when a net assigns an IC pin a peripheral function its silicon can't route — for example a `UART5_TX` net on a pin whose alternate-function table only offers `UART5_RX`. It's reported as an error straight from the datasheet's pin table and names the likely swap (TX↔RX, SDA↔SCL). It deliberately does not judge signal *direction* across an interface — a direct UART crosses TX↔RX while a transceiver runs straight through — so it only fires on physically impossible pin assignments, never on wiring style.
- [New] LED forward-current check. For each LED, Periscope computes the forward current from the supply rail, the series resistor, and the LED's rated forward voltage, and flags any channel whose current exceeds the LED's rated maximum. Each color of an RGB LED is checked separately, and a leg with no current-limiting resistor at all is called out as a caution.
- [New] "Not reviewed" list on the report. Components with no datasheet on file — for instance a do-not-populate footprint that isn't in the BOM — are now called out explicitly, so a mis-wired pin on an unreviewed part shows up as a known gap instead of being silently absent.
- [New] Findings from these automatic checks carry an "Automated check" badge, so they're easy to tell apart from datasheet-review findings.

## 2.3.3 — 2026-06-08 — Faster Reviews

Multi-chip designs now review several times faster — Periscope works through ICs in parallel instead of one at a time.

- [Improved] Datasheet extraction and schematic review now process multiple ICs at once, so reports on multi-IC projects come back substantially faster. The findings are unchanged — only the wait is shorter.

## 2.3.2 — 2026-05-26 — Smarter RF Topology Review

Schematic review now reasons about *what each external part is for* before flagging it — catching valid bias, coupling, and matching circuits that previously looked like errors.

- [Improved] The reviewer states the role of every external part on an IC pin (choke, blocking cap, divider, decoupling, matching) before judging the connection. Common RF topologies like bias-T (DC injected onto a coax through a choke, with the chip protected by an internal DC block and a downstream load doing the actual draw) are no longer flagged as errors against the chip.
- [Improved] Stricter absolute-maximum-rating checks: the cited limit must come from the same pin under stress (a Vdd abs-max no longer counts against an RF or signal pin), and the inequality must be a strict exceed — equal-to-abs-max is at most a Warning.
- [Improved] Single-concern deep dives are capped at two follow-up queries; concerns that can't be resolved in that budget are reported as Warnings with the unresolved question stated, so one suspect finding can't starve the rest of the IC review.
- [Improved] Inferred rail voltages from the power-tree pass are no longer treated as ground truth by the schematic reviewer. Voltages set by net name (`+5V`, `+3V3`) or by user power-source hints are trusted as before; voltages the power-tree LLM guessed for an adjustable regulator output or propagated through inference are kept on the power-tree view for reference but excluded from review reasoning, so a single misread rail can't anchor a false-positive Error.
- [Improved] After each IC's review, a second pass normalizes findings against a fixed Error/Warning/Info rubric and merges any two findings that share a single root cause (e.g. "series resistor drops VIN" and "VOUT setpoint exceeds available VIN" are one defect, not two). Cuts run-to-run severity drift and avoids inflating the error count when one defect can be described from multiple angles.

## 2.3.1 — 2026-05-25 — EDIF Netlist Support

EDIF 2.0.0 netlists upload alongside PADS-PCB, with a sub-design picker for files that contain more than one design. Schematic review is also more cautious about polarity / direction-control findings.

- [New] Upload EDIF 2.0.0 (`.edn`) netlists directly. Format is auto-detected from the file contents — no need to convert to PADS-PCB first. Verified against Siemens xDX Designer exports.
- [New] When an EDIF file contains multiple sub-designs, project setup shows a picker so you can choose which one to review. The picker auto-confirms when there's a single clean match against your BOM and only asks when it's ambiguous; unselected sub-designs are filtered out of the design graph.
- [Improved] Stronger verification of differential and polarity pin assignments (USB D+/D−, TX/RX, IN+/IN−, anode/cathode) directly against the datasheet.
- [Improved] Improved support for bidirectional buffers and level translators (74xx245 and friends) — direction-control truth tables are factored into bus-contention analysis.
- [Improved] Findings that share a single root cause on the same chip are grouped into one combined finding.

## 2.3.0 — 2026-05-24 — LCSC Part Number Support

JLCPCB-style BOMs with LCSC part numbers (e.g. `C12044`) now work out of the box — Periscope auto-detects the column, resolves each id to the real manufacturer part number, and shows you what it resolved to before the pipeline runs.

- [New] LCSC part numbers in the manufacturer part number column are auto-detected at BOM upload and converted to real MPNs. Works with JLCPCB / EasyEDA exports without any column renaming.
- [New] Project setup now shows the LCSC → MPN mapping on each IC row in the datasheet step (e.g. `C12044 → TP4057-42-SOT26-R`), so you can see what each LCSC id became before the pipeline starts.
- [New] Passive specs (value, voltage, tolerance, dielectric, package) are resolved from the LCSC catalog during project setup, with per-row progress and status — you see what's resolved before spending credits on the full pipeline.
- [Improved] Datasheet auto-fetch hit rate is dramatically higher on LCSC BOMs, because DigiKey now sees real MPNs instead of `C…` ids.

## 2.2.1 — 2026-05-22 — Easier Netlist Uploads & Xpedition Support

Tabbed file upload guide with per-tool instructions, Xpedition coverage, and direct `.net` / `.txt` uploads.

- [New] Documentation for exporting a PADS-PCB netlist from Siemens Xpedition Designer / DxDesigner (VX.2.x, including VX.2.14).
- [Improved] File upload guide reorganized into tabs — KiCad, Altium, OrCAD/Allegro, Xpedition, EasyEDA, and Eagle each get their own panel.
- [Improved] Netlist uploads now accept `.asc`, `.net`, `.NET`, and `.txt` directly — no more renaming required before upload.
- [Improved] File guide now calls out the difference between the PADS-PCB schematic netlist Periscope needs and the `!PADS-POWERPCB` PCB-layout dump that some EDA tools also save as `.asc`.

## 2.2.0 — 2026-05-20 — Cross-chip Datasheet Review

The reviewer now reads neighbor-chip datasheets to verify cross-chip constraints, with fewer false errors when a spec can't be confirmed.

- [Improved] Schematic review now cross-references connected chips: when an issue depends on a neighbor's spec (5V tolerance, absolute-max, drive strength), the reviewer pulls the relevant pages from that chip's datasheet before flagging it.
- [Improved] Fewer false errors on cross-chip findings: if a counterpart spec can't be confirmed from the datasheet, the issue is reported as a Warning with the unverified assumption stated — instead of being overstated as an Error.
- [Fixed] Some review findings could occasionally fail to appear in the report.

## 2.1.0 — 2026-05-19 — Datasheet Reference Highlighting

Datasheet citations now highlight the exact supporting sentence on the PDF page, with more reliable page numbers on large datasheets.

- [Improved] Datasheet references now highlight the exact supporting sentence on the PDF page, not just the page number.
- [Fixed] Datasheet citations landing on the wrong page for large (multi-hundred-page) datasheets.
- [Fixed] Reviewed findings losing their checked state on page refresh.

## 2.0.1 — 2026-05-01 — Flagging & Onboarding

One-click flags on finding cards, an onboarding survey for new users, and small UI polish.

- [New] Report findings with one click via the flag button on any finding card.
- [New] Onboarding survey for new users to help us improve the product.
- [Improved] Comment input box now fills available width.

## 2.0.0 — 2026-04-29 — Public Changelog

- [New] Initial public changelog.