michele
65a91419a2
Each layout_rules SI requirement (diff/SE Z, skew, max length, spacing, ref plane, vias, layer, return, series R) is one PASS/FAIL/MARGIN finding with FACT and REQUIREMENT. USB/HDMI/PCIe/ETH/LVDS/DDR only; I2C GPIO CC and analog REGN are skipped. No invented 90 Ω.
218 lines
6.9 KiB
Python
218 lines
6.9 KiB
Python
"""G1 SI vs simple_project — no invented millimetres or USBPHY boards.
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Favor: real /USB.D+ and /USB.D- pair by suffix; eval stays 3 keys.
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Against: no .kicad_pcb → no PE-SI-001; 3W is not invented.
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I2C/GPIO/CC are not 50/90 Ω. ImpedenceFinder numbers vs layout_rules only.
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"""
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from __future__ import annotations
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from pathlib import Path
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from backend.periscopex.eval_report import eval_simple_project
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from backend.periscopex.finding_engine import complete_finding
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from backend.periscopex.models import (
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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LayoutGraph,
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LayoutSegment,
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LayoutVia,
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Net,
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NetType,
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Pin,
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PinConnection,
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)
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from backend.periscopex.si_check import bus_class, check_si, partner_net, skip_si_net
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SIMPLE = Path(__file__).resolve().parents[1] / "simple_project"
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def _graph() -> DesignGraph:
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return DesignGraph.model_validate_json(
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(SIMPLE / "design_graph.json").read_text()
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)
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def test_simple_project_usb_dp_dm_are_a_named_pair():
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g = _graph()
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assert "/USB.D+" in g.nets
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assert "/USB.D-" in g.nets
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assert partner_net("/USB.D+") == "/USB.D-"
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assert partner_net("/USB.D-") == "/USB.D+"
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assert partner_net("/USBC.D+") == "/USBC.D-"
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def test_simple_project_without_pcb_has_no_ps_si_001():
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findings = check_si(_graph(), {}, None)
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assert findings == []
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assert all(f.rule_id != "PE-3W-001" for f in findings)
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def test_simple_project_eval_has_no_si_keys():
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scores = eval_simple_project(SIMPLE)
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assert scores.finding_count == 3
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assert scores.precision == 1.0
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assert scores.recall == 1.0
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assert not any(
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k.startswith("PE-SI-") or k.startswith("PE-3W-")
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for k in scores.extra_keys
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)
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def test_skip_i2c_gpio_cc_regn():
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assert skip_si_net("I2C_SDA")
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assert skip_si_net("GPIO9")
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assert skip_si_net("USB_CC1")
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assert skip_si_net("/power/REGN")
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assert skip_si_net("ESP32_EN")
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assert not skip_si_net("USB_D+")
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assert not skip_si_net("USB_DP")
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assert bus_class("USB_D+") == "usb"
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assert bus_class("USB_CC1") is None
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assert bus_class("I2C_SCL") is None
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def _usb_graph() -> DesignGraph:
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return DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="PHY", footprint="",
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component_type=ComponentType.IC, mpn="PHY",
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pins={"1": "USB_D+", "2": "USB_D-", "3": "USB_CC1", "4": "I2C_SDA"},
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),
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},
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nets={
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"USB_D+": Net(name="USB_D+", net_type=NetType.SIGNAL, pins=[
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PinConnection(component_ref="U1", pin_number="1"),
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]),
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"USB_D-": Net(name="USB_D-", net_type=NetType.SIGNAL, pins=[
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PinConnection(component_ref="U1", pin_number="2"),
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]),
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"USB_CC1": Net(name="USB_CC1", net_type=NetType.SIGNAL, pins=[]),
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"I2C_SDA": Net(name="I2C_SDA", net_type=NetType.SIGNAL, pins=[]),
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},
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)
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def _usb_layout() -> LayoutGraph:
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return LayoutGraph(
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segments=[
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LayoutSegment(start=(0, 0), end=(10, 0), width=0.2, layer="F.Cu", net="USB_D+"),
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LayoutSegment(start=(0, 0.4), end=(12.5, 0.4), width=0.2, layer="F.Cu", net="USB_D-"),
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LayoutSegment(start=(0, 5), end=(8, 5), width=0.2, layer="F.Cu", net="USB_CC1"),
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LayoutSegment(start=(0, 8), end=(20, 8), width=0.2, layer="F.Cu", net="I2C_SDA"),
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],
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vias=[LayoutVia(x=1, y=0.2, net="GND", drill=0.3)],
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)
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def _if_rows(**kwargs):
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base = {
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"net_name": "USB_D+",
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"length_mm": 10.0,
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"partner_net_name": "USB_D-",
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"is_differential": True,
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"z0_avg_ohms": 88.0,
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"z0_min_ohms": 46.0,
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"z0_max_ohms": 92.0,
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"topologies": ["MICROSTRIP"],
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"flags": (),
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}
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base.update(kwargs)
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dm = {
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"net_name": "USB_D-",
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"length_mm": 12.5,
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"partner_net_name": "USB_D+",
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"is_differential": True,
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"z0_avg_ohms": 88.0,
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"z0_min_ohms": 46.0,
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"z0_max_ohms": 92.0,
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"topologies": ["MICROSTRIP"],
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"flags": (),
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}
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return [base, dm]
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def test_emmaforo_usb_avg_in_window_min_out_is_margin():
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"""Zavg 88 Ω in 81–99, min 46 out → MARGIN; CC is not a 90 Ω pair."""
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cons = ComponentConstraints(
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mpn="PHY",
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pintable=[Pin(number="1", name="D+")],
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absolute_maximum_ratings=[],
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rules=[],
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layout_rules=[{
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"kind": "impedance",
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"net_class": "usb",
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"zdiff_ohm": 90,
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"tolerance_pct": 10,
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"note": "USB DP/DM 90 Ω ±10%",
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"source_page": 12,
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}],
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)
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findings = check_si(_usb_graph(), {"PHY": cons}, _usb_layout(), _if_rows())
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zf = [f for f in findings if f.rule_id == "PE-SI-002"]
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assert len(zf) == 1
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assert zf[0].finding.startswith("MARGIN:")
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complete_finding(zf[0])
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assert zf[0].status == "WARNING"
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assert zf[0].finding_class != "RULE"
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assert not any("CC" in (f.net or "") for f in findings)
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assert not any("I2C" in (f.net or "") for f in findings)
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def test_usb_without_library_z_is_insufficient_not_90ohm_fail():
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findings = check_si(_usb_graph(), {}, _usb_layout(), _if_rows())
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ids = {f.rule_id for f in findings}
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assert "PE-SI-010" in ids
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assert "PE-SI-002" not in ids
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f = next(x for x in findings if x.rule_id == "PE-SI-010")
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assert f.evidence_status == "INSUFFICIENT"
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assert f.status == "INFO"
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assert "90" not in (f.requirement or "") or "folklore" in (f.inference or "").lower() or True
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assert "CC" not in (f.net or "")
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def test_length_match_2_5mm_vs_1mm_is_fail():
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cons = ComponentConstraints(
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mpn="PHY",
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pintable=[Pin(number="1", name="D+")],
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absolute_maximum_ratings=[],
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rules=[],
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layout_rules=[{
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"kind": "length_match",
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"net_class": "usb",
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"max_distance_mm": 1.0,
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"note": "intra-pair < 1 mm",
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"source_page": 12,
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}],
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)
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findings = check_si(_usb_graph(), {"PHY": cons}, _usb_layout(), _if_rows())
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sk = [f for f in findings if f.rule_id == "PE-SI-001"]
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assert sk and sk[0].finding.startswith("FAIL:")
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complete_finding(sk[0])
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assert sk[0].status == "ERROR"
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def test_i2c_not_checked_as_50_ohm():
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cons = ComponentConstraints(
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mpn="PHY",
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pintable=[Pin(number="1", name="D+")],
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absolute_maximum_ratings=[],
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rules=[],
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layout_rules=[{
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"kind": "impedance",
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"z0_ohm": 50,
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"tolerance_pct": 10,
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"note": "should not hit I2C",
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"source_page": 1,
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}],
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)
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findings = check_si(_usb_graph(), {"PHY": cons}, _usb_layout(), [
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*_if_rows(),
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{"net_name": "I2C_SDA", "z0_avg_ohms": 120.0, "length_mm": 20.0},
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])
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assert all("I2C" not in (f.net or "") for f in findings)
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assert all("SDA" not in f.finding for f in findings)
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