michele
69d5dd9313
Phase A: stub, return-split, and BOM termination on buses present on the graph; DDR/CPU/FPGA class certifiers only when that device exists. Skip without evidence. Via, pad, track, and zone stay distinct. Not DRC or FEM.
429 lines
15 KiB
Python
429 lines
15 KiB
Python
"""G1 SI vs simple_project — no invented millimetres or USBPHY boards.
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Favor: real /USB.D+ and /USB.D- pair by suffix; eval has no PE-SI keys.
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Against: no .kicad_pcb → no PE-SI-001; 3W is not invented.
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I2C/GPIO/CC are not 50/90 Ω. ImpedenceFinder numbers vs layout_rules only.
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"""
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from __future__ import annotations
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from tests.paths import SIMPLE_PROJECT, TAXONOMY
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from pathlib import Path
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from backend.periscopex.eval_report import eval_simple_project
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from backend.periscopex.finding_engine import complete_finding
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from backend.periscopex.models import (
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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LayoutGraph,
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LayoutSegment,
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LayoutVia,
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Net,
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NetType,
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Pin,
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PinConnection,
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)
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from backend.periscopex.si_check import bus_class, check_si, partner_net, skip_si_net
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SIMPLE = SIMPLE_PROJECT
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def _graph() -> DesignGraph:
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return DesignGraph.model_validate_json(
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(SIMPLE / "design_graph.json").read_text()
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)
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def test_simple_project_usb_dp_dm_are_a_named_pair():
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g = _graph()
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assert "/USB.D+" in g.nets
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assert "/USB.D-" in g.nets
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assert partner_net("/USB.D+") == "/USB.D-"
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assert partner_net("/USB.D-") == "/USB.D+"
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assert partner_net("/USBC.D+") == "/USBC.D-"
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def test_simple_project_without_pcb_has_no_ps_si_001():
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findings = check_si(_graph(), {}, None)
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assert findings == []
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assert all(f.rule_id != "PE-3W-001" for f in findings)
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def test_simple_project_eval_has_no_si_keys():
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scores = eval_simple_project(SIMPLE)
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assert scores.finding_count == 8
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assert scores.precision == 1.0
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assert scores.recall == 1.0
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assert not any(
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k.startswith("PE-SI-") or k.startswith("PE-3W-")
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for k in scores.extra_keys
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)
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def test_skip_i2c_gpio_cc_regn():
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assert skip_si_net("I2C_SDA")
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assert skip_si_net("GPIO9")
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assert skip_si_net("USB_CC1")
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assert skip_si_net("/power/REGN")
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assert skip_si_net("ESP32_EN")
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assert not skip_si_net("USB_D+")
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assert not skip_si_net("USB_DP")
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assert bus_class("USB_D+") == "usb2"
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assert bus_class("USB_SSTX_P") == "usb3"
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assert bus_class("ETH_TX+") == "eth_mdi"
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assert bus_class("RGMII_TXD0") == "rgmii"
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assert bus_class("SGMII_TX_P") == "sgmii"
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assert bus_class("DDR3_DQ0") == "ddr3_dq"
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assert bus_class("DDR3_DQS0_P") == "ddr3_dqs"
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assert bus_class("MIPI_D0_P") == "mipi"
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assert bus_class("GTX_CLK") == "hf_clk"
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assert bus_class("XTAL_IN") is None
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assert bus_class("USB_CC1") is None
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assert bus_class("I2C_SCL") is None
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def _usb_graph() -> DesignGraph:
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return DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="PHY", footprint="",
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component_type=ComponentType.IC, mpn="PHY",
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pins={"1": "USB_D+", "2": "USB_D-", "3": "USB_CC1", "4": "I2C_SDA"},
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),
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},
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nets={
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"USB_D+": Net(name="USB_D+", net_type=NetType.SIGNAL, pins=[
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PinConnection(component_ref="U1", pin_number="1"),
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]),
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"USB_D-": Net(name="USB_D-", net_type=NetType.SIGNAL, pins=[
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PinConnection(component_ref="U1", pin_number="2"),
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]),
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"USB_CC1": Net(name="USB_CC1", net_type=NetType.SIGNAL, pins=[]),
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"I2C_SDA": Net(name="I2C_SDA", net_type=NetType.SIGNAL, pins=[]),
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},
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)
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def _usb_layout() -> LayoutGraph:
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return LayoutGraph(
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segments=[
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LayoutSegment(start=(0, 0), end=(10, 0), width=0.2, layer="F.Cu", net="USB_D+"),
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LayoutSegment(start=(0, 0.4), end=(12.5, 0.4), width=0.2, layer="F.Cu", net="USB_D-"),
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LayoutSegment(start=(0, 5), end=(8, 5), width=0.2, layer="F.Cu", net="USB_CC1"),
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LayoutSegment(start=(0, 8), end=(20, 8), width=0.2, layer="F.Cu", net="I2C_SDA"),
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],
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vias=[LayoutVia(x=1, y=0.2, net="GND", drill=0.3)],
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)
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def _if_rows(**kwargs):
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base = {
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"net_name": "USB_D+",
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"length_mm": 10.0,
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"partner_net_name": "USB_D-",
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"is_differential": True,
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"z0_avg_ohms": 88.0,
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"z0_min_ohms": 46.0,
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"z0_max_ohms": 92.0,
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"topologies": ["MICROSTRIP"],
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"flags": (),
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}
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base.update(kwargs)
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dm = {
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"net_name": "USB_D-",
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"length_mm": 12.5,
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"partner_net_name": "USB_D+",
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"is_differential": True,
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"z0_avg_ohms": 88.0,
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"z0_min_ohms": 46.0,
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"z0_max_ohms": 92.0,
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"topologies": ["MICROSTRIP"],
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"flags": (),
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}
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return [base, dm]
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def test_emmaforo_usb_avg_in_window_min_out_is_margin():
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"""Zavg 88 Ω in 81–99, min 46 out → MARGIN; CC is not a 90 Ω pair."""
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cons = ComponentConstraints(
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mpn="PHY",
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pintable=[Pin(number="1", name="D+")],
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absolute_maximum_ratings=[],
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rules=[],
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layout_rules=[{
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"kind": "impedance",
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"net_class": "usb",
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"zdiff_ohm": 90,
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"tolerance_pct": 10,
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"note": "USB DP/DM 90 Ω ±10%",
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"source_page": 12,
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}],
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)
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findings = check_si(_usb_graph(), {"PHY": cons}, _usb_layout(), _if_rows())
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zf = [f for f in findings if f.rule_id == "PE-SI-002"]
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assert len(zf) == 1
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assert zf[0].finding.startswith("MARGIN:")
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complete_finding(zf[0])
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assert zf[0].status == "WARNING"
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assert zf[0].finding_class != "RULE"
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assert not any("CC" in (f.net or "") for f in findings)
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assert not any("I2C" in (f.net or "") for f in findings)
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def test_usb_without_library_z_is_insufficient_not_90ohm_fail():
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findings = check_si(_usb_graph(), {}, _usb_layout(), _if_rows())
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ids = {f.rule_id for f in findings}
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assert "PE-SI-010" in ids
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assert "PE-SI-002" not in ids
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f = next(x for x in findings if x.rule_id == "PE-SI-010")
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assert f.evidence_status == "INSUFFICIENT"
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assert f.status == "INFO"
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assert "90" not in (f.requirement or "")
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blob = f"{f.finding} {f.requirement} {f.inference}"
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assert "FAIL" not in f.finding
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assert "90 Ω" not in blob or "folklore" in (f.inference or "").lower()
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assert "CC" not in (f.net or "")
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def test_length_match_2_5mm_vs_1mm_is_fail():
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cons = ComponentConstraints(
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mpn="PHY",
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pintable=[Pin(number="1", name="D+")],
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absolute_maximum_ratings=[],
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rules=[],
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layout_rules=[{
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"kind": "length_match",
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"net_class": "usb",
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"max_distance_mm": 1.0,
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"note": "intra-pair < 1 mm",
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"source_page": 12,
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}],
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)
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findings = check_si(_usb_graph(), {"PHY": cons}, _usb_layout(), _if_rows())
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sk = [f for f in findings if f.rule_id == "PE-SI-001"]
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assert sk and sk[0].finding.startswith("FAIL:")
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complete_finding(sk[0])
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assert sk[0].status == "ERROR"
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def test_i2c_not_checked_as_50_ohm():
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cons = ComponentConstraints(
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mpn="PHY",
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pintable=[Pin(number="1", name="D+")],
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absolute_maximum_ratings=[],
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rules=[],
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layout_rules=[{
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"kind": "impedance",
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"z0_ohm": 50,
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"tolerance_pct": 10,
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"note": "should not hit I2C",
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"source_page": 1,
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}],
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)
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findings = check_si(_usb_graph(), {"PHY": cons}, _usb_layout(), [
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*_if_rows(),
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{"net_name": "I2C_SDA", "z0_avg_ohms": 120.0, "length_mm": 20.0},
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])
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assert all("I2C" not in (f.net or "") for f in findings)
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assert all("SDA" not in f.finding for f in findings)
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def test_en_rc_series_resistor_does_not_paint_usb():
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"""PE-SI-009 must not use ESP32 EN RC 10 kΩ / 1 µF as a USB series R."""
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cons = ComponentConstraints(
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mpn="ESP32",
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pintable=[Pin(number="1", name="D+"), Pin(number="3", name="EN")],
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absolute_maximum_ratings=[],
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rules=[],
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layout_rules=[{
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"kind": "series_resistor",
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"pin": "EN",
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"value_ohms": 10000,
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"note": "EN RC 10 kΩ / 1 µF",
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"source_page": 28,
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}],
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)
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findings = check_si(_usb_graph(), {"PHY": cons}, _usb_layout(), _if_rows())
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si009 = [f for f in findings if f.rule_id == "PE-SI-009"]
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assert si009 == []
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zfail = [f for f in findings if f.rule_id == "PE-SI-002"]
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assert zfail == []
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si010 = [f for f in findings if f.rule_id == "PE-SI-010"]
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assert si010
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assert si010[0].evidence_status == "INSUFFICIENT"
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assert "88" in (si010[0].finding or "")
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assert "90" not in (si010[0].requirement or "")
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def _phy_graph() -> DesignGraph:
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pins = {
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"1": "ETH_TX+", "2": "ETH_TX-",
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"3": "RGMII_TXD0", "4": "RGMII_TXD1",
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"5": "USB_SSTX_P", "6": "USB_SSTX_N",
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"7": "DDR3_DQ0", "8": "DDR3_DQ1",
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"9": "DDR3_DQS0_P", "10": "DDR3_DQS0_N",
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"11": "USB_D+", "12": "USB_D-",
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}
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nets = {
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n: Net(name=n, net_type=NetType.SIGNAL, pins=[
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PinConnection(component_ref="U1", pin_number=p),
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])
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for p, n in pins.items()
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}
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return DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="PHY", footprint="",
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component_type=ComponentType.IC, mpn="PHY",
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pins=pins,
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),
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},
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nets=nets,
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)
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def _phy_layout() -> LayoutGraph:
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segs = [
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LayoutSegment(start=(0, 0), end=(10, 0), width=0.2, layer="F.Cu", net="ETH_TX+"),
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LayoutSegment(start=(0, 0.4), end=(10.2, 0.4), width=0.2, layer="F.Cu", net="ETH_TX-"),
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LayoutSegment(start=(0, 2), end=(8, 2), width=0.15, layer="F.Cu", net="RGMII_TXD0"),
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LayoutSegment(start=(0, 2.4), end=(8.4, 2.4), width=0.15, layer="F.Cu", net="RGMII_TXD1"),
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LayoutSegment(start=(0, 4), end=(20, 4), width=0.12, layer="F.Cu", net="USB_SSTX_P"),
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LayoutSegment(start=(0, 4.3), end=(20.5, 4.3), width=0.12, layer="F.Cu", net="USB_SSTX_N"),
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LayoutSegment(start=(0, 6), end=(15, 6), width=0.1, layer="F.Cu", net="DDR3_DQ0"),
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LayoutSegment(start=(0, 6.2), end=(15.1, 6.2), width=0.1, layer="F.Cu", net="DDR3_DQ1"),
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LayoutSegment(start=(0, 7), end=(12, 7), width=0.1, layer="F.Cu", net="DDR3_DQS0_P"),
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LayoutSegment(start=(0, 7.2), end=(12.3, 7.2), width=0.1, layer="F.Cu", net="DDR3_DQS0_N"),
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LayoutSegment(start=(0, 9), end=(10, 9), width=0.2, layer="F.Cu", net="USB_D+"),
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LayoutSegment(start=(0, 9.4), end=(12.5, 9.4), width=0.2, layer="F.Cu", net="USB_D-"),
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]
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return LayoutGraph(segments=segs, vias=[LayoutVia(x=1, y=0.2, net="GND", drill=0.3)])
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def _z(name, partner, avg, length, **kw):
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row = {
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"net_name": name,
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"partner_net_name": partner,
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"is_differential": True,
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"z0_avg_ohms": avg,
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"z0_min_ohms": avg - 2,
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"z0_max_ohms": avg + 2,
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"length_mm": length,
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"topologies": ["MICROSTRIP"],
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"flags": (),
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}
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row.update(kw)
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return row
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def test_coverage_mdi_rgmii_ddr3_usb3_gated_not_cross_mapped():
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cons = ComponentConstraints(
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mpn="PHY",
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pintable=[Pin(number="1", name="TX+")],
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absolute_maximum_ratings=[],
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rules=[],
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layout_rules=[
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{
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"kind": "impedance",
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"net_class": "eth_mdi",
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"zdiff_ohm": 100,
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"tolerance_pct": 10,
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"note": "MDI 100 Ω to RJ45",
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"source_page": 40,
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},
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{
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"kind": "max_length",
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"net_class": "rgmii",
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"max_distance_mm": 20,
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"note": "RGMII MAC–PHY trace < 20 mm",
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"source_page": 41,
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},
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{
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"kind": "length_match",
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"net_class": "ddr3",
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"max_distance_mm": 1.0,
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"note": "DDR3 DQS intra-pair",
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"source_page": 42,
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},
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{
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"kind": "impedance",
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"net_class": "usb3",
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"zdiff_ohm": 90,
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"tolerance_pct": 10,
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"note": "USB-C SuperSpeed 90 Ω",
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"source_page": 43,
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},
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{
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"kind": "series_resistor",
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"net_class": "rgmii",
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"value_ohms": 22,
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"note": "RGMII series 22 Ω",
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"source_page": 41,
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},
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],
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)
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rows = [
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_z("ETH_TX+", "ETH_TX-", 95.0, 10.0),
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_z("ETH_TX-", "ETH_TX+", 95.0, 10.2),
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_z("USB_SSTX_P", "USB_SSTX_N", 88.0, 20.0),
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_z("USB_SSTX_N", "USB_SSTX_P", 88.0, 20.5),
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_z("DDR3_DQS0_P", "DDR3_DQS0_N", 50.0, 12.0),
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_z("DDR3_DQS0_N", "DDR3_DQS0_P", 50.0, 12.3),
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_z("USB_D+", "USB_D-", 88.0, 10.0),
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_z("USB_D-", "USB_D+", 88.0, 12.5),
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{"net_name": "RGMII_TXD0", "z0_avg_ohms": 48.0, "length_mm": 8.0, "topologies": ["MICROSTRIP"]},
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{"net_name": "RGMII_TXD1", "z0_avg_ohms": 48.0, "length_mm": 8.4, "topologies": ["MICROSTRIP"]},
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{"net_name": "DDR3_DQ0", "z0_avg_ohms": 50.0, "length_mm": 15.0, "topologies": ["MICROSTRIP"]},
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]
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findings = check_si(_phy_graph(), {"PHY": cons}, _phy_layout(), rows)
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by = {}
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for f in findings:
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by.setdefault(f.rule_id, []).append(f)
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mdi_z = [f for f in by.get("PE-SI-002", []) if f.net and "ETH" in f.net]
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assert mdi_z and mdi_z[0].finding.startswith("PASS:")
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usb3_z = [f for f in by.get("PE-SI-002", []) if f.net and "SSTX" in f.net]
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assert usb3_z and usb3_z[0].finding.startswith("PASS:")
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usb2_z = [f for f in by.get("PE-SI-002", []) if f.net and "USB_D" in (f.net or "")]
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assert usb2_z == []
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rgmii_len = [f for f in by.get("PE-SI-003", []) if f.net and "RGMII" in f.net]
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assert rgmii_len and rgmii_len[0].finding.startswith("PASS:")
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assert not any(f.net and "ETH_TX" in f.net for f in by.get("PE-SI-003", []))
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dqs = [f for f in by.get("PE-SI-001", []) if f.net and "DQS" in f.net]
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assert dqs and dqs[0].finding.startswith("PASS:")
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si009 = by.get("PE-SI-009", [])
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assert si009
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assert all(f.net and "RGMII" in f.net for f in si009)
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assert not any(f.net and "USB" in f.net for f in si009)
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si010 = by.get("PE-SI-010", [])
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nets010 = {f.net for f in si010}
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assert any(n and "USB_D" in n for n in nets010)
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assert not any(n and "ETH_TX" in n for n in nets010)
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assert not any(n and "SSTX" in n for n in nets010)
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def test_empty_net_class_impedance_does_not_paint_usb():
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cons = ComponentConstraints(
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mpn="PHY",
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pintable=[Pin(number="1", name="D+")],
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absolute_maximum_ratings=[],
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rules=[],
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layout_rules=[{
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"kind": "impedance",
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"z0_ohm": 50,
|
||
"tolerance_pct": 10,
|
||
"note": "generic 50 Ω with no bus",
|
||
"source_page": 1,
|
||
}],
|
||
)
|
||
findings = check_si(_usb_graph(), {"PHY": cons}, _usb_layout(), _if_rows())
|
||
assert all(f.rule_id != "PE-SI-002" for f in findings)
|
||
assert any(f.rule_id == "PE-SI-010" for f in findings)
|