michele
4df04df5d4
Add /api/library datasheet import and component GET/PUT with no exam. Reorganize pytest into datasheet, library, schematic, PCB, and AF+AI. Document Rust criteria (none chosen; no rustup) and coding conformity.
312 lines
10 KiB
Python
312 lines
10 KiB
Python
"""Via is never a footprint pad. PE-BOM-011 uses parsed component pads only."""
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from __future__ import annotations
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from pathlib import Path
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from backend.periscopex.bom_pcb_check import check_bom_pcb_datasheet
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from backend.periscopex.models import (
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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LayoutGraph,
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PackageInfo,
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Pin,
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)
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from backend.periscopex.parsers_kicad_pcb import parse_kicad_pcb
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def _smd_pad(num: int, x: float, y: float, net: str = "SIG") -> str:
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return (
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f' (pad "{num}" smd rect (at {x} {y}) (size 0.25 0.4) '
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f'(layers "F.Cu" "F.Mask" "F.Paste") (net 2 "{net}") '
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f'(pinfunction "P{num}") (pintype "passive"))\n'
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)
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def _via_pad(num: int, x: float, y: float, net: str, net_code: int = 1) -> str:
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"""KiCad stitching via stored as a copper-only thru_hole pad."""
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return (
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f' (pad "{num}" thru_hole circle (at {x} {y}) (size 0.6 0.6) '
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f'(drill 0.3) (layers "*.Cu") (net {net_code} "{net}"))\n'
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)
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def _board_via(x: float, y: float, net: str, net_code: int = 1) -> str:
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return (
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f' (via (at {x} {y}) (size 0.8) (drill 0.4) '
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f'(layers "F.Cu" "B.Cu") (net {net_code}))\n'
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)
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def _fp_via(x: float, y: float, net: str, net_code: int = 1) -> str:
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return (
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f' (via (at {x} {y}) (size 0.8) (drill 0.4) '
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f'(layers "F.Cu" "B.Cu") (net {net_code} "{net}"))\n'
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)
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def _qfn24_pcb(
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tmp_path: Path,
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*,
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n_pads: int = 24,
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stitch_via_pads: list[tuple[int, float, float, str]] | None = None,
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nested_vias: list[tuple[float, float, str]] | None = None,
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board_vias: list[tuple[float, float, str, int]] | None = None,
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extra_smd: list[tuple[int, float, float, str]] | None = None,
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ep_pad: bool = False,
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) -> Path:
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nets = {
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0: "",
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1: "GND",
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2: "SIG",
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3: "3V3",
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4: "VCC",
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}
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net_code = {v: k for k, v in nets.items() if v}
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body = ["(kicad_pcb (version 20240108) (generator pcbnew)\n"]
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for code, name in nets.items():
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body.append(f' (net {code} "{name}")\n')
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body.append(
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' (footprint "Package_DFN_QFN:QFN-24"\n'
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' (layer "F.Cu")\n'
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" (at 50 40 0)\n"
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' (property "Reference" "U1" (at 0 0 0) (effects (font (size 1 1))))\n'
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' (fp_rect (start -2.2 -2.2) (end 2.2 2.2) (layer "F.CrtYd") (stroke (width 0.05)))\n'
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)
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for i in range(1, n_pads + 1):
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body.append(_smd_pad(i, -1.5 + (i % 6) * 0.5, -1.5 + (i // 6) * 0.5))
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if extra_smd:
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for num, x, y, net in extra_smd:
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body.append(_smd_pad(num, x, y, net))
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if ep_pad:
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body.append(
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' (pad "25" smd custom (at 0 0) (size 0.2 0.2) '
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'(layers "F.Cu") (net 1 "GND") '
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'(pinfunction "EXP_25") (pintype "power_in"))\n'
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)
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for num, x, y, net in stitch_via_pads or []:
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body.append(_via_pad(num, x, y, net, net_code.get(net, 2)))
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for x, y, net in nested_vias or []:
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body.append(_fp_via(x, y, net, net_code.get(net, 2)))
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body.append(" )\n")
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for x, y, net, _code in board_vias or []:
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body.append(_board_via(x, y, net, net_code.get(net, 2)))
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body.append(")\n")
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p = tmp_path / "board.kicad_pcb"
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p.write_text("".join(body))
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return p
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def _ds24() -> tuple[DesignGraph, dict]:
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pins = [Pin(number=str(i), name=f"P{i}") for i in range(1, 25)]
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cons = ComponentConstraints(
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mpn="IC24",
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package_info=PackageInfo(base_family="QFN", package="QFN-24", pin_count=24),
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pintable=pins,
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absolute_maximum_ratings=[],
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rules=[],
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)
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1",
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value="IC",
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footprint="Package_DFN_QFN:QFN-24",
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component_type=ComponentType.IC,
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mpn="IC24",
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pins={str(i): "SIG" for i in range(1, 25)},
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),
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},
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)
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return graph, {"IC24": cons}
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def _bom_ids(tmp_path: Path, **pcb_kw) -> tuple[set[str], LayoutGraph]:
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layout = parse_kicad_pcb(_qfn24_pcb(tmp_path, **pcb_kw))
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graph, cmap = _ds24()
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ids = {f.rule_id for f in check_bom_pcb_datasheet(graph, cmap, layout)}
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return ids, layout
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def test_24_pads_0_vias_no_mismatch(tmp_path: Path):
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ids, layout = _bom_ids(tmp_path, n_pads=24)
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u1 = layout.footprints["U1"]
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assert len(u1.pads) == 24
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assert layout.vias == []
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assert "PE-BOM-011" not in ids
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def test_stitching_via_pads_are_vias_not_pads(tmp_path: Path):
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stitches = [(25 + i, -1.0 + (i % 3) * 0.7, -1.0 + (i // 3) * 0.7, "GND") for i in range(9)]
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ids, layout = _bom_ids(tmp_path, n_pads=24, stitch_via_pads=stitches)
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u1 = layout.footprints["U1"]
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assert [p.number for p in u1.pads] == [str(i) for i in range(1, 25)]
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assert len(u1.pads) == 24
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assert len(layout.vias) == 9
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assert all(v.net == "GND" for v in layout.vias)
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assert "PE-BOM-011" not in ids
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def test_nearby_external_board_vias_not_counted_as_pads(tmp_path: Path):
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nearby = [
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(52.0, 40.0, "GND", 1),
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(48.0, 42.0, "3V3", 3),
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(50.5, 37.5, "SIG", 2),
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]
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ids, layout = _bom_ids(tmp_path, n_pads=24, board_vias=nearby)
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assert len(layout.footprints["U1"].pads) == 24
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assert len(layout.vias) == 3
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assert "PE-BOM-011" not in ids
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def test_vias_inside_footprint_courtyard_not_pads(tmp_path: Path):
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inside = [
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(50.0, 40.0, "GND", 1),
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(50.4, 40.4, "VCC", 4),
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(49.6, 39.6, "SIG", 2),
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]
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ids, layout = _bom_ids(tmp_path, n_pads=24, board_vias=inside)
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assert len(layout.footprints["U1"].pads) == 24
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assert len(layout.vias) == 3
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assert "PE-BOM-011" not in ids
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def test_nested_footprint_via_token_is_via(tmp_path: Path):
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ids, layout = _bom_ids(
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tmp_path,
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n_pads=24,
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nested_vias=[(0.0, 0.0, "GND"), (0.5, 0.5, "3V3")],
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)
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assert len(layout.footprints["U1"].pads) == 24
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assert len(layout.vias) == 2
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nets = {v.net for v in layout.vias}
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assert nets == {"GND", "3V3"}
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assert "PE-BOM-011" not in ids
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def test_via_pads_on_gnd_3v3_vcc_signal(tmp_path: Path):
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stitches = [
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(26, 0.0, 0.0, "GND"),
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(27, 0.5, 0.0, "3V3"),
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(28, 0.0, 0.5, "VCC"),
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(29, 0.5, 0.5, "SIG"),
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]
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ids, layout = _bom_ids(tmp_path, n_pads=24, stitch_via_pads=stitches)
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assert len(layout.footprints["U1"].pads) == 24
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assert {v.net for v in layout.vias} == {"GND", "3V3", "VCC", "SIG"}
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assert "PE-BOM-011" not in ids
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def test_true_mismatch_24_vs_23_still_fires(tmp_path: Path):
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ids, layout = _bom_ids(tmp_path, n_pads=23)
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assert len(layout.footprints["U1"].pads) == 23
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assert "PE-BOM-011" in ids
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def test_true_mismatch_24_vs_25_still_fires(tmp_path: Path):
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ids, layout = _bom_ids(
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tmp_path,
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n_pads=24,
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extra_smd=[(30, 1.8, 1.8, "SIG")],
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)
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assert len(layout.footprints["U1"].pads) == 25 # 24 signal + extra 30
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assert "PE-BOM-011" in ids
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def test_vias_do_not_hide_true_mismatch(tmp_path: Path):
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stitches = [(40 + i, 0.2 * i, 0.2, "GND") for i in range(6)]
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board = [(51.0, 41.0, "3V3", 3), (49.0, 39.0, "SIG", 2)]
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ids23, layout23 = _bom_ids(
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tmp_path, n_pads=23, stitch_via_pads=stitches, board_vias=board,
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)
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assert len(layout23.footprints["U1"].pads) == 23
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assert len(layout23.vias) == 8
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assert "PE-BOM-011" in ids23
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tmp2 = tmp_path / "b"
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tmp2.mkdir()
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ids25, layout25 = _bom_ids(
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tmp2,
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n_pads=24,
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extra_smd=[(30, 1.8, 1.8, "SIG")],
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stitch_via_pads=stitches,
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board_vias=board,
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)
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assert len(layout25.footprints["U1"].pads) == 25
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assert "PE-BOM-011" in ids25
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def test_exposed_pad_plus_via_array_matches_24_pin_datasheet(tmp_path: Path):
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"""QFN-24 + EP land + thermal via array: pin_count 24, not 34."""
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stitches = [(26 + i, -0.6 + (i % 3) * 0.6, -0.6 + (i // 3) * 0.6, "GND") for i in range(9)]
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ids, layout = _bom_ids(tmp_path, n_pads=24, stitch_via_pads=stitches, ep_pad=True)
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u1 = layout.footprints["U1"]
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assert len(u1.pads) == 25
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assert any(p.number == "25" and p.pinfunction == "EXP_25" for p in u1.pads)
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assert len(layout.vias) == 9
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assert "PE-BOM-011" not in ids
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def test_tht_solder_pads_stay_component_pads(tmp_path: Path):
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p = tmp_path / "tht.kicad_pcb"
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p.write_text("""(kicad_pcb (version 20240108)
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(net 0 "")
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(net 1 "GND")
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(net 2 "SIG")
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(footprint "Resistor_THT:R_Axial"
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(layer "F.Cu")
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(at 0 0 0)
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(property "Reference" "R1" (at 0 0 0) (effects (font (size 1 1))))
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(pad "1" thru_hole circle (at -3.81 0) (size 1.6 1.6) (drill 0.8)
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(layers "*.Cu" "*.Mask") (net 2 "SIG"))
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(pad "2" thru_hole circle (at 3.81 0) (size 1.6 1.6) (drill 0.8)
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(layers "*.Cu" "*.Mask") (net 1 "GND"))
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)
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)
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""")
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g = parse_kicad_pcb(p)
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assert [p.number for p in g.footprints["R1"].pads] == ["1", "2"]
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assert g.vias == []
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class _Ws:
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def __init__(self, root: Path):
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self.root = root
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def local_path(self, rel: str) -> Path:
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return self.root / rel
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def _upload_file(self, rel: str) -> None:
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return None
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def test_pcb_pipeline_reparses_stale_layout_graph(tmp_path: Path):
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from backend.periscopex.models import LayoutFootprint, LayoutGraph, LayoutPad
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from backend.services.pcb_pipeline import _load_layout
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uploads = tmp_path / "uploads"
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uploads.mkdir()
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pcb = _qfn24_pcb(
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tmp_path,
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n_pads=24,
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stitch_via_pads=[(26, 0.0, 0.0, "GND")],
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)
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(uploads / "pcb.kicad_pcb").write_text(pcb.read_text())
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stale = LayoutGraph(
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footprints={
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"U1": LayoutFootprint(
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reference="U1",
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footprint="QFN-24",
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x=0, y=0, layer="F.Cu",
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pads=[LayoutPad(number=str(i), x=0, y=0, net="GND") for i in range(1, 35)],
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),
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},
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)
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(tmp_path / "layout_graph.json").write_text(stale.model_dump_json())
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layout = _load_layout(_Ws(tmp_path))
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assert layout is not None
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assert len(layout.footprints["U1"].pads) == 24
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assert len(layout.vias) == 1
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