micheleandCursor
45e820fabc
PS-SI-001 and decoupling skip without a numeric layout_rule. Tests use simple_project nets, not invented USBPHY boards. Co-authored-by: Cursor <cursoragent@cursor.com>
44 lines
1.3 KiB
Python
44 lines
1.3 KiB
Python
"""G2 placement vs simple_project — no invented 15 mm / 2 mm boards.
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Favor: real U1 + caps on +3V3 exist; eval stays 3 keys.
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Against: no .kicad_pcb → no PS-PLC-001; no 3 mm default.
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"""
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from __future__ import annotations
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from pathlib import Path
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from backend.pinscopex.eval_report import eval_simple_project
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from backend.pinscopex.models import DesignGraph
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from backend.pinscopex.placement_check import check_placement
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SIMPLE = Path(__file__).resolve().parents[1] / "simple_project"
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def _graph() -> DesignGraph:
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return DesignGraph.model_validate_json(
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(SIMPLE / "design_graph.json").read_text()
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)
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def test_simple_project_has_ldo_and_3v3_caps():
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g = _graph()
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assert "U1" in g.components
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assert g.components["U1"].mpn == "SPX3819M5-L-3-3/TR"
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caps = g.capacitors_on_net("+3V3")
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assert caps, "simple_project must keep decoupling caps on +3V3"
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def test_simple_project_without_pcb_has_no_ps_plc_001():
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findings = check_placement(_graph(), {}, None)
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assert findings == []
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assert all(f.rule_id != "PS-PLC-001" for f in findings)
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def test_simple_project_eval_has_no_placement_keys():
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scores = eval_simple_project(SIMPLE)
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assert scores.finding_count == 3
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assert scores.precision == 1.0
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assert scores.recall == 1.0
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assert not any(k.startswith("PS-PLC-") for k in scores.extra_keys)
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