michele
342792df2d
ERROR stays only for RULE+MANDATORY. Hierarchy walks component→pin→net→block. Derating is PASS/MARGIN/RISK from Vop/Vrated. Timing and PI skip without numbers. ESD and HS return path are REVIEW, not RULE ERROR.
309 lines
10 KiB
Python
309 lines
10 KiB
Python
"""Fase B slices: hierarchy, derating stress, timing, PI, ESD/return."""
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from __future__ import annotations
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from backend.periscopex.esd_return_check import check_esd, check_return_path
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from backend.periscopex.finding_engine import complete_finding
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from backend.periscopex.hierarchy import build_hierarchy, check_hierarchy
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from backend.periscopex.models import (
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CapacitorSpecs,
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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Finding,
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InternalFeatures,
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LayoutFootprint,
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LayoutGraph,
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LayoutSegment,
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LayoutVia,
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LayoutZone,
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Net,
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NetType,
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Pin,
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PinConnection,
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ResistorSpecs,
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SimpleComponentSpecs,
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)
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from backend.periscopex.pcb_checks import check_pcb_derating
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from backend.periscopex.pi_check import check_power_integrity
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from backend.periscopex.timing_check import check_timing
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def test_hierarchy_component_pin_net_block():
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="LDO", footprint="",
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component_type=ComponentType.IC, mpn="LDO",
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pins={"1": "VIN", "2": "+3V3", "3": ""},
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),
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},
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nets={
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"VIN": Net(
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name="VIN", net_type=NetType.POWER, voltage=5.0,
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pins=[PinConnection(component_ref="U1", pin_number="1")],
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),
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"+3V3": Net(
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name="+3V3", net_type=NetType.POWER, voltage=3.3,
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pins=[PinConnection(component_ref="U1", pin_number="2")],
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),
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},
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)
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hier = build_hierarchy(graph)
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assert hier.components[0].ref == "U1"
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assert {p.number: p.net for p in hier.components[0].pins}["1"] == "VIN"
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assert any(b.kind == "rail" for b in hier.blocks)
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dangling = check_hierarchy(graph)
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assert dangling and dangling[0].rule_id == "PE-HIER-001"
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assert dangling[0].status == "INFO"
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assert dangling[0].facts
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def test_derating_pass_margin_risk():
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def cap(ref, rated, net="3V3"):
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return Component(
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reference=ref, value="", footprint="",
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component_type=ComponentType.CAPACITOR,
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component_subtype="passive.capacitor.ceramic",
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mpn=ref,
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pins={"1": net, "2": "GND"},
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specs=CapacitorSpecs(
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value_farads=1e-6, value_formatted="1uF",
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voltage_rating_v=f"{rated}V", dielectric="X7R",
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),
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)
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g = DesignGraph(
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components={
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"C1": cap("C1", 16),
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"C2": cap("C2", 4.0),
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"C3": cap("C3", 3.0),
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},
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nets={
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"3V3": Net(
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name="3V3", net_type=NetType.POWER, voltage=3.3,
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pins=[
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PinConnection(component_ref="C1", pin_number="1"),
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PinConnection(component_ref="C2", pin_number="1"),
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PinConnection(component_ref="C3", pin_number="1"),
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],
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),
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"GND": Net(name="GND", net_type=NetType.GROUND, voltage=0.0, pins=[]),
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},
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)
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from backend.periscopex.derating import build_derating_table
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by = {r["designator"]: r["stress"] for r in build_derating_table(g)}
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assert by["C1"] == "PASS"
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assert by["C2"] == "MARGIN"
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assert by["C3"] == "RISK"
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findings = check_pcb_derating(g)
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ids = {f.rule_id for f in findings}
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assert "PE-DRT-001" in ids
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assert "PE-DRT-002" in ids
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assert "PE-DRT-003" in ids
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exceed = next(f for f in findings if f.rule_id == "PE-DRT-001")
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complete_finding(exceed)
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assert exceed.status == "ERROR"
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assert exceed.finding_class == "RULE"
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margin = next(f for f in findings if f.rule_id == "PE-DRT-002")
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complete_finding(margin)
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assert margin.status == "WARNING"
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assert margin.finding_class == "RISK"
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def test_timing_skips_without_numbers():
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="", footprint="",
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component_type=ComponentType.IC, mpn="MCU",
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pins={"1": "NRST"},
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),
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"R1": Component(
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reference="R1", value="10k", footprint="",
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component_type=ComponentType.RESISTOR, mpn="",
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pins={"1": "NRST", "2": "+3V3"},
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),
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},
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nets={"NRST": Net(name="NRST", net_type=NetType.SIGNAL, pins=[])},
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)
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cons = ComponentConstraints(
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mpn="MCU",
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pintable=[Pin(number="1", name="NRST")],
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absolute_maximum_ratings=[],
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rules=[],
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)
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assert check_timing(graph, {"MCU": cons}) == []
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def test_timing_reset_rc_vs_t_reset():
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="", footprint="",
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component_type=ComponentType.IC, mpn="MCU",
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pins={"1": "NRST"},
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specs=SimpleComponentSpecs(
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specs_type="discrete",
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values={"t_reset_min_s": 0.01},
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),
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),
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"R1": Component(
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reference="R1", value="1k", footprint="",
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component_type=ComponentType.RESISTOR, mpn="",
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pins={"1": "NRST", "2": "+3V3"},
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specs=ResistorSpecs(value_ohms=1000, value_formatted="1k"),
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),
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"C1": Component(
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reference="C1", value="100n", footprint="",
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component_type=ComponentType.CAPACITOR, mpn="",
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pins={"1": "NRST", "2": "GND"},
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specs=CapacitorSpecs(value_farads=100e-9, value_formatted="100n"),
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),
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},
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nets={
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"NRST": Net(
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name="NRST", net_type=NetType.SIGNAL,
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pins=[
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PinConnection(component_ref="U1", pin_number="1"),
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PinConnection(component_ref="R1", pin_number="1"),
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PinConnection(component_ref="C1", pin_number="1"),
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],
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),
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"+3V3": Net(name="+3V3", net_type=NetType.POWER, voltage=3.3, pins=[]),
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"GND": Net(name="GND", net_type=NetType.GROUND, pins=[]),
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},
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)
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cons = ComponentConstraints(
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mpn="MCU",
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pintable=[Pin(number="1", name="NRST")],
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absolute_maximum_ratings=[],
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rules=[],
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)
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findings = check_timing(graph, {"MCU": cons})
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assert findings and findings[0].rule_id == "PE-TIM-001"
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complete_finding(findings[0])
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assert findings[0].status == "ERROR"
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assert findings[0].finding_class == "RULE"
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def test_pi_missing_local_is_risk_not_error():
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="LDO", footprint="",
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component_type=ComponentType.IC, mpn="LDO",
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pins={"1": "VIN"},
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),
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},
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nets={
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"VIN": Net(
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name="VIN", net_type=NetType.POWER, voltage=5.0,
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pins=[PinConnection(component_ref="U1", pin_number="1")],
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),
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},
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)
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cons = ComponentConstraints(
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mpn="LDO",
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pintable=[Pin(number="1", name="VIN")],
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absolute_maximum_ratings=[],
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rules=[],
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)
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findings = check_power_integrity(graph, {"LDO": cons})
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assert findings and findings[0].rule_id == "PE-PI-001"
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complete_finding(findings[0])
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assert findings[0].status == "WARNING"
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assert findings[0].finding_class == "RISK"
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def test_esd_without_part_is_review_not_error():
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graph = DesignGraph(
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components={
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"J1": Component(
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reference="J1", value="USB", footprint="",
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component_type=ComponentType.CONNECTOR, mpn="",
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pins={"1": "USB_DP"},
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),
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"U2": Component(
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reference="U2", value="UART", footprint="",
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component_type=ComponentType.IC, mpn="CH",
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pins={"1": "USB_DP"},
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),
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},
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nets={
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"USB_DP": Net(
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name="USB_DP", net_type=NetType.SIGNAL,
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pins=[
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PinConnection(component_ref="J1", pin_number="1"),
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PinConnection(component_ref="U2", pin_number="1"),
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],
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),
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},
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)
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cons = ComponentConstraints(
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mpn="CH",
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pintable=[Pin(number="1", name="UD+")],
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absolute_maximum_ratings=[],
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rules=[],
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internal_features=InternalFeatures(esd_clamp_pins=["UD+"]),
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)
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findings = check_esd(graph, {"CH": cons})
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assert findings and findings[0].rule_id == "PE-ESD-001"
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complete_finding(findings[0])
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assert findings[0].finding_class == "REVIEW"
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assert findings[0].status != "ERROR"
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def test_return_path_hs_is_review():
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="", footprint="",
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component_type=ComponentType.IC, mpn="X",
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pins={"1": "USB_DP"},
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),
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},
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nets={
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"USB_DP": Net(
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name="USB_DP", net_type=NetType.SIGNAL,
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pins=[PinConnection(component_ref="U1", pin_number="1")],
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),
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},
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)
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layout = LayoutGraph(
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footprints={"U1": LayoutFootprint(reference="U1", x=0, y=0, layer="F.Cu")},
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segments=[
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LayoutSegment(start=(0, 0), end=(20, 8), width=0.2, layer="F.Cu", net="USB_DP"),
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],
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zones=[
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LayoutZone(net="GND", layer="B.Cu", outlines=[[(0, -5), (20, -5), (20, 10), (0, 10)]]),
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],
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vias=[],
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)
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findings = check_return_path(graph, layout)
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assert findings and findings[0].rule_id == "PE-RET-001"
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complete_finding(findings[0])
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assert findings[0].finding_class == "REVIEW"
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assert findings[0].status != "ERROR"
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layout.vias = [LayoutVia(x=10, y=4, net="GND", drill=0.3)]
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assert check_return_path(graph, layout) == []
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def test_llm_error_review_clamped_in_complete_finding():
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f = Finding(
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designator="U1",
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finding="no vias",
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why="PowerPAD",
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status="ERROR",
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source="pcb_review",
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facts="0 vias",
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requirement="must have vias",
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source_quote="Use thermal vias in the exposed pad.",
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evidence_status="SUFFICIENT",
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)
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complete_finding(f)
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assert f.finding_class == "REVIEW"
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assert f.status == "WARNING"
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