validate/validation_tools alias native lookup and review tools. Passive
resolve, derating, BOM summary, pin-mux, LED current, and net-function
tokens are original Periscope code. finding_engine and pcb_* unchanged.
TAXONOMY_DIR is taxonomy_dir() so src reads dependency/taxonomy until a src tree exists. Inherited taxonomy.py stays on disk. Changelog covers models, parsers, and taxonomy.
utils, resolve_passives, derating, bom_summary, pin_mux, LED current,
pin-function tokens, plus live analysis validate/validation_tools/pipeline/
validation/extraction, skills, and taxonomy JSON now resolve from
periscope/src. Inherited copies stay in dependency/. repo_paths prefers
src then /app; Docker copies src taxonomy/skills last.
Src-first imports now load graph/parsers/EDIF/models/taxonomy from
periscope/src. Inherited copies stay in dependency/. Taxonomy JSON path
uses repo_paths. New periscope/lens mark at existing 16/32/180/192/512
favicon sizes; header uses PeriscopeMark instead of the lucide CPU glyph.
Cached layout_graph still listed stitching via-pads as component pads,
so PE-BOM-011 kept firing after the ingest fix. PCB/placement jobs now
parse the board file and refresh the cache.
KiCad stitching/thermal vias inside a footprint are (via) or copper-only
thru_hole (pad) objects. parse_kicad_pcb was appending every (pad) to
LayoutFootprint.pads, so PE-BOM-011 compared datasheet pin_count to via
numbers. Nested vias join LayoutGraph.vias; soldered THT pads stay pads.
Live review_ic_async comes from review_session; PinScope validate.py and
validation_tools.py stay in dependency as _inherited_review_ic_async fallback.
Keep validate.py and the finding engine as-is. AGPL LICENSE stays at the repo root.
Docker overlays dependency then src. Do not delete the inherited tree.
PE-SI-009 no longer treats ESP32 CHIP_PU/EN RC as a USB series R.
USB without a library Z number stays PE-SI-010 measurement-only.
Pintable skill 1.13.0 requires net_class on SI kinds (usb2/usb3/MDI/RGMII/DDR3).
Package/pinout/ratings mismatches, SPOF as REVIEW, EMI only with a
datasheet quote, and Tj from copper+vias+θJA when every parameter exists.
Re-extract SI layout_rules from 1.12.0; ImpedenceFinder license stays UNKNOWN.
Each layout_rules SI requirement (diff/SE Z, skew, max length, spacing,
ref plane, vias, layer, return, series R) is one PASS/FAIL/MARGIN finding
with FACT and REQUIREMENT. USB/HDMI/PCIe/ETH/LVDS/DDR only; I2C GPIO CC
and analog REGN are skipped. No invented 90 Ω.
The status watcher synthesized pcb_error with pcb_status=complete (terminal)
when the worker finished before pcb_complete arrived. Map that hatch to
pcb_complete, publish the event before flipping status, and send /pcb to
the layout report tree.
PE-ESD-001 only on J* connector–IC nets (skip NC, unconnected, VSYS/GND/3V3).
PE-PI-001 treats any capacitor on the rail, including KiCad slash prefixes, as
decoupling. Sort findings ERROR then WARNING then INFO, then RULE/RISK/REVIEW/INFO.
Report sidebar is a collapsed expand-on-click tree instead of an all-open list.
GET /report and complete_findings fail-soft and sort the same way.
ERROR stays only for RULE+MANDATORY. Hierarchy walks component→pin→net→block.
Derating is PASS/MARGIN/RISK from Vop/Vrated. Timing and PI skip without numbers.
ESD and HS return path are REVIEW, not RULE ERROR.
Layout and AI findings always get action (fallback recommendation). The card
renders that sentence in the body. PCB review context now includes vias under
the footprint, copper thickness, nearby widths, courtyard, and keepout polygons.
Fill action on every finding and show it in the report. Stitch/return only
on large HS/power nets. Parse stackup thickness, arcs, and vias from the
board. IC courtyard pad copper is not PE-PLC-004 RULE. Recommended RC/cap
stay REVIEW.
FACT, REQUIREMENT, and INFERENCE are separate fields; datasheet provenance
lives in the rule DB so Recommended cannot stay ERROR; LLM output is REVIEW.
Designer decisions persist across rescans. Schematic and PCB share one library
and the same finding object in the report UI.
PCB AI skips a second PDF exam (pintable cache, pdf_path=None) and the report
gains a PCB exam section plus power-trace, thermal, via, Kelvin, and GND-stitch
checks grounded in board geometry and extracted specs.
Pad-net compare strips leading slash and nested sheet path so /ESP32_EN
matches ESP32_EN. If every mismatch is only that prefix, emit PE-LAY-003
once instead of per-pad reconnect errors.
A container rebuild left Emmaforo status=running with no process, so
PCB start kept 409. Heal on GET now matches placement/PCB: complete if
report.json exists, otherwise error.
update_project used meta.user_id for the path, so JWT projects that still
have user_id=local never persisted pcb_status=queued and the PCB worker
exited as draft. Point writes at the prefix used to read the project.
Refuse update-periscope.sh unless dirname resolves to the canonical
checkout, set compose project name periscope, and document that the
GitHub clone URL may still be manvalan/pinscope.
michele