Commit Graph
18 Commits
Author SHA1 Message Date
michele 8f4ebc645c Share library/extracted for schematic and PCB review.
PCB AI skips a second PDF exam (pintable cache, pdf_path=None) and the report
gains a PCB exam section plus power-trace, thermal, via, Kelvin, and GND-stitch
checks grounded in board geometry and extracted specs.
2026-09-20 08:32:23 +02:00
michele a2011dad91 Update PCB review plan: AI exam like schematic, no auto-place.
Adds per-IC LLM review, domains/groups as exam context, required
recommendations, and phased job MODE=pcb. Packing stays parked.
2026-09-19 22:43:58 +02:00
michele 721ede4243 Add PCB review plan: verify placement and routing, no auto-place.
Documents a parallel MODE=pcb exam job (inventory + datasheet-gated
checks) that reuses placement_check, si_check, and the placement job
pattern. Parks F2 packing/export.
2026-09-19 21:41:27 +02:00
micheleandCursor 8d2b85600f Rebrand Pinscope to Periscope across product and codebase.
Rename the core package to periscopex, update UI/docs/Docker/deploy defaults to periscope.michelebigi.it, and keep legacy version/storage key aliases so existing projects keep working.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 20:02:04 +02:00
micheleandCursor 556306bf4d Add IFA/meander/stub antenna templates with SVG and KiCad export.
Progetta now returns a parametric radiator geometry (segments + preview + .kicad_mod) so the layout can be replicated without inventing EM results.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 19:27:06 +02:00
micheleandCursor 1d3cf12482 Add RF antenna verify and design recipe to Impedance tab.
Detect matching toward ANT*/ANT_FEED, compute 50 Ω feed width from stackup, and optional λ/4 length from f0 — before auto-draw or F2 packing.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 18:57:59 +02:00
micheleandCursor 68af0fd432 Classify strap/bootstrap caps and drop unclassified satellites.
EN/BOOT/REGN/PMID bypass and flying bootstrap caps get real roles; other is omitted from assemble_order.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 18:37:01 +02:00
micheleandCursor 21e2be1cd0 Strengthen pintable layout_rules skill and refresh empty extractions.
Treat PCB/application layout guidance as a first-class extract, keep those pages in PDF trim, and re-run IC extraction once when rules are still empty under older model_version.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 18:01:15 +02:00
micheleandCursor 86121e6547 Add gated Placement F2 pack skeleton for satellite xy.
Propose positions only from PCB footprints plus numeric decoupling max_distance_mm; otherwise skip with an explicit reason.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 17:50:47 +02:00
micheleandCursor 4c4b604cca Add parallel Placement pipeline for routing-first topology plans.
Ship a free, analysis-independent job that writes placement_plan.json (domains/satellites, no mm) with API, SSE progress, and a minimal project UI.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-12 16:41:00 +02:00
micheleandCursor 2950446e12 Add Layout F1 functional groups and crystal/NC checks.
Write routing-first domain/satellite topology after graph_build, and
flag crystal CL mismatches and NC pins on active nets without inventing
millimetres.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-12 16:22:56 +02:00
micheleandCursor 30aaf55de6 Ship DeepSeek roadmap P0-5/P2 integrations.
Smoke simple_project offline, reviewer shortest_path, library promotion
gate, PDF drop logs, and per-stage cache hit-rate helper — without
touching Layout placement packing.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-12 15:48:39 +02:00
micheleandCursor 3f6082ae6d Run ImpedenceFinder Z0 on routed signal nets during project analysis.
Pipeline samples PCB traces when stackup εr/h is present; power/ground are skipped. Named nets can be re-analyzed from the Impedance tab.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 00:21:49 +02:00
micheleandCursor 796cd9d8a2 Flag keepout tracks in the courtyard and mark the plan map OK.
PS-PLC-004 is a foreign net endpoint inside the KiCad courtyard. The lista↔codice table and sprints 0–10+ get an OK column where the hole is closed without invented millimetres.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 00:11:02 +02:00
micheleandCursor e4fd6c3849 Ship Sprint 0 CAD foundations so findings, KiCad hierarchy, BOM match, eval, and optional PCB ingest have a stable contract.
Extend Finding with rule_id/net/pins, flatten multi-sheet .kicad_sch, flag MPN mismatches, score simple_project, and parse .kicad_pcb without running layout DRC.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 21:54:37 +02:00
Siddharth Kothari a8c242933a README: add pipeline diagram 2026-07-17 00:19:56 -07:00
Siddharth Kothari 6e83ef9da0 Remove internal review case log; use support address in contact fallbacks
The false-positive case log documents real production designs and belongs
in the private repo only. Contact-form fallback strings now point at the
public support address.
2026-07-16 23:40:39 -07:00
Siddharth Kothari 6672d2be57 Pinscope open-source core
Agentic schematic validation: datasheet extraction via Claude Console
Skills, netlist/BOM design graph, per-IC direct datasheet review with
page citations, capacitor derating, Next.js report UI.

Extracted from the Pinscope cloud codebase. Auth and billing live in the
private gateway repo behind stable seams (billing_hook.py, adapter files
listed in CLAUDE.md).
2026-07-16 21:29:45 -07:00