Rename the core package to periscopex, update UI/docs/Docker/deploy defaults to periscope.michelebigi.it, and keep legacy version/storage key aliases so existing projects keep working.
Co-authored-by: Cursor <cursoragent@cursor.com>
Progetta now returns a parametric radiator geometry (segments + preview + .kicad_mod) so the layout can be replicated without inventing EM results.
Co-authored-by: Cursor <cursoragent@cursor.com>
EN/BOOT/REGN/PMID bypass and flying bootstrap caps get real roles; other is omitted from assemble_order.
Co-authored-by: Cursor <cursoragent@cursor.com>
Stop LDO 3V3 groups from inheriting VSYS caps/filters, drop connector/switch noise, and align Power rails with domain membership.
Co-authored-by: Cursor <cursoragent@cursor.com>
Treat PCB/application layout guidance as a first-class extract, keep those pages in PDF trim, and re-run IC extraction once when rules are still empty under older model_version.
Co-authored-by: Cursor <cursoragent@cursor.com>
Propose positions only from PCB footprints plus numeric decoupling max_distance_mm; otherwise skip with an explicit reason.
Co-authored-by: Cursor <cursoragent@cursor.com>
Sidebar tabs show routing-first topology from placement_plan/functional_groups, with IC groups and satellite roles highlighted per domain and per supply rail.
Co-authored-by: Cursor <cursoragent@cursor.com>
If the event log already ends with pipeline_complete, flip meta to complete on project/status fetch so Progress no longer spins on a dead worker.
Co-authored-by: Cursor <cursoragent@cursor.com>
Gate /progress SSE and auto-redirect on a live queued/running status so historical pipeline_complete events no longer flash Processing then open the report.
Co-authored-by: Cursor <cursoragent@cursor.com>
Open finished projects on the hub instead of /report, and hard-navigate when leaving nested report/progress/placement routes for Dashboard, Library, and hub tabs.
Co-authored-by: Cursor <cursoragent@cursor.com>
Ship a free, analysis-independent job that writes placement_plan.json (domains/satellites, no mm) with API, SSE progress, and a minimal project UI.
Co-authored-by: Cursor <cursoragent@cursor.com>
Write routing-first domain/satellite topology after graph_build, and
flag crystal CL mismatches and NC pins on active nets without inventing
millimetres.
Co-authored-by: Cursor <cursoragent@cursor.com>
AUTH_JWT_SECRET was never written because upsert ran before git pull;
sidebar used Button asChild which Base UI does not support.
Co-authored-by: Cursor <cursoragent@cursor.com>
Schematic geometry on KiCad 10 boards was swapping rails and inventing
floating pins; board connectivity is authoritative when a PCB is uploaded.
Co-authored-by: Cursor <cursoragent@cursor.com>
Disconnected GND power flags were named GND_/GND__/… so the reviewer
flagged swapped rails and floating pins on correctly wired designs.
Co-authored-by: Cursor <cursoragent@cursor.com>
Sheets, optional BOM, and PCB are extracted together; a storage round-trip test proves the pipeline can re-parse child Sheetfiles.
Co-authored-by: Cursor <cursoragent@cursor.com>
A single .kicad_sch was parsed in isolation, so child sheets looked like an empty netlist. Report 404s now surface the real API error instead of a generic fetch failure.
Co-authored-by: Cursor <cursoragent@cursor.com>
Pipeline samples PCB traces when stackup εr/h is present; power/ground are skipped. Named nets can be re-analyzed from the Impedance tab.
Co-authored-by: Cursor <cursoragent@cursor.com>
PS-PLC-004 is a foreign net endpoint inside the KiCad courtyard. The lista↔codice table and sprints 0–10+ get an OK column where the hole is closed without invented millimetres.
Co-authored-by: Cursor <cursoragent@cursor.com>
X1 uses the same proximity rule as ICs. A detour is shortest path on PCB segments versus that millimetre, not a guessed loop ratio.
Co-authored-by: Cursor <cursoragent@cursor.com>
PS-PLC-003 uses the same_layer flag plus F/B layers from the PCB. A via in the courtyard is enough; an unset flag skips.
Co-authored-by: Cursor <cursoragent@cursor.com>
Skip without courtyard geometry or a numeric count — no pad-radius default. Tests use simple_project plus explicit coordinates as parameters.
Co-authored-by: Cursor <cursoragent@cursor.com>
PS-SI-001 and decoupling skip without a numeric layout_rule. Tests use simple_project nets, not invented USBPHY boards.
Co-authored-by: Cursor <cursoragent@cursor.com>
PS-PLC-001 fires only with a LayoutGraph: 15 mm vs a 2 mm rule is an error, a 1 mm cap is silent, and a null millimetre uses the declared 3 mm default as WARNING.
Co-authored-by: Cursor <cursoragent@cursor.com>
Accepted findings become ECO rows with a required reason; false-positive and wontfix stay off the change list. Pipeline re-runs keep dispositions by finding_id like comments.
Co-authored-by: Cursor <cursoragent@cursor.com>
Use the vendored Hammerstad-Jensen/Cohn engine for microstrip, stripline, and coupled-diff advice. Skip OpenEMS/pcbnew and refuse CPWG rather than inventing a number.
Co-authored-by: Cursor <cursoragent@cursor.com>
PROVIDER_*=anthropic and Claude fallbacks now coerce to DeepSeek, skills stay local, and default_model_version bumps without upload_skills.py.
Co-authored-by: Cursor <cursoragent@cursor.com>
Cache distributor EOL/NRND/RoHS without inventing replacements, flag catalogued errata pull-ups only, and store layout_rules with a closed kind enum so millimetres stay null unless the datasheet stated a number.
Co-authored-by: Cursor <cursoragent@cursor.com>
Write pinscope-findings.json from the report, keep symbol uuid and child-sheet on the graph, and let the pcbnew plugin jump to a footprint or show the schematic uuid when IPC focus is unavailable.
Co-authored-by: Cursor <cursoragent@cursor.com>
Compare only specified IQ plus I_load to Iout_max and series-R drop, flag sequencing only when power_sequence is in specs, and treat DNP as a fitted-variant graph so a missing enable pull is ERROR only when the BOM actually marks DNP.
Co-authored-by: Cursor <cursoragent@cursor.com>
Match RC/LC/π/T without inventing fc, compare to ADC rate only when specs list it, and skip ferrite DCR unless the IC gives a limit. LDO Tj uses I_load not Iout_max, and missing θJA stays INFO.
Co-authored-by: Cursor <cursoragent@cursor.com>
Keep these as WARNING hints with wide bounds so a 4.7 kΩ or 100 nF VDD cap is not treated as a datasheet µF error.
Co-authored-by: Cursor <cursoragent@cursor.com>
V4.1 is natively multimodal so every stage uses deepseek-flash; pricing and the UI now surface dollars instead of empty credits. KiCad netlists and neighborhood fingerprints land in the same cut so a second run can keep the project and skip unchanged ICs.
Co-authored-by: Cursor <cursoragent@cursor.com>
Ignore enable straps on a power rail, NC nets, and SPI aliases; treat FB as an inductor and RN as a resistor so pull-ups and beads classify correctly.
Co-authored-by: Cursor <cursoragent@cursor.com>
Skip the model (and the credit gate) when LCSC/DigiKey already list C/V/Z, when the BOM value is a single R/C/L/FB token, or when the MPN is an LQW18AN inductor. Ferrite beads keep impedance, not invented henries; value-only specs stay out of the shared library.
Co-authored-by: Cursor <cursoragent@cursor.com>
Add Microchip/Murata/Silicon Labs URL tables, optional Mouser search, and suggested URLs on a miss so the wizard can open PDFs in the user's browser when the VPS is blocked.
Co-authored-by: Cursor <cursoragent@cursor.com>
Hub Audio pull-ups sit on 3V3_DIGITAL typed as signal, and ADAU/TAC5212 SPI pins list SDA in the name — both produced false I2C/reset warnings.
Co-authored-by: Cursor <cursoragent@cursor.com>
Flag supply nets with no cap to ground and open-drain I2C/reset nets with no pull-up, without guessing datasheet capacitor values.
Co-authored-by: Cursor <cursoragent@cursor.com>
micheleandCursor