michele/periscope
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
80 Commits 8 Branches 1 Tag
1d3cf12482ed7e4d8291e8d8d1dd0b5c669523e2
Commit Graph
10 Commits
Author SHA1 Message Date
micheleandCursor 1d3cf12482 Add RF antenna verify and design recipe to Impedance tab. 
Detect matching toward ANT*/ANT_FEED, compute 50 Ω feed width from stackup, and optional λ/4 length from f0 — before auto-draw or F2 packing.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-13 18:57:59 +02:00
micheleandCursor 68af0fd432 Classify strap/bootstrap caps and drop unclassified satellites. 
EN/BOOT/REGN/PMID bypass and flying bootstrap caps get real roles; other is omitted from assemble_order.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-13 18:37:01 +02:00
micheleandCursor 21e2be1cd0 Strengthen pintable layout_rules skill and refresh empty extractions. 
Treat PCB/application layout guidance as a first-class extract, keep those pages in PDF trim, and re-run IC extraction once when rules are still empty under older model_version.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-13 18:01:15 +02:00
micheleandCursor 86121e6547 Add gated Placement F2 pack skeleton for satellite xy. 
Propose positions only from PCB footprints plus numeric decoupling max_distance_mm; otherwise skip with an explicit reason.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-13 17:50:47 +02:00
micheleandCursor 4c4b604cca Add parallel Placement pipeline for routing-first topology plans. 
Ship a free, analysis-independent job that writes placement_plan.json (domains/satellites, no mm) with API, SSE progress, and a minimal project UI.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-12 16:41:00 +02:00
micheleandCursor 2950446e12 Add Layout F1 functional groups and crystal/NC checks. 
Write routing-first domain/satellite topology after graph_build, and
flag crystal CL mismatches and NC pins on active nets without inventing
millimetres.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-12 16:22:56 +02:00
micheleandCursor 30aaf55de6 Ship DeepSeek roadmap P0-5/P2 integrations. 
Smoke simple_project offline, reviewer shortest_path, library promotion
gate, PDF drop logs, and per-stage cache hit-rate helper — without
touching Layout placement packing.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-12 15:48:39 +02:00
micheleandCursor 3f6082ae6d Run ImpedenceFinder Z0 on routed signal nets during project analysis. 
Pipeline samples PCB traces when stackup εr/h is present; power/ground are skipped. Named nets can be re-analyzed from the Impedance tab.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-11 00:21:49 +02:00
micheleandCursor 796cd9d8a2 Flag keepout tracks in the courtyard and mark the plan map OK. 
PS-PLC-004 is a foreign net endpoint inside the KiCad courtyard. The lista↔codice table and sprints 0–10+ get an OK column where the hole is closed without invented millimetres.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-11 00:11:02 +02:00
micheleandCursor e4fd6c3849 Ship Sprint 0 CAD foundations so findings, KiCad hierarchy, BOM match, eval, and optional PCB ingest have a stable contract. 
Extend Finding with rule_id/net/pins, flatten multi-sheet .kicad_sch, flag MPN mismatches, score simple_project, and parse .kicad_pcb without running layout DRC.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-10 21:54:37 +02:00