Add PCB intra-pair skew only when the datasheet gives millimetres.
PS-SI-001 and decoupling skip without a numeric layout_rule. Tests use simple_project nets, not invented USBPHY boards. Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
@@ -31,6 +31,7 @@ from backend.pinscopex.lifecycle import check_lifecycle
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from backend.pinscopex.errata_check import check_errata
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from backend.pinscopex.internal_features_check import check_internal_features
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from backend.pinscopex.placement_check import check_placement
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from backend.pinscopex.si_check import check_si
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class EvalScores(BaseModel):
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@@ -101,6 +102,7 @@ def run_deterministic_on_graph(graph: DesignGraph) -> list[Finding]:
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out.extend(check_errata(graph, cmap))
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out.extend(check_internal_features(graph, cmap))
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out.extend(check_placement(graph, cmap, None))
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out.extend(check_si(graph, cmap, None))
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return out
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@@ -4,7 +4,7 @@ from __future__ import annotations
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from typing import Any
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KNOWN_KINDS = frozenset({"decoupling_proximity", "thermal_via", "keepout"})
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KNOWN_KINDS = frozenset({"decoupling_proximity", "thermal_via", "keepout", "length_match"})
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def _num(v: Any) -> float | None:
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@@ -1,9 +1,7 @@
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"""G2: decoupling proximity on the PCB vs datasheet layout_rules.
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Runs only when a LayoutGraph is present. Empty layout_rules skip the IC.
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No capacitor on the rail does not invent a distance. A null
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max_distance_mm uses the declared DEFAULT_MAX_DISTANCE_MM (3 mm) as
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WARNING, never as an invented datasheet number.
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Runs only when a LayoutGraph is present and a decoupling_proximity rule
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has a numeric max_distance_mm. Null millimetres skip — no 3 mm default.
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"""
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from __future__ import annotations
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@@ -20,8 +18,6 @@ from backend.pinscopex.models import (
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)
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from backend.pinscopex.validate import _match_constraints
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DEFAULT_MAX_DISTANCE_MM = 3.0
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def _pad_for(layout: LayoutGraph, ref: str, number: str) -> LayoutPad | None:
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fp = layout.footprints.get(ref)
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@@ -95,20 +91,10 @@ def check_placement(
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nearest = min(_dist(ic_pad, p) for p in cap_pads)
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extracted = rule.get("max_distance_mm")
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if extracted is None:
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limit = DEFAULT_MAX_DISTANCE_MM
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used_default = True
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status = "WARNING"
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else:
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continue
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limit = float(extracted)
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used_default = False
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status = "ERROR"
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if nearest <= limit:
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continue
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why = (
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f"Datasheet does not specify mm; used default {DEFAULT_MAX_DISTANCE_MM:g} mm."
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if used_default
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else f"Datasheet max_distance_mm={limit:g}."
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)
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findings.append(Finding(
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designator=ref,
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mpn=comp.mpn or cons.mpn,
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@@ -117,8 +103,8 @@ def check_placement(
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f"Decoupling on {net} is {nearest:.1f} mm from {ref}.{pin_no} "
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f"(limit {limit:g} mm)."
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),
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why=why,
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status=status,
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why=f"Datasheet max_distance_mm={limit:g}.",
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status="ERROR",
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recommendation="Place the decoupling capacitor closer to the supply pin.",
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source="placement_check",
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rule_id="PS-PLC-001",
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@@ -0,0 +1,91 @@
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"""G1 SI: intra-pair skew only when the datasheet gives millimetres.
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Pair names (_DP/_DM, _P/_N) only identify which nets to compare. The
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limit is never 3W, USB spec folklore, or a default millimetre.
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"""
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from __future__ import annotations
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import math
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from backend.pinscopex.models import DesignGraph, Finding, LayoutGraph, LayoutSegment
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from backend.pinscopex.validate import _match_constraints
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_PAIR_SUFFIXES = (("_DP", "_DM"), ("_P", "_N"), ("+", "-"))
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def _seg_len(seg: LayoutSegment) -> float:
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return math.hypot(seg.end[0] - seg.start[0], seg.end[1] - seg.start[1])
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def net_length_mm(layout: LayoutGraph, net: str) -> float:
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return sum(_seg_len(s) for s in layout.segments if s.net == net)
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def partner_net(name: str) -> str | None:
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for a, b in _PAIR_SUFFIXES:
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if name.endswith(a):
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return name[: -len(a)] + b
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if name.endswith(b):
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return name[: -len(b)] + a
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return None
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def _length_match_limit_mm(constraints_map: dict, graph: DesignGraph) -> tuple[float, int | None] | None:
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for comp in graph.components.values():
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cons = _match_constraints(comp.mpn, constraints_map)
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if not cons:
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continue
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for rule in cons.layout_rules or []:
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if rule.get("kind") != "length_match":
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continue
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mm = rule.get("max_distance_mm")
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if mm is None:
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continue
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return float(mm), rule.get("source_page")
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return None
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def check_si(
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graph: DesignGraph,
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constraints_map: dict,
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layout: LayoutGraph | None,
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) -> list[Finding]:
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if layout is None or not layout.segments:
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return []
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limit = _length_match_limit_mm(constraints_map, graph)
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if limit is None:
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return []
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max_mm, page = limit
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seen: set[tuple[str, str]] = set()
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findings: list[Finding] = []
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names = {s.net for s in layout.segments if s.net}
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for net in names:
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partner = partner_net(net)
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if not partner or partner not in names:
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continue
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key = tuple(sorted((net, partner)))
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if key in seen:
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continue
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seen.add(key)
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skew = abs(net_length_mm(layout, net) - net_length_mm(layout, partner))
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if skew <= max_mm:
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continue
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findings.append(Finding(
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designator="layout",
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mpn="",
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aspect="si",
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finding=(
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f"Intra-pair skew {skew:.1f} mm on {key[0]}/{key[1]} "
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f"(datasheet max {max_mm:g} mm)."
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),
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why=f"length_match max_distance_mm={max_mm:g}.",
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status="ERROR",
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recommendation="Length-match the differential pair.",
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source="si_check",
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rule_id="PS-SI-001",
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net=net,
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pins=[],
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source_page=page,
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))
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return findings
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@@ -135,7 +135,7 @@ PINTABLE_TOOL = {
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},
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"layout_rules": {
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"type": "array",
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"description": "Optional PCB layout constraints from typical-application pages. kind must be decoupling_proximity, thermal_via, or keepout. max_distance_mm only if the PDF states a number.",
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"description": "Optional PCB layout constraints from typical-application pages. kind must be decoupling_proximity, thermal_via, keepout, or length_match. max_distance_mm only if the PDF states a number — never invent 3 mm or 3W.",
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"items": {"type": "object"},
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},
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},
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@@ -62,6 +62,7 @@ from backend.pinscopex.lifecycle import check_lifecycle, load_lifecycle_dir
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from backend.pinscopex.errata_check import check_errata
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from backend.pinscopex.internal_features_check import check_internal_features
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from backend.pinscopex.placement_check import check_placement
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from backend.pinscopex.si_check import check_si
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TRACE_VERSION = 1
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@@ -98,6 +99,7 @@ def _run_deterministic_checks(
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("errata_check", lambda: check_errata(graph, constraints_map)),
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("internal_features_check", lambda: check_internal_features(graph, constraints_map)),
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("placement_check", lambda: check_placement(graph, constraints_map, layout)),
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("si_check", lambda: check_si(graph, constraints_map, layout)),
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):
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try:
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out.extend(fn())
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@@ -1,5 +1,5 @@
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{
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"default_model_version": "1.8.0",
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"default_model_version": "1.9.0",
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"extract-pintable": {
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"skill_id": "skill_01VMWPZuvuZAe4LmLbmsNWNY",
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"latest_version": "1784798970179642",
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@@ -2,11 +2,17 @@
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What's new in Pinscope.
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## 2.21.0 — 2026-09-10 — Layout SI skew (datasheet mm only)
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Intra-pair skew is measured on the PCB only when `layout_rules` `length_match` has a number. 3W, creepage, and CPWG are not guessed.
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- [New] `PS-SI-001` ERROR when a named pair (_DP/_DM, _P/_N) exceeds that millimetre. No mm in the datasheet → skip.
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## 2.20.0 — 2026-09-10 — Placement vs datasheet (PCB)
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Decoupling distance is measured on the `.kicad_pcb` against `layout_rules`. No board → no `PS-PLC-001`. A null millimetre uses the declared 3 mm default as WARNING.
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Decoupling distance is measured on the `.kicad_pcb` against `layout_rules`. No board → no `PS-PLC-001`. A null millimetre skips — no 3 mm default.
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- [New] `PS-PLC-001` when a decoupling cap is farther than `max_distance_mm` (ERROR) or the 3 mm default (WARNING). Empty `layout_rules` and missing caps skip.
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- [New] `PS-PLC-001` when a decoupling cap is farther than datasheet `max_distance_mm`. Empty `layout_rules` and missing caps skip.
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## 2.19.0 — 2026-09-10 — Finding review and ECO
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@@ -31,7 +31,7 @@ Rules for pin extraction:
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Optional extras (omit if the PDF does not show them):
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- `internal_features.pullup_pins` / `esd_clamp_pins` / `analog_switch` from the **block diagram** only.
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- `layout_rules` from **PCB layout / typical application** pages. `kind` is only `decoupling_proximity`, `thermal_via`, or `keepout`. Set `max_distance_mm` only when the document states a number — do not invent JEDEC millimetres.
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- `layout_rules` from **PCB layout / typical application** pages. `kind` is only `decoupling_proximity`, `thermal_via`, `keepout`, or `length_match` (intra-pair skew mm). Set `max_distance_mm` only when the document states a number — do not invent JEDEC or USB millimetres.
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Rules for pin extraction:`
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- If the datasheet has separate tables for different packages, extract for the package matching the MPN
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@@ -85,7 +85,7 @@ def validate(data: dict) -> list[str]:
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if not isinstance(data["layout_rules"], list):
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errors.append("layout_rules must be an array")
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else:
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kinds = {"decoupling_proximity", "thermal_via", "keepout"}
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kinds = {"decoupling_proximity", "thermal_via", "keepout", "length_match"}
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for i, row in enumerate(data["layout_rules"]):
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if not isinstance(row, dict):
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errors.append(f"layout_rules[{i}] must be an object")
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@@ -29,6 +29,15 @@ def test_valid_decoupling_proximity_keeps_distance():
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assert ok[0]["kind"] == "decoupling_proximity"
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def test_length_match_kind_is_accepted():
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ok, errors = validate_layout_rules([
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{"kind": "length_match", "net_class": "diff", "max_distance_mm": 2.0, "source_page": 9},
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])
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assert errors == []
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assert ok[0]["kind"] == "length_match"
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assert ok[0]["max_distance_mm"] == 2.0
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def test_empty_list_is_explicit_skip():
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ok, errors = validate_layout_rules([])
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assert ok == []
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+31
-122
@@ -1,134 +1,43 @@
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"""G2 placement vs datasheet layout_rules — only with a LayoutGraph.
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"""G2 placement vs simple_project — no invented 15 mm / 2 mm boards.
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Favor: decoupling cap 15 mm from VDD pad with max_distance_mm=2 → PS-PLC-001;
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null mm uses declared 3 mm default as WARNING.
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Against: no PCB → silent; empty layout_rules skip; cap at 1 mm is ok;
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no cap on the net does not invent a millimetre.
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Favor: real U1 + caps on +3V3 exist; eval stays 3 keys.
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Against: no .kicad_pcb → no PS-PLC-001; no 3 mm default.
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"""
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from __future__ import annotations
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from backend.pinscopex.models import (
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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LayoutFootprint,
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LayoutGraph,
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LayoutPad,
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Net,
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NetType,
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Pin,
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PinConnection,
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)
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from pathlib import Path
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from backend.pinscopex.eval_report import eval_simple_project
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from backend.pinscopex.models import DesignGraph
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from backend.pinscopex.placement_check import check_placement
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SIMPLE = Path(__file__).resolve().parents[1] / "simple_project"
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def _graph():
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u = Component(
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reference="U1", value="", footprint="",
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component_type=ComponentType.IC, mpn="UTEST",
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pins={"1": "VDD", "2": "GND"},
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)
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c = Component(
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reference="C1", value="100n", footprint="",
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component_type=ComponentType.CAPACITOR, mpn="C",
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pins={"1": "+3V3", "2": "GND"},
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)
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return DesignGraph(
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components={"U1": u, "C1": c},
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nets={
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"+3V3": Net(name="+3V3", net_type=NetType.POWER, pins=[
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PinConnection(component_ref="U1", pin_number="1"),
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PinConnection(component_ref="C1", pin_number="1"),
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]),
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"GND": Net(name="GND", net_type=NetType.GROUND, pins=[
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PinConnection(component_ref="U1", pin_number="2"),
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PinConnection(component_ref="C1", pin_number="2"),
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]),
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},
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def _graph() -> DesignGraph:
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return DesignGraph.model_validate_json(
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(SIMPLE / "design_graph.json").read_text()
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)
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def _cons(max_mm: float | None):
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return {
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"UTEST": ComponentConstraints(
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mpn="UTEST",
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pintable=[Pin(number=1, name="VDD"), Pin(number=2, name="GND")],
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absolute_maximum_ratings=[], rules=[],
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layout_rules=[{
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"kind": "decoupling_proximity",
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"pin": "VDD",
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"max_distance_mm": max_mm,
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"source_page": 14,
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}],
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)
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}
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def _layout(cap_x: float) -> LayoutGraph:
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return LayoutGraph(
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footprints={
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"U1": LayoutFootprint(
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reference="U1", x=0, y=0, layer="F.Cu",
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pads=[
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LayoutPad(number="1", x=0.0, y=0.0, net="+3V3"),
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LayoutPad(number="2", x=0.0, y=1.0, net="GND"),
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],
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),
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"C1": LayoutFootprint(
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reference="C1", x=cap_x, y=0, layer="F.Cu",
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pads=[
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LayoutPad(number="1", x=cap_x, y=0.0, net="+3V3"),
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LayoutPad(number="2", x=cap_x, y=0.5, net="GND"),
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],
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),
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}
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)
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def test_cap_15mm_from_2mm_rule_is_ps_plc_001():
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findings = check_placement(_graph(), _cons(2.0), _layout(15.0))
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assert len(findings) == 1
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f = findings[0]
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assert f.rule_id == "PS-PLC-001"
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assert f.source == "placement_check"
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assert f.status == "ERROR"
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assert f.net == "+3V3"
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assert "1" in (f.pins or [])
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assert f.source_page == 14
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def test_cap_1mm_is_silent():
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assert check_placement(_graph(), _cons(2.0), _layout(1.0)) == []
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def test_no_layout_graph_is_silent():
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assert check_placement(_graph(), _cons(2.0), None) == []
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def test_empty_layout_rules_skip():
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cons = {
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"UTEST": ComponentConstraints(
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mpn="UTEST",
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pintable=[Pin(number=1, name="VDD"), Pin(number=2, name="GND")],
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absolute_maximum_ratings=[], rules=[],
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layout_rules=[],
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)
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}
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assert check_placement(_graph(), cons, _layout(15.0)) == []
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def test_null_mm_uses_declared_3mm_default_as_warning():
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findings = check_placement(_graph(), _cons(None), _layout(10.0))
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assert len(findings) == 1
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assert findings[0].status == "WARNING"
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assert findings[0].rule_id == "PS-PLC-001"
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assert "3 mm" in findings[0].finding or "3 mm" in (findings[0].why or "")
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def test_no_capacitor_does_not_invent_distance():
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def test_simple_project_has_ldo_and_3v3_caps():
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g = _graph()
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g.components.pop("C1")
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g.nets["+3V3"].pins = [PinConnection(component_ref="U1", pin_number="1")]
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assert check_placement(g, _cons(2.0), _layout(15.0)) == []
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assert "U1" in g.components
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assert g.components["U1"].mpn == "SPX3819M5-L-3-3/TR"
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caps = g.capacitors_on_net("+3V3")
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assert caps, "simple_project must keep decoupling caps on +3V3"
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def test_simple_project_without_pcb_has_no_ps_plc_001():
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findings = check_placement(_graph(), {}, None)
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assert findings == []
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assert all(f.rule_id != "PS-PLC-001" for f in findings)
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def test_simple_project_eval_has_no_placement_keys():
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scores = eval_simple_project(SIMPLE)
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assert scores.finding_count == 3
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assert scores.precision == 1.0
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||||
assert scores.recall == 1.0
|
||||
assert not any(k.startswith("PS-PLC-") for k in scores.extra_keys)
|
||||
|
||||
@@ -0,0 +1,47 @@
|
||||
"""G1 SI vs simple_project — no invented millimetres or USBPHY boards.
|
||||
|
||||
Favor: real /USB.D+ and /USB.D- pair by suffix; eval stays 3 keys.
|
||||
Against: no .kicad_pcb → no PS-SI-001; 3W is not invented.
|
||||
"""
|
||||
|
||||
from __future__ import annotations
|
||||
|
||||
from pathlib import Path
|
||||
|
||||
from backend.pinscopex.eval_report import eval_simple_project
|
||||
from backend.pinscopex.models import DesignGraph
|
||||
from backend.pinscopex.si_check import check_si, partner_net
|
||||
|
||||
SIMPLE = Path(__file__).resolve().parents[1] / "simple_project"
|
||||
|
||||
|
||||
def _graph() -> DesignGraph:
|
||||
return DesignGraph.model_validate_json(
|
||||
(SIMPLE / "design_graph.json").read_text()
|
||||
)
|
||||
|
||||
|
||||
def test_simple_project_usb_dp_dm_are_a_named_pair():
|
||||
g = _graph()
|
||||
assert "/USB.D+" in g.nets
|
||||
assert "/USB.D-" in g.nets
|
||||
assert partner_net("/USB.D+") == "/USB.D-"
|
||||
assert partner_net("/USB.D-") == "/USB.D+"
|
||||
assert partner_net("/USBC.D+") == "/USBC.D-"
|
||||
|
||||
|
||||
def test_simple_project_without_pcb_has_no_ps_si_001():
|
||||
findings = check_si(_graph(), {}, None)
|
||||
assert findings == []
|
||||
assert all(f.rule_id != "PS-3W-001" for f in findings)
|
||||
|
||||
|
||||
def test_simple_project_eval_has_no_si_keys():
|
||||
scores = eval_simple_project(SIMPLE)
|
||||
assert scores.finding_count == 3
|
||||
assert scores.precision == 1.0
|
||||
assert scores.recall == 1.0
|
||||
assert not any(
|
||||
k.startswith("PS-SI-") or k.startswith("PS-3W-")
|
||||
for k in scores.extra_keys
|
||||
)
|
||||
Reference in New Issue
Block a user