Add AS4C32M16SA/SB SDRAM parts and castellated breakout footprints
- AS4C32M16SA-7TCNTR (TSOP-54) and AS4C32M16SB-7BIN (TFBGA-54) 512Mb SDRAM symbols/footprints, imported via UltraLibrarian/SnapEDA sources (see MANIFEST.csv for full provenance). - Fix Lattice LFE5U-45F-8BG381 symbol's Value/manf# grade suffix. - Import 3 castellated breakout footprints (QFP48/QFP64/SSOP8, 1.27mm castellation pitch) from coddingtonbear/kicad-castellated-breakouts into footprints/other/castellated_breakouts.pretty/, plus the upstream reference board projects under reference/ for future consultation. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01T5pjBJQ7tf9pwsSs8rG2sm
This commit is contained in:
Claude Sonnet 5
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(kicad_pcb (version 20170920) (host pcbnew "(2017-09-25 revision 6e440ff)-master")
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(general
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(thickness 1.6)
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(drawings 10)
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(tracks 32)
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(nets 1)
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)
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(page A4)
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(layers
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(0 F.Cu signal)
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(31 B.Cu signal)
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(32 B.Adhes user)
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(33 F.Adhes user)
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(34 B.Paste user)
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(35 F.Paste user)
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(36 B.SilkS user)
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(37 F.SilkS user)
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(38 B.Mask user)
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(39 F.Mask user)
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(40 Dwgs.User user)
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(41 Cmts.User user)
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(42 Eco1.User user)
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(43 Eco2.User user)
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(44 Edge.Cuts user)
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(45 Margin user)
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(46 B.CrtYd user)
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(47 F.CrtYd user)
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(48 B.Fab user)
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(49 F.Fab user)
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)
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(setup
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(outputdirectory ""))
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)
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(net 0 "")
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(uvia_drill 0.1)
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)
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(module KiCad/Housings_SSOP.pretty:SSOP-8_2.95x2.8mm_Pitch0.65mm (layer F.Cu) (tedit 5A1A1C6B) (tstamp 5A2CB6B2)
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(at 148.844 86.41)
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(descr "SSOP-8 2.9 x2.8mm Pitch 0.65mm")
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)
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(pad 8 smd rect (at 2.4 -0.975 270) (size 0.3 4.2) (layers F.Cu F.Paste F.Mask))
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(pad 7 smd rect (at 2.4 -0.325 270) (size 0.3 4.2) (layers F.Cu F.Paste F.Mask))
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(pad 6 smd rect (at 2.4 0.325 270) (size 0.3 4.2) (layers F.Cu F.Paste F.Mask))
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(pad 5 smd rect (at 2.4 0.975 270) (size 0.3 4.2) (layers F.Cu F.Paste F.Mask))
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(pad 4 smd rect (at -2.4 0.975 270) (size 0.3 4.2) (layers F.Cu F.Paste F.Mask))
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(pad 3 smd rect (at -2.4 0.325 270) (size 0.3 4.2) (layers F.Cu F.Paste F.Mask))
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(pad 2 smd rect (at -2.4 -0.325 270) (size 0.3 4.2) (layers F.Cu F.Paste F.Mask))
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(pad 1 smd rect (at -2.4 -0.975 270) (size 0.3 4.2) (layers F.Cu F.Paste F.Mask))
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)
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(gr_text "Cast. SSOP8 Breakout\n@coddingtonbear\n25 Nov 2017\n\n0.65mm Pitch\nMax 9mm Width" (at 144.0815 85.9155) (layer B.SilkS)
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(effects (font (size 0.5 0.5) (thickness 0.125)) (justify right mirror))
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)
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(gr_text SSOP8 (at 148.844 88.9) (layer F.SilkS)
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)
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(segment (start 153.597894 84.455) (end 154.305 84.455) (width 0.25) (layer F.Cu) (net 0))
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(segment (start 151.244 87.785) (end 151.724 88.265) (width 0.25) (layer F.Cu) (net 0))
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(segment (start 151.724 88.265) (end 153.597894 88.265) (width 0.25) (layer F.Cu) (net 0))
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(segment (start 153.597894 88.265) (end 154.305 88.265) (width 0.25) (layer F.Cu) (net 0))
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(segment (start 151.244 86.735) (end 154.045 86.735) (width 0.25) (layer F.Cu) (net 0))
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(segment (start 154.045 86.735) (end 154.305 86.995) (width 0.25) (layer F.Cu) (net 0))
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(segment (start 151.244 86.085) (end 153.945 86.085) (width 0.25) (layer F.Cu) (net 0))
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(segment (start 153.945 86.085) (end 154.305 85.725) (width 0.25) (layer F.Cu) (net 0))
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(via (at 143.51 84.455) (size 1) (drill 0.5) (layers F.Cu B.Cu) (net 0))
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(via (at 143.51 88.265) (size 1) (drill 0.5) (layers F.Cu B.Cu) (net 0))
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(via (at 143.51 86.995) (size 1) (drill 0.5) (layers F.Cu B.Cu) (net 0))
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(via (at 143.51 85.725) (size 1) (drill 0.5) (layers F.Cu B.Cu) (net 0))
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(via (at 154.305 84.455) (size 1) (drill 0.5) (layers F.Cu B.Cu) (net 0))
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(via (at 154.305 88.265) (size 1) (drill 0.5) (layers F.Cu B.Cu) (net 0))
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(via (at 154.305 86.995) (size 1) (drill 0.5) (layers F.Cu B.Cu) (net 0))
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(via (at 154.305 85.725) (size 1) (drill 0.5) (layers F.Cu B.Cu) (net 0))
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)
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@@ -0,0 +1,62 @@
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update=22/05/2015 07:44:53
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version=1
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last_client=kicad
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[general]
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version=1
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RootSch=
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BoardNm=
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[pcbnew]
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version=1
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LastNetListRead=
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UseCmpFile=1
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PadDrill=0.600000000000
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PadDrillOvalY=0.600000000000
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PadSizeH=1.500000000000
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PadSizeV=1.500000000000
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PcbTextSizeV=1.500000000000
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PcbTextSizeH=1.500000000000
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PcbTextThickness=0.300000000000
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ModuleTextSizeV=1.000000000000
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ModuleTextSizeH=1.000000000000
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ModuleTextSizeThickness=0.150000000000
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SolderMaskClearance=0.000000000000
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SolderMaskMinWidth=0.000000000000
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DrawSegmentWidth=0.200000000000
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BoardOutlineThickness=0.100000000000
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ModuleOutlineThickness=0.150000000000
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[cvpcb]
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version=1
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NetIExt=net
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[eeschema]
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version=1
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LibDir=
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[eeschema/libraries]
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LibName1=power
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LibName2=device
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LibName3=transistors
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LibName4=conn
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LibName5=linear
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LibName6=regul
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LibName7=74xx
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LibName8=cmos4000
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LibName9=adc-dac
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LibName10=memory
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LibName11=xilinx
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LibName12=microcontrollers
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LibName13=dsp
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LibName14=microchip
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LibName15=analog_switches
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LibName16=motorola
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LibName17=texas
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LibName18=intel
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LibName19=audio
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LibName20=interface
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LibName21=digital-audio
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LibName22=philips
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LibName23=display
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LibName24=cypress
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LibName25=siliconi
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LibName26=opto
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LibName27=atmel
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LibName28=contrib
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LibName29=valves
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