588 lines
4.5 KiB
Markdown
588 lines
4.5 KiB
Markdown
# HubAudio
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# Bus Architecture and Preliminary Pin Assignment
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**Document:** Hardware Interface Definition
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**Revision:** 0.1
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**Status:** Preliminary Design
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**Controller:** ESP32-S3
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---
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# 1. Purpose
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This document defines the preliminary hardware interfaces between the ESP32-S3 system controller and all HubAudio modules.
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The purpose is to establish:
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- bus ownership
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- GPIO allocation
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- peripheral assignment
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- boot-safe pins
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- expansion possibilities
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This document must be reviewed before PCB routing.
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---
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# 2. Design Rules
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The following rules apply:
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## Rule 1
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The ESP32-S3 controls configuration only.
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Audio data does not pass through the MCU.
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---
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## Rule 2
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All audio sources connect directly to ADAU1467.
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SOURCE
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I2S
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ADAU1467
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---
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## Rule 3
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Every external module must be identifiable.
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Identification:
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24AA025E48T-I/OT
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---
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# 3. ESP32-S3 Peripheral Allocation
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## 3.1 Overview
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| Function | Interface |
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|-|-|
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| Radio control | SPI |
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| DSP control | I2C |
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| Module EEPROM | I2C |
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| Bluetooth control | UART |
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| Debug | USB/JTAG |
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| Expansion | Reserved GPIO |
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---
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# 4. Proposed GPIO Map
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## 4.1 I2C Bus
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Shared bus:
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| Signal | ESP32-S3 GPIO | Devices |
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|-|-|-|
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| SDA | GPIO8 | EEPROM, ADAU1467 |
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| SCL | GPIO9 | EEPROM, ADAU1467 |
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Notes:
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- keep traces short
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- external pull-ups required
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- address conflicts must be checked
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---
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# 4.2 SPI Bus
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Used for radio and memories.
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| Signal | ESP32-S3 GPIO | Function |
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|-|-|-|
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| SCLK | GPIO12 | SPI Clock |
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| MOSI | GPIO11 | SPI Data |
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| MISO | GPIO13 | SPI Data |
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| CS_RADIO | GPIO10 | Si4684 |
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| CS_FLASH | GPIO14 | External memories |
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---
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# 4.3 UART Bus
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Bluetooth modules:
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## BT RX
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| Signal | GPIO |
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|-|-|
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| TX ESP32 | GPIO17 |
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| RX ESP32 | GPIO18 |
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## BT1035 TX
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Second UART:
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| Signal | GPIO |
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|-|-|
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| TX ESP32 | GPIO43 |
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| RX ESP32 | GPIO44 |
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Notes:
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ESP32-S3 provides multiple UART peripherals.
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---
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# 4.4 Module Control GPIO
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| Signal | GPIO | Function |
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|-|-|-|
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| RADIO_RESET | GPIO4 | Si4684 reset |
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| DSP_RESET | GPIO5 | ADAU1467 reset |
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| BT_RX_RESET | GPIO6 | BT receiver reset |
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| BT_TX_RESET | GPIO7 | BT1035 reset |
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---
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# 5. Si4684 Interface
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## Control
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SPI:
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ESP32-S3
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SCLK
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Si4684 CLK
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MOSI
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Si4684 SDIO
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CS
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Si4684 CS
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Control:
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GPIO4
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RESET
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Interrupt:
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Si4684 IRQ
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ESP32 GPIO
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---
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# 6. ADAU1467 Interface
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## Control Interface
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Preferred:
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I2C
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ESP32-S3
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SDA
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SCL
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ADAU1467
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Used for:
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- volume
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- routing
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- DSP parameters
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---
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# 7. Bluetooth TX Interface
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Device:
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FSC-BT1035
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## Control
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UART:
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ESP32-S3
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TX
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BT1035 RX
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ESP32-S3
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RX
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BT1035 TX
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---
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## Audio
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I2S:
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ADAU1467
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BT1035
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BCLK
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LRCLK
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DATA
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The clock direction must be verified.
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Preferred:
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ADAU1467 master.
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---
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# 8. Bluetooth RX Interface
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Device:
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FSC-BT1026 or equivalent.
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## Control
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UART:
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ESP32-S3
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BT RX Module
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---
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## Audio
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BT RX
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I2S OUT
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ADAU1467 INPUT
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---
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# 9. I2S Architecture
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## Important Design Decision
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Multiple I2S sources are not connected together.
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Wrong:
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Si4684
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BT RX
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+------ I2S ------ ADAU1467
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Correct:
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Si4684
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I2S Port 0
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ADAU1467
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BT RX
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I2S Port 1
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ADAU1467
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The ADAU1467 internal serial ports perform routing.
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---
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# 10. Proposed ADAU1467 Serial Port Allocation
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| DSP Port | Device | Direction |
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|-|-|-|
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| Serial Input 0 | Si4684 | RX |
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| Serial Input 1 | BT RX | RX |
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| Serial Output 0 | DAC | TX |
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| Serial Output 1 | BT1035 | TX |
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---
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# 11. EEPROM Bus
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All modules include:
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24AA025E48T
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Example:
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| Module | Address |
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| Main Board | 0x50 |
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| Radio | 0x51 |
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| Bluetooth | 0x52 |
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| DSP | 0x53 |
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Address selection must be verified.
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---
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# 12. Reserved Expansion Interface
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Future modules:
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Possible:
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- external DAC
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- amplifier module
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- display
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- sensors
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- remote control
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Reserved:
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SPI
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I2C
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UART
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I2S
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GPIO
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Power
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---
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# 13. Boot Safety Review
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ESP32-S3 boot pins must be checked.
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Before PCB release:
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Verify:
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- GPIO assignment
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- strapping pins
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- pull-up/pull-down resistors
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No external device must force an incorrect boot state.
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---
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# 14. Recommended Connector Between Modules
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For removable modules:
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Example:
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MODULE HEADER
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1 3.3V
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2 GND
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3 SDA
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4 SCL
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5 UART TX
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6 UART RX
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7 RESET
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8 IRQ
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9 I2S BCLK
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10 I2S LRCLK
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11 I2S DATA
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12 RESERVED
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---
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# 15. Final Review Before Schematic
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Before drawing schematic:
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Check:
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[ ] ESP32-S3 GPIO availability
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[ ] Boot strap conflicts
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[ ] I2S clock ownership
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[ ] Module power consumption
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[ ] RF placement
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[ ] EEPROM addressing
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[ ] Firmware update paths
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---
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# END |