772 lines
21 KiB
Markdown
772 lines
21 KiB
Markdown
# DigiRadio — Clock Architecture and I²S Clock-Domain Implementation
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**Document ID:** ARCH-CLOCK-001
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**Status:** Design Baseline
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**Revision:** 2.0
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**Date:** 2026-08-15
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**Scope:** ADAU1467, Si4684, ESP32-S31-WROOM3, TLV320AIC3104IRHBR, BT1035, S/PDIF
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---
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## 1. Purpose
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This document defines the DigiRadio digital-audio clock architecture and the physical implementation rules for the I²S clock signals.
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The architecture is based on the **ADAU1467** as the central DSP and audio-clock hub.
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The design objectives are:
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- one primary 12.288 MHz audio reference;
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- 48 kHz primary audio sample rate;
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- removal of the dedicated Si4684 crystal by supplying its external reference from the ADAU1467;
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- use of the TLV320AIC3104 as the analog audio codec;
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- independent BCLK/LRCLK pairs for the individual I²S interfaces;
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- no external BCLK/LRCLK splitter or "clock mixing" network;
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- explicit separation of ADAU1467 input and output clock domains;
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- use of ADAU1467 internal clock-domain architecture rather than electrically tying unrelated clock signals together.
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This document is an **implementation document**: it defines how the clock architecture shall be translated into the KiCad schematic and PCB.
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---
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# 2. Architectural Principle
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The fundamental design principle is:
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> **Each external I²S peripheral receives its own BCLK/LRCLK pair from the corresponding ADAU1467 serial-port clock domain.**
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The PCB shall **not electrically combine BCLK or LRCLK signals belonging to different serial ports**.
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The ADAU1467 internally generates and manages the required audio clock domains.
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Therefore, the PCB must not contain a global:
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```text
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BCLK ─┬─ Device 1
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├─ Device 2
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├─ Device 3
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└─ Device 4
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or:
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LRCLK ─┬─ Device 1
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├─ Device 2
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├─ Device 3
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└─ Device 4
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unless a specific group of peripherals has deliberately been assigned to the same physical clock source and the electrical topology has been explicitly designed for that purpose.
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The default DigiRadio implementation is one BCLK/LRCLK pair per I²S interface.
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3. Master Reference Clock
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3.1 Primary reference
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The DigiRadio primary audio reference is:
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12.288 MHz
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generated by a passive crystal connected to the ADAU1467 oscillator/MCLK input.
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Architecture:
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12.288 MHz crystal
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│
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▼
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ADAU1467 MCLK/XTAL
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│
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▼
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PLL
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│
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▼
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Clock Generators
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│
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├── audio clock domains
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└── CLKOUT
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The 12.288 MHz reference is appropriate for a 48 kHz audio system because:
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12.288 MHz / 256 = 48 kHz
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4. ADAU1467 Clock Architecture
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The ADAU1467 contains the clock-generation infrastructure required for a multi-peripheral audio system.
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The important architectural distinction is:
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ADAU1467 INPUT CLOCK DOMAINS
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≠
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ADAU1467 OUTPUT CLOCK DOMAINS
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Even if two domains are configured to exactly the same nominal frequency, they are not to be treated as the same physical PCB clock net.
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The ADAU1467 provides multiple serial input and output ports and multiple clock domains, allowing different peripherals to be assigned independently.
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This is the reason a separate BCLK/LRCLK splitter IC is not required by the baseline architecture.
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5. Primary Audio Rate
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The primary DigiRadio audio rate is:
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Fs = 48 kHz
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For stereo I²S with 32-bit slots:
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BCLK = 48,000 × 32 × 2
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= 3,072,000 Hz
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= 3.072 MHz
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Therefore the baseline values are:
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Signal
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Frequency
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Master reference
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12.288 MHz
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LRCLK / WCLK
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48 kHz
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BCLK
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3.072 MHz
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I²S slot width
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32 bit
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Channels
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2
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These values are the baseline. Individual devices must still be configured according to their own I²S timing and supported formats.
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6. Global Clock Tree
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The logical architecture is:
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12.288 MHz
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passive crystal
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│
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▼
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┌────────────────┐
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│ ADAU1467 │
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│ │
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│ MCLK / PLL │
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│ Clock Generators│
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│ │
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│ DSP @ 48 kHz │
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└───────┬────────┘
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│
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┌───────────────┴────────────────┐
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│ │
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▼ ▼
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CLKOUT 12.288 MHz I²S clock domains
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│ │
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┌────┴────┐ ┌──────────┼──────────┐
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│ │ │ │ │
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▼ ▼ ▼ ▼ ▼
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Si4684 AIC3104 Si4684 BT1035 Codec
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XTALI MCLK I²S IN I²S OUT I²S
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The 12.288 MHz reference and the I²S BCLK/LRCLK signals are separate functions.
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7. Si4684 Reference Clock
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7.1 External reference
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The Si4684 supports an external reference clock through XTALI.
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The DigiRadio design shall use:
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ADAU1467 CLKOUT
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│
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│ 12.288 MHz
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▼
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Si4684 XTALI
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The Si4684 shall be configured for the appropriate external-clock mode.
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The firmware configuration must explicitly set:
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XTAL_FREQ = 12,288,000 Hz
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and the correct external-clock CLK_MODE.
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The Si4684 crystal oscillator configuration parameters shall not be blindly reused for external-clock operation.
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7.2 Crystal removal
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The Si4684's dedicated crystal is therefore not part of the baseline design.
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The only primary 12.288 MHz crystal in the DigiRadio design is the one associated with the ADAU1467.
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7.3 Electrical validation
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Before schematic/PCB freeze, verify:
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• ADAU1467 CLKOUT output level;
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• Si4684 XTALI input limits;
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• frequency;
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• duty cycle;
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• rise/fall time;
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• startup sequence;
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• signal integrity;
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• routing noise coupling.
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8. Si4684 I²S Input
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The Si4684 audio data enters the ADAU1467.
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Baseline:
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Si4684 ADAU1467
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DOUT ──────────────────────► Serial IN
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BCLK ◄────────────────────── Serial IN clock
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LRCLK ◄────────────────────── Serial IN frame clock
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The Si4684 is configured as an I²S slave.
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The BCLK/LRCLK pair used by the Si4684 belongs to the selected ADAU1467 input clock domain.
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It shall not be physically connected to the BCLK/LRCLK pair used by an ADAU1467 output port merely because both operate at 48 kHz.
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9. ESP32-S31-WROOM3 I²S Input
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The ESP32 audio stream enters the ADAU1467.
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Preferred configuration:
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ADAU1467 = I²S clock master
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ESP32 = I²S clock slave
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Physical connection:
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ESP32 DATA ─────────────────► ADAU1467 Serial IN
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ADAU1467 BCLK_x ────────────► ESP32 BCLK
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ADAU1467 LRCLK_x ───────────► ESP32 LRCLK
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The ESP32 BCLK/LRCLK pair is a dedicated clock pair for that serial interface.
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It is not to be joined to the Si4684 BCLK/LRCLK pair on the PCB.
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The final ESP32 firmware shall use:
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Fs = 48 kHz
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slot width = 32 bit
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I²S slave mode
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where supported by the selected ESP32 I²S implementation.
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10. TLV320AIC3104 Codec
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The codec is:
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TLV320AIC3104IRHBR
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It provides:
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• stereo ADC;
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• stereo DAC;
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• Line In;
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• Line Out;
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• headphone output path;
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• digital I²S interface;
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• internal clock/PLL circuitry.
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11. Codec MCLK
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The codec can use the same 12.288 MHz clock reference.
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Preferred connection:
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ADAU1467 CLKOUT
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│
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│ 12.288 MHz
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▼
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TLV320AIC3104 MCLK
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At 48 kHz:
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12.288 MHz / 256 = 48 kHz
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This provides a clean and deterministic clock relationship between the ADAU1467 and codec.
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The codec's PLL/divider configuration must be programmed according to the TLV320AIC3104 datasheet.
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12. Codec ADC — Line In to ADAU1467
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The analog input path is:
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LINE IN
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│
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▼
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TLV320AIC3104 ADC
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│
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│ DOUT
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▼
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ADAU1467 Serial IN
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The digital clock connection is:
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ADAU1467 BCLK_CODEC_IN
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│
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└──────────────► AIC3104 BCLK
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ADAU1467 LRCLK_CODEC_IN
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│
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└──────────────► AIC3104 WCLK/LRCLK
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and:
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AIC3104 DOUT ─────────► ADAU1467 Serial IN
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The codec ADC interface is therefore an ADAU1467 input serial port.
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13. Codec DAC — ADAU1467 to Line Out / Headphone
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The output path is:
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ADAU1467 Serial OUT
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│
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│ DIN
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▼
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TLV320AIC3104 DAC
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│
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├──► LINE OUT
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│
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└──► HEADPHONE AMPLIFIER
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│
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▼
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Headphone Jack
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Clocking:
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ADAU1467 BCLK_CODEC_OUT
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│
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└──────────────► AIC3104 BCLK
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ADAU1467 LRCLK_CODEC_OUT
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│
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└──────────────► AIC3104 WCLK/LRCLK
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Data:
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ADAU1467 Serial OUT DATA ──► AIC3104 DIN
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The codec output clock pair is a dedicated ADAU1467 output clock-domain pair.
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14. Important: Codec Input and Output Clocks
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Even though the codec ADC and DAC operate at the same nominal:
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48 kHz / 3.072 MHz
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the schematic shall not assume that the codec ADC and DAC automatically share one physical BCLK/LRCLK net.
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The preferred implementation is:
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ADAU1467 INPUT CLOCK DOMAIN
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│
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├── BCLK_CODEC_IN
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└── LRCLK_CODEC_IN
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│
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▼
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AIC3104 ADC
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ADAU1467 OUTPUT CLOCK DOMAIN
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│
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├── BCLK_CODEC_OUT
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└── LRCLK_CODEC_OUT
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│
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▼
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AIC3104 DAC
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Whether the final AIC3104 implementation can safely use one common physical clock pair for both directions is a specific codec-interface configuration decision and must be made from the TLV320AIC3104 timing/master/slave requirements.
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The architecture does not require us to tie the two domains together.
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15. BT1035
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The BT1035 is an I²S output peripheral.
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Preferred configuration:
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ADAU1467 = I²S master
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BT1035 = I²S slave
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Physical connections:
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ADAU1467 BCLK_BT
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└──────────────► BT1035 BCLK
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ADAU1467 LRCLK_BT
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└──────────────► BT1035 LRCLK
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ADAU1467 DATA_BT
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└──────────────► BT1035 I²S DATA
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Baseline:
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48 kHz
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32 bit
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BCLK = 3.072 MHz
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The BT1035 interface is an ADAU1467 output clock domain.
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It shall not share a PCB BCLK/LRCLK net with the codec unless deliberately configured and electrically verified.
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16. S/PDIF Input
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S/PDIF is handled by the dedicated ADAU1467 S/PDIF input.
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S/PDIF IN
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│
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▼
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ADAU1467 S/PDIF RX
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│
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▼
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ASRC / DSP clock domain
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There is no external BCLK/LRCLK connection.
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The recovered S/PDIF clock is not physically combined with the I²S clock network.
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17. S/PDIF Output
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Likewise:
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ADAU1467 S/PDIF TX
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│
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▼
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S/PDIF OUT
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No external BCLK/LRCLK is required.
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18. Clock-Domain Allocation
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The following is the proposed logical allocation.
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Input side
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Device
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ADAU interface
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Clock ownership
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Si4684
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Serial IN 0
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ADAU1467 input clock domain
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ESP32-S31-WROOM3
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Serial IN 1
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ADAU1467 input clock domain
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AIC3104 ADC
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Serial IN 2
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ADAU1467 input clock domain
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S/PDIF
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Dedicated S/PDIF IN
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Recovered S/PDIF clock / ASRC
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Output side
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Device
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ADAU interface
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Clock ownership
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BT1035
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Serial OUT 0
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ADAU1467 output clock domain
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AIC3104 DAC
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Serial OUT 1
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ADAU1467 output clock domain
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S/PDIF
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Dedicated S/PDIF OUT
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ADAU1467 S/PDIF subsystem
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The exact serial-port numbers are implementation assignments and shall be finalized against the ADAU1467 pinout and PCB placement.
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19. No Clock "Mishmash"
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The following shall be considered a design rule:
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Do not electrically connect unrelated BCLK or LRCLK signals merely because they have the same frequency.
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For example, these are logically different:
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BCLK_SI4684
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BCLK_ESP32
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BCLK_CODEC_IN
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BCLK_BT
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BCLK_CODEC_OUT
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Even if all are:
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3.072 MHz
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they are separate clock nets.
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Likewise:
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LRCLK_SI4684
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LRCLK_ESP32
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LRCLK_CODEC_IN
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LRCLK_BT
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LRCLK_CODEC_OUT
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remain separate nets.
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This provides:
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• deterministic ownership;
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• no contention between clock drivers;
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• cleaner PCB routing;
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• easier debugging;
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• easier clock-domain changes;
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• easier future support for different sample rates.
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20. Internal ADAU1467 Clock Relationship
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The important distinction is:
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PHYSICAL PCB CONNECTION
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≠
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LOGICAL CLOCK RELATIONSHIP
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The ADAU1467 can derive several clock domains from the same master reference.
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Therefore:
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BCLK_A = 3.072 MHz
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BCLK_B = 3.072 MHz
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BCLK_C = 3.072 MHz
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does not imply:
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BCLK_A = physical net BCLK_B = physical net BCLK_C
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They are independently generated/assigned clock-domain signals.
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The synchronization relationship is established by the ADAU1467 clock-generation architecture.
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21. PCB Net Naming
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The schematic shall use explicit net names.
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Recommended names:
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MCLK_12M288
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SI4684_BCLK
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SI4684_LRCLK
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SI4684_SDOUT
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ESP32_BCLK
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ESP32_LRCLK
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ESP32_SDOUT
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CODEC_ADC_BCLK
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CODEC_ADC_LRCLK
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CODEC_ADC_SDOUT
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BT_BCLK
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BT_LRCLK
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BT_SDIN
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CODEC_DAC_BCLK
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CODEC_DAC_LRCLK
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CODEC_DAC_SDIN
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SPDIF_IN
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SPDIF_OUT
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Do not use a generic:
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BCLK
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LRCLK
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label for the entire board unless that net is intentionally a single shared physical clock.
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22. PCB Routing Rules
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22.1 MCLK_12M288
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Route:
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ADAU1467 CLKOUT
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│
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├──► Si4684 XTALI
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└──► AIC3104 MCLK
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The two loads may be fed from the same source only after checking the ADAU1467 CLKOUT drive capability and total input capacitance.
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Keep the clock routes short and away from switching-regulator nodes.
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22.2 BCLK/LRCLK
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Each clock pair shall be routed independently:
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ADAU1467
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│
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├── SI4684_BCLK / LRCLK
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│
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├── ESP32_BCLK / LRCLK
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│
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├── CODEC_ADC_BCLK / LRCLK
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│
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├── BT_BCLK / LRCLK
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│
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└── CODEC_DAC_BCLK / LRCLK
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Avoid unnecessary stubs.
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Use source termination if required by signal-integrity analysis.
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23. Why No External Clock Splitter?
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A clock splitter is not required simply because several peripherals use 48 kHz.
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The ADAU1467 already provides the required clock-generation architecture.
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Adding an external clock splitter would introduce:
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• another active clock component;
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• additional propagation delay;
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• additional jitter;
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• additional power consumption;
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• another configuration dependency;
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• another possible failure point.
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It should therefore be added only if electrical analysis proves that a specific fanout requirement cannot be met by the ADAU1467 clock outputs.
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24. Why Not Share BCLK/LRCLK Everywhere?
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Sharing clock signals is technically possible in some I²S designs, but it is not the baseline DigiRadio architecture.
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The risks of indiscriminate sharing are:
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• conflicting clock drivers;
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• accidental master/master configuration;
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• long PCB branches;
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• uncontrolled stubs;
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• difficult debugging;
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• inability to independently change one interface;
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• confusion between ADAU input and output clock domains.
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The ADAU1467 gives us enough clock-domain infrastructure to avoid these problems.
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Therefore the design deliberately favors independent clock pairs.
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25. Master/Slave Policy
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The baseline policy is:
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Device
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I²S role
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||
ADAU1467
|
||
Master
|
||
Si4684
|
||
Slave
|
||
ESP32-S31-WROOM3
|
||
Slave
|
||
TLV320AIC3104
|
||
Slave where supported/configured
|
||
BT1035
|
||
Slave
|
||
This avoids multiple external clock masters.
|
||
Any deviation must be documented as an explicit architecture change.
|
||
|
||
26. Sample-Rate Conversion
|
||
If an external source operates at a sample rate different from 48 kHz:
|
||
|
||
|
||
External clock domain
|
||
│
|
||
▼
|
||
ADAU1467 Serial Port
|
||
│
|
||
▼
|
||
ASRC
|
||
│
|
||
▼
|
||
48 kHz DSP domain
|
||
|
||
The external BCLK/LRCLK must remain local to that interface.
|
||
It shall not be forced onto the main 48 kHz clock net.
|
||
|
||
27. Final Logical Architecture
|
||
|
||
|
||
12.288 MHz
|
||
ADAU CRYSTAL
|
||
│
|
||
▼
|
||
┌───────────────┐
|
||
│ ADAU1467 │
|
||
│ │
|
||
│ PLL │
|
||
│ Clock Gen. │
|
||
│ DSP │
|
||
└───────┬───────┘
|
||
│
|
||
┌──────────────┼───────────────┐
|
||
│ │ │
|
||
▼ ▼ ▼
|
||
CLKOUT INPUT DOMAINS OUTPUT DOMAINS
|
||
12.288 MHz │ │
|
||
│ │ │
|
||
┌─────┴─────┐ │ ┌────┼─────┐
|
||
│ │ │ │ │
|
||
▼ ▼ ▼ ▼ ▼
|
||
Si4684 AIC3104 Si4684 BT1035 AIC3104
|
||
XTALI MCLK I²S IN I²S OUT I²S OUT
|
||
▲ │ │
|
||
│ │ │
|
||
ESP32 I²S BCLK/LR BCLK/LR
|
||
▲
|
||
│
|
||
ESP32 DATA
|
||
|
||
S/PDIF remains on the dedicated ADAU1467 interfaces.
|
||
|
||
28. Implementation Sequence
|
||
The schematic implementation shall proceed in this order:
|
||
1 Place ADAU1467.
|
||
2 Place the 12.288 MHz crystal and its oscillator network.
|
||
3 Define ADAU1467 PLL and clock-generator configuration.
|
||
4 Define serial input clock domains.
|
||
5 Assign Si4684 to an input serial port.
|
||
6 Assign ESP32 to an input serial port.
|
||
7 Assign AIC3104 ADC to an input serial port.
|
||
8 Define output clock domains.
|
||
9 Assign BT1035 to an output serial port.
|
||
10 Assign AIC3104 DAC to an output serial port.
|
||
11 Connect ADAU1467 CLKOUT to Si4684 XTALI.
|
||
12 Connect ADAU1467 CLKOUT to AIC3104 MCLK if the final loading analysis permits.
|
||
13 Route every BCLK/LRCLK pair as a separate named net.
|
||
14 Verify that no two clock outputs are accidentally shorted.
|
||
15 Verify all master/slave settings.
|
||
16 Verify SigmaStudio serial-port and clock-domain assignments against the schematic.
|
||
17 Perform signal-integrity review before PCB release.
|
||
|
||
29. Verification Checklist
|
||
Master clock
|
||
• 12.288 MHz crystal connected to ADAU1467.
|
||
• ADAU1467 PLL configuration verified.
|
||
• 12.288 MHz CLKOUT configuration verified.
|
||
• CLKOUT loading verified.
|
||
Si4684
|
||
• Dedicated crystal removed.
|
||
• XTALI driven from ADAU1467 CLKOUT.
|
||
• External-clock mode configured.
|
||
• XTAL_FREQ = 12,288,000 Hz.
|
||
• I²S slave mode configured.
|
||
• Dedicated SI4684_BCLK net.
|
||
• Dedicated SI4684_LRCLK net.
|
||
ESP32
|
||
• I²S slave mode verified.
|
||
• Dedicated ESP32_BCLK net.
|
||
• Dedicated ESP32_LRCLK net.
|
||
• 48 kHz / selected slot format verified.
|
||
TLV320AIC3104
|
||
• MCLK = 12.288 MHz verified.
|
||
• ADC serial input assigned.
|
||
• DAC serial output assigned.
|
||
• Master/slave mode verified.
|
||
• ADC BCLK/LRCLK routing verified.
|
||
• DAC BCLK/LRCLK routing verified.
|
||
• Headphone path verified.
|
||
BT1035
|
||
• I²S slave mode verified.
|
||
• 48 kHz / 32-bit configuration verified.
|
||
• Dedicated BT_BCLK.
|
||
• Dedicated BT_LRCLK.
|
||
S/PDIF
|
||
• Dedicated ADAU1467 S/PDIF IN.
|
||
• Dedicated ADAU1467 S/PDIF OUT.
|
||
• No BCLK/LRCLK connection required.
|
||
PCB
|
||
• No unintended common BCLK net.
|
||
• No unintended common LRCLK net.
|
||
• No master/master connection.
|
||
• Clock routes kept short.
|
||
• Switching-node coupling checked.
|
||
• Signal integrity checked.
|
||
|
||
30. Design Decision
|
||
The DigiRadio clock architecture is therefore based on the following definitive principles:
|
||
1 One primary 12.288 MHz crystal on the ADAU1467.
|
||
2 ADAU1467 is the central audio clock master.
|
||
3 Main audio rate is 48 kHz.
|
||
4 Baseline I²S BCLK is 3.072 MHz for stereo 32-bit slots.
|
||
5 Si4684 receives 12.288 MHz externally from ADAU1467 CLKOUT.
|
||
6 The Si4684 dedicated crystal is removed.
|
||
7 TLV320AIC3104 may receive the same 12.288 MHz master reference on MCLK.
|
||
8 Each I²S peripheral receives its own BCLK/LRCLK pair.
|
||
9 Input and output ADAU1467 clock domains are treated as distinct.
|
||
10 BCLK/LRCLK signals are not electrically mixed on the PCB.
|
||
11 No generic BCLK/LRCLK splitter is required by the architecture.
|
||
12 S/PDIF uses the dedicated ADAU1467 interfaces.
|
||
13 ASRC is used when an external source belongs to an incompatible/asynchronous clock domain.
|
||
14 All clock-domain assignments must be explicitly reflected in both SigmaStudio and KiCad.
|
||
|
||
31. References
|
||
Primary references to be kept with the DigiRadio repository:
|
||
• Analog Devices — ADAU1463/ADAU1467 Data Sheet.
|
||
• Analog Devices — ADAU1467 product and evaluation-board documentation.
|
||
• Silicon Labs — Si468x Receiver Programming Guide (AN649).
|
||
• Silicon Labs — Si4684 hardware/reference documentation.
|
||
• Texas Instruments — TLV320AIC3104 Data Sheet.
|
||
• Feasycom — BT1035 Programming User Guide.
|
||
• DigiRadio SigmaStudio project and generated DSP configuration.
|
||
Vendor documents stored in the repository shall be treated as the implementation references. If a newer revision is added, this architecture document shall be reviewed before schematic freeze.
|