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# DigiRadio — Clock Architecture and I²S Clock-Domain Implementation
**Document ID:** ARCH-CLOCK-001
**Status:** Design Baseline
**Revision:** 2.0
**Date:** 2026-08-15
**Scope:** ADAU1467, Si4684, ESP32-S31-WROOM3, TLV320AIC3104IRHBR, BT1035, S/PDIF
---
## 1. Purpose
This document defines the DigiRadio digital-audio clock architecture and the physical implementation rules for the I²S clock signals.
The architecture is based on the **ADAU1467** as the central DSP and audio-clock hub.
The design objectives are:
- one primary 12.288 MHz audio reference;
- 48 kHz primary audio sample rate;
- removal of the dedicated Si4684 crystal by supplying its external reference from the ADAU1467;
- use of the TLV320AIC3104 as the analog audio codec;
- independent BCLK/LRCLK pairs for the individual I²S interfaces;
- no external BCLK/LRCLK splitter or "clock mixing" network;
- explicit separation of ADAU1467 input and output clock domains;
- use of ADAU1467 internal clock-domain architecture rather than electrically tying unrelated clock signals together.
This document is an **implementation document**: it defines how the clock architecture shall be translated into the KiCad schematic and PCB.
---
# 2. Architectural Principle
The fundamental design principle is:
> **Each external I²S peripheral receives its own BCLK/LRCLK pair from the corresponding ADAU1467 serial-port clock domain.**
The PCB shall **not electrically combine BCLK or LRCLK signals belonging to different serial ports**.
The ADAU1467 internally generates and manages the required audio clock domains.
Therefore, the PCB must not contain a global:
```text
BCLK ─┬─ Device 1
├─ Device 2
├─ Device 3
└─ Device 4
or:
LRCLK ─┬─ Device 1
├─ Device 2
├─ Device 3
└─ Device 4
unless a specific group of peripherals has deliberately been assigned to the same physical clock source and the electrical topology has been explicitly designed for that purpose.
The default DigiRadio implementation is one BCLK/LRCLK pair per I²S interface.
3. Master Reference Clock
3.1 Primary reference
The DigiRadio primary audio reference is:
12.288 MHz
generated by a passive crystal connected to the ADAU1467 oscillator/MCLK input.
Architecture:
12.288 MHz crystal
│
▼
ADAU1467 MCLK/XTAL
│
▼
PLL
│
▼
Clock Generators
│
├── audio clock domains
└── CLKOUT
The 12.288 MHz reference is appropriate for a 48 kHz audio system because:
12.288 MHz / 256 = 48 kHz
4. ADAU1467 Clock Architecture
The ADAU1467 contains the clock-generation infrastructure required for a multi-peripheral audio system.
The important architectural distinction is:
ADAU1467 INPUT CLOCK DOMAINS
≠
ADAU1467 OUTPUT CLOCK DOMAINS
Even if two domains are configured to exactly the same nominal frequency, they are not to be treated as the same physical PCB clock net.
The ADAU1467 provides multiple serial input and output ports and multiple clock domains, allowing different peripherals to be assigned independently.
This is the reason a separate BCLK/LRCLK splitter IC is not required by the baseline architecture.
5. Primary Audio Rate
The primary DigiRadio audio rate is:
Fs = 48 kHz
For stereo I²S with 32-bit slots:
BCLK = 48,000 × 32 × 2
= 3,072,000 Hz
= 3.072 MHz
Therefore the baseline values are:
Signal
Frequency
Master reference
12.288 MHz
LRCLK / WCLK
48 kHz
BCLK
3.072 MHz
I²S slot width
32 bit
Channels
2
These values are the baseline. Individual devices must still be configured according to their own I²S timing and supported formats.
6. Global Clock Tree
The logical architecture is:
12.288 MHz
passive crystal
│
▼
┌────────────────┐
│ ADAU1467 │
│ │
│ MCLK / PLL │
│ Clock Generators│
│ │
│ DSP @ 48 kHz │
└───────┬────────┘
│
┌───────────────┴────────────────┐
│ │
▼ ▼
CLKOUT 12.288 MHz I²S clock domains
│ │
┌────┴────┐ ┌──────────┼──────────┐
│ │ │ │ │
▼ ▼ ▼ ▼ ▼
Si4684 AIC3104 Si4684 BT1035 Codec
XTALI MCLK I²S IN I²S OUT I²S
The 12.288 MHz reference and the I²S BCLK/LRCLK signals are separate functions.
7. Si4684 Reference Clock
7.1 External reference
The Si4684 supports an external reference clock through XTALI.
The DigiRadio design shall use:
ADAU1467 CLKOUT
│
│ 12.288 MHz
▼
Si4684 XTALI
The Si4684 shall be configured for the appropriate external-clock mode.
The firmware configuration must explicitly set:
XTAL_FREQ = 12,288,000 Hz
and the correct external-clock CLK_MODE.
The Si4684 crystal oscillator configuration parameters shall not be blindly reused for external-clock operation.
7.2 Crystal removal
The Si4684's dedicated crystal is therefore not part of the baseline design.
The only primary 12.288 MHz crystal in the DigiRadio design is the one associated with the ADAU1467.
7.3 Electrical validation
Before schematic/PCB freeze, verify:
• ADAU1467 CLKOUT output level;
• Si4684 XTALI input limits;
• frequency;
• duty cycle;
• rise/fall time;
• startup sequence;
• signal integrity;
• routing noise coupling.
8. Si4684 I²S Input
The Si4684 audio data enters the ADAU1467.
Baseline:
Si4684 ADAU1467
DOUT ──────────────────────► Serial IN
BCLK ◄────────────────────── Serial IN clock
LRCLK ◄────────────────────── Serial IN frame clock
The Si4684 is configured as an I²S slave.
The BCLK/LRCLK pair used by the Si4684 belongs to the selected ADAU1467 input clock domain.
It shall not be physically connected to the BCLK/LRCLK pair used by an ADAU1467 output port merely because both operate at 48 kHz.
9. ESP32-S31-WROOM3 I²S Input
The ESP32 audio stream enters the ADAU1467.
Preferred configuration:
ADAU1467 = I²S clock master
ESP32 = I²S clock slave
Physical connection:
ESP32 DATA ─────────────────► ADAU1467 Serial IN
ADAU1467 BCLK_x ────────────► ESP32 BCLK
ADAU1467 LRCLK_x ───────────► ESP32 LRCLK
The ESP32 BCLK/LRCLK pair is a dedicated clock pair for that serial interface.
It is not to be joined to the Si4684 BCLK/LRCLK pair on the PCB.
The final ESP32 firmware shall use:
Fs = 48 kHz
slot width = 32 bit
I²S slave mode
where supported by the selected ESP32 I²S implementation.
10. TLV320AIC3104 Codec
The codec is:
TLV320AIC3104IRHBR
It provides:
• stereo ADC;
• stereo DAC;
• Line In;
• Line Out;
• headphone output path;
• digital I²S interface;
• internal clock/PLL circuitry.
11. Codec MCLK
The codec can use the same 12.288 MHz clock reference.
Preferred connection:
ADAU1467 CLKOUT
│
│ 12.288 MHz
▼
TLV320AIC3104 MCLK
At 48 kHz:
12.288 MHz / 256 = 48 kHz
This provides a clean and deterministic clock relationship between the ADAU1467 and codec.
The codec's PLL/divider configuration must be programmed according to the TLV320AIC3104 datasheet.
12. Codec ADC — Line In to ADAU1467
The analog input path is:
LINE IN
│
▼
TLV320AIC3104 ADC
│
│ DOUT
▼
ADAU1467 Serial IN
The digital clock connection is:
ADAU1467 BCLK_CODEC_IN
│
└──────────────► AIC3104 BCLK
ADAU1467 LRCLK_CODEC_IN
│
└──────────────► AIC3104 WCLK/LRCLK
and:
AIC3104 DOUT ─────────► ADAU1467 Serial IN
The codec ADC interface is therefore an ADAU1467 input serial port.
13. Codec DAC — ADAU1467 to Line Out / Headphone
The output path is:
ADAU1467 Serial OUT
│
│ DIN
▼
TLV320AIC3104 DAC
│
├──► LINE OUT
│
└──► HEADPHONE AMPLIFIER
│
▼
Headphone Jack
Clocking:
ADAU1467 BCLK_CODEC_OUT
│
└──────────────► AIC3104 BCLK
ADAU1467 LRCLK_CODEC_OUT
│
└──────────────► AIC3104 WCLK/LRCLK
Data:
ADAU1467 Serial OUT DATA ──► AIC3104 DIN
The codec output clock pair is a dedicated ADAU1467 output clock-domain pair.
14. Important: Codec Input and Output Clocks
Even though the codec ADC and DAC operate at the same nominal:
48 kHz / 3.072 MHz
the schematic shall not assume that the codec ADC and DAC automatically share one physical BCLK/LRCLK net.
The preferred implementation is:
ADAU1467 INPUT CLOCK DOMAIN
│
├── BCLK_CODEC_IN
└── LRCLK_CODEC_IN
│
▼
AIC3104 ADC
ADAU1467 OUTPUT CLOCK DOMAIN
│
├── BCLK_CODEC_OUT
└── LRCLK_CODEC_OUT
│
▼
AIC3104 DAC
Whether the final AIC3104 implementation can safely use one common physical clock pair for both directions is a specific codec-interface configuration decision and must be made from the TLV320AIC3104 timing/master/slave requirements.
The architecture does not require us to tie the two domains together.
15. BT1035
The BT1035 is an I²S output peripheral.
Preferred configuration:
ADAU1467 = I²S master
BT1035 = I²S slave
Physical connections:
ADAU1467 BCLK_BT
└──────────────► BT1035 BCLK
ADAU1467 LRCLK_BT
└──────────────► BT1035 LRCLK
ADAU1467 DATA_BT
└──────────────► BT1035 I²S DATA
Baseline:
48 kHz
32 bit
BCLK = 3.072 MHz
The BT1035 interface is an ADAU1467 output clock domain.
It shall not share a PCB BCLK/LRCLK net with the codec unless deliberately configured and electrically verified.
16. S/PDIF Input
S/PDIF is handled by the dedicated ADAU1467 S/PDIF input.
S/PDIF IN
│
▼
ADAU1467 S/PDIF RX
│
▼
ASRC / DSP clock domain
There is no external BCLK/LRCLK connection.
The recovered S/PDIF clock is not physically combined with the I²S clock network.
17. S/PDIF Output
Likewise:
ADAU1467 S/PDIF TX
│
▼
S/PDIF OUT
No external BCLK/LRCLK is required.
18. Clock-Domain Allocation
The following is the proposed logical allocation.
Input side
Device
ADAU interface
Clock ownership
Si4684
Serial IN 0
ADAU1467 input clock domain
ESP32-S31-WROOM3
Serial IN 1
ADAU1467 input clock domain
AIC3104 ADC
Serial IN 2
ADAU1467 input clock domain
S/PDIF
Dedicated S/PDIF IN
Recovered S/PDIF clock / ASRC
Output side
Device
ADAU interface
Clock ownership
BT1035
Serial OUT 0
ADAU1467 output clock domain
AIC3104 DAC
Serial OUT 1
ADAU1467 output clock domain
S/PDIF
Dedicated S/PDIF OUT
ADAU1467 S/PDIF subsystem
The exact serial-port numbers are implementation assignments and shall be finalized against the ADAU1467 pinout and PCB placement.
19. No Clock "Mishmash"
The following shall be considered a design rule:
Do not electrically connect unrelated BCLK or LRCLK signals merely because they have the same frequency.
For example, these are logically different:
BCLK_SI4684
BCLK_ESP32
BCLK_CODEC_IN
BCLK_BT
BCLK_CODEC_OUT
Even if all are:
3.072 MHz
they are separate clock nets.
Likewise:
LRCLK_SI4684
LRCLK_ESP32
LRCLK_CODEC_IN
LRCLK_BT
LRCLK_CODEC_OUT
remain separate nets.
This provides:
• deterministic ownership;
• no contention between clock drivers;
• cleaner PCB routing;
• easier debugging;
• easier clock-domain changes;
• easier future support for different sample rates.
20. Internal ADAU1467 Clock Relationship
The important distinction is:
PHYSICAL PCB CONNECTION
≠
LOGICAL CLOCK RELATIONSHIP
The ADAU1467 can derive several clock domains from the same master reference.
Therefore:
BCLK_A = 3.072 MHz
BCLK_B = 3.072 MHz
BCLK_C = 3.072 MHz
does not imply:
BCLK_A = physical net BCLK_B = physical net BCLK_C
They are independently generated/assigned clock-domain signals.
The synchronization relationship is established by the ADAU1467 clock-generation architecture.
21. PCB Net Naming
The schematic shall use explicit net names.
Recommended names:
MCLK_12M288
SI4684_BCLK
SI4684_LRCLK
SI4684_SDOUT
ESP32_BCLK
ESP32_LRCLK
ESP32_SDOUT
CODEC_ADC_BCLK
CODEC_ADC_LRCLK
CODEC_ADC_SDOUT
BT_BCLK
BT_LRCLK
BT_SDIN
CODEC_DAC_BCLK
CODEC_DAC_LRCLK
CODEC_DAC_SDIN
SPDIF_IN
SPDIF_OUT
Do not use a generic:
BCLK
LRCLK
label for the entire board unless that net is intentionally a single shared physical clock.
22. PCB Routing Rules
22.1 MCLK_12M288
Route:
ADAU1467 CLKOUT
│
├──► Si4684 XTALI
└──► AIC3104 MCLK
The two loads may be fed from the same source only after checking the ADAU1467 CLKOUT drive capability and total input capacitance.
Keep the clock routes short and away from switching-regulator nodes.
22.2 BCLK/LRCLK
Each clock pair shall be routed independently:
ADAU1467
│
├── SI4684_BCLK / LRCLK
│
├── ESP32_BCLK / LRCLK
│
├── CODEC_ADC_BCLK / LRCLK
│
├── BT_BCLK / LRCLK
│
└── CODEC_DAC_BCLK / LRCLK
Avoid unnecessary stubs.
Use source termination if required by signal-integrity analysis.
23. Why No External Clock Splitter?
A clock splitter is not required simply because several peripherals use 48 kHz.
The ADAU1467 already provides the required clock-generation architecture.
Adding an external clock splitter would introduce:
• another active clock component;
• additional propagation delay;
• additional jitter;
• additional power consumption;
• another configuration dependency;
• another possible failure point.
It should therefore be added only if electrical analysis proves that a specific fanout requirement cannot be met by the ADAU1467 clock outputs.
24. Why Not Share BCLK/LRCLK Everywhere?
Sharing clock signals is technically possible in some I²S designs, but it is not the baseline DigiRadio architecture.
The risks of indiscriminate sharing are:
• conflicting clock drivers;
• accidental master/master configuration;
• long PCB branches;
• uncontrolled stubs;
• difficult debugging;
• inability to independently change one interface;
• confusion between ADAU input and output clock domains.
The ADAU1467 gives us enough clock-domain infrastructure to avoid these problems.
Therefore the design deliberately favors independent clock pairs.
25. Master/Slave Policy
The baseline policy is:
Device
I²S role
ADAU1467
Master
Si4684
Slave
ESP32-S31-WROOM3
Slave
TLV320AIC3104
Slave where supported/configured
BT1035
Slave
This avoids multiple external clock masters.
Any deviation must be documented as an explicit architecture change.
26. Sample-Rate Conversion
If an external source operates at a sample rate different from 48 kHz:
External clock domain
│
▼
ADAU1467 Serial Port
│
▼
ASRC
│
▼
48 kHz DSP domain
The external BCLK/LRCLK must remain local to that interface.
It shall not be forced onto the main 48 kHz clock net.
27. Final Logical Architecture
12.288 MHz
ADAU CRYSTAL
│
▼
┌───────────────┐
│ ADAU1467 │
│ │
│ PLL │
│ Clock Gen. │
│ DSP │
└───────┬───────┘
│
┌──────────────┼───────────────┐
│ │ │
▼ ▼ ▼
CLKOUT INPUT DOMAINS OUTPUT DOMAINS
12.288 MHz │ │
│ │ │
┌─────┴─────┐ │ ┌────┼─────┐
│ │ │ │ │
▼ ▼ ▼ ▼ ▼
Si4684 AIC3104 Si4684 BT1035 AIC3104
XTALI MCLK I²S IN I²S OUT I²S OUT
▲ │ │
│ │ │
ESP32 I²S BCLK/LR BCLK/LR
▲
│
ESP32 DATA
S/PDIF remains on the dedicated ADAU1467 interfaces.
28. Implementation Sequence
The schematic implementation shall proceed in this order:
1 Place ADAU1467.
2 Place the 12.288 MHz crystal and its oscillator network.
3 Define ADAU1467 PLL and clock-generator configuration.
4 Define serial input clock domains.
5 Assign Si4684 to an input serial port.
6 Assign ESP32 to an input serial port.
7 Assign AIC3104 ADC to an input serial port.
8 Define output clock domains.
9 Assign BT1035 to an output serial port.
10 Assign AIC3104 DAC to an output serial port.
11 Connect ADAU1467 CLKOUT to Si4684 XTALI.
12 Connect ADAU1467 CLKOUT to AIC3104 MCLK if the final loading analysis permits.
13 Route every BCLK/LRCLK pair as a separate named net.
14 Verify that no two clock outputs are accidentally shorted.
15 Verify all master/slave settings.
16 Verify SigmaStudio serial-port and clock-domain assignments against the schematic.
17 Perform signal-integrity review before PCB release.
29. Verification Checklist
Master clock
• 12.288 MHz crystal connected to ADAU1467.
• ADAU1467 PLL configuration verified.
• 12.288 MHz CLKOUT configuration verified.
• CLKOUT loading verified.
Si4684
• Dedicated crystal removed.
• XTALI driven from ADAU1467 CLKOUT.
• External-clock mode configured.
• XTAL_FREQ = 12,288,000 Hz.
• I²S slave mode configured.
• Dedicated SI4684_BCLK net.
• Dedicated SI4684_LRCLK net.
ESP32
• I²S slave mode verified.
• Dedicated ESP32_BCLK net.
• Dedicated ESP32_LRCLK net.
• 48 kHz / selected slot format verified.
TLV320AIC3104
• MCLK = 12.288 MHz verified.
• ADC serial input assigned.
• DAC serial output assigned.
• Master/slave mode verified.
• ADC BCLK/LRCLK routing verified.
• DAC BCLK/LRCLK routing verified.
• Headphone path verified.
BT1035
• I²S slave mode verified.
• 48 kHz / 32-bit configuration verified.
• Dedicated BT_BCLK.
• Dedicated BT_LRCLK.
S/PDIF
• Dedicated ADAU1467 S/PDIF IN.
• Dedicated ADAU1467 S/PDIF OUT.
• No BCLK/LRCLK connection required.
PCB
• No unintended common BCLK net.
• No unintended common LRCLK net.
• No master/master connection.
• Clock routes kept short.
• Switching-node coupling checked.
• Signal integrity checked.
30. Design Decision
The DigiRadio clock architecture is therefore based on the following definitive principles:
1 One primary 12.288 MHz crystal on the ADAU1467.
2 ADAU1467 is the central audio clock master.
3 Main audio rate is 48 kHz.
4 Baseline I²S BCLK is 3.072 MHz for stereo 32-bit slots.
5 Si4684 receives 12.288 MHz externally from ADAU1467 CLKOUT.
6 The Si4684 dedicated crystal is removed.
7 TLV320AIC3104 may receive the same 12.288 MHz master reference on MCLK.
8 Each I²S peripheral receives its own BCLK/LRCLK pair.
9 Input and output ADAU1467 clock domains are treated as distinct.
10 BCLK/LRCLK signals are not electrically mixed on the PCB.
11 No generic BCLK/LRCLK splitter is required by the architecture.
12 S/PDIF uses the dedicated ADAU1467 interfaces.
13 ASRC is used when an external source belongs to an incompatible/asynchronous clock domain.
14 All clock-domain assignments must be explicitly reflected in both SigmaStudio and KiCad.
31. References
Primary references to be kept with the DigiRadio repository:
• Analog Devices — ADAU1463/ADAU1467 Data Sheet.
• Analog Devices — ADAU1467 product and evaluation-board documentation.
• Silicon Labs — Si468x Receiver Programming Guide (AN649).
• Silicon Labs — Si4684 hardware/reference documentation.
• Texas Instruments — TLV320AIC3104 Data Sheet.
• Feasycom — BT1035 Programming User Guide.
• DigiRadio SigmaStudio project and generated DSP configuration.
Vendor documents stored in the repository shall be treated as the implementation references. If a newer revision is added, this architecture document shall be reviewed before schematic freeze.