diff --git a/datasheets/ADG936_936R.pdf b/datasheets/ADG936_936R.pdf new file mode 100644 index 0000000..fbac395 Binary files /dev/null and b/datasheets/ADG936_936R.pdf differ diff --git a/datasheets/ASE-50.000MHZ-LC-T b/datasheets/ASE-50.000MHZ-LC-T new file mode 100644 index 0000000..039bea3 Binary files /dev/null and b/datasheets/ASE-50.000MHZ-LC-T differ diff --git a/datasheets/CDCLVP1102RGT.PDF b/datasheets/CDCLVP1102RGT.PDF new file mode 100644 index 0000000..ee2245f Binary files /dev/null and b/datasheets/CDCLVP1102RGT.PDF differ diff --git a/datasheets/LAN8720A.pdf b/datasheets/LAN8720A.pdf new file mode 100644 index 0000000..d7e06bc Binary files /dev/null and b/datasheets/LAN8720A.pdf differ diff --git a/datasheets/MCP23S17.pdf b/datasheets/MCP23S17.pdf new file mode 100644 index 0000000..1e5abc0 Binary files /dev/null and b/datasheets/MCP23S17.pdf differ diff --git a/datasheets/RJ45_Abracon_ARJP11A-MASA-B-A-EMU2.pdf b/datasheets/RJ45_Abracon_ARJP11A-MASA-B-A-EMU2.pdf new file mode 100644 index 0000000..a5a73cb Binary files /dev/null and b/datasheets/RJ45_Abracon_ARJP11A-MASA-B-A-EMU2.pdf differ diff --git a/datasheets/TPS63020.pdf b/datasheets/TPS63020.pdf new file mode 100644 index 0000000..fdff011 Binary files /dev/null and b/datasheets/TPS63020.pdf differ diff --git a/datasheets/UNI-ROYAL 4D03WGF499JT5E.pdf b/datasheets/UNI-ROYAL 4D03WGF499JT5E.pdf new file mode 100644 index 0000000..0da872b Binary files /dev/null and b/datasheets/UNI-ROYAL 4D03WGF499JT5E.pdf differ diff --git a/datasheets/bq25896.pdf b/datasheets/bq25896.pdf new file mode 100644 index 0000000..9cd1f1b Binary files /dev/null and b/datasheets/bq25896.pdf differ diff --git a/datasheets/esp32-s31-wroom-3_datasheet_en.pdf b/datasheets/esp32-s31-wroom-3_datasheet_en.pdf new file mode 100644 index 0000000..092b567 Binary files /dev/null and b/datasheets/esp32-s31-wroom-3_datasheet_en.pdf differ diff --git a/datasheets/tps22919.pdf b/datasheets/tps22919.pdf new file mode 100644 index 0000000..1522303 Binary files /dev/null and b/datasheets/tps22919.pdf differ diff --git a/docs/architecture/Clock-Architecture.md b/docs/architecture/Clock-Architecture.md new file mode 100644 index 0000000..b2e3ac3 --- /dev/null +++ b/docs/architecture/Clock-Architecture.md @@ -0,0 +1,771 @@ +# DigiRadio — Clock Architecture and I²S Clock-Domain Implementation + +**Document ID:** ARCH-CLOCK-001 +**Status:** Design Baseline +**Revision:** 2.0 +**Date:** 2026-08-15 +**Scope:** ADAU1467, Si4684, ESP32-S31-WROOM3, TLV320AIC3104IRHBR, BT1035, S/PDIF + +--- + +## 1. Purpose + +This document defines the DigiRadio digital-audio clock architecture and the physical implementation rules for the I²S clock signals. + +The architecture is based on the **ADAU1467** as the central DSP and audio-clock hub. + +The design objectives are: + +- one primary 12.288 MHz audio reference; +- 48 kHz primary audio sample rate; +- removal of the dedicated Si4684 crystal by supplying its external reference from the ADAU1467; +- use of the TLV320AIC3104 as the analog audio codec; +- independent BCLK/LRCLK pairs for the individual I²S interfaces; +- no external BCLK/LRCLK splitter or "clock mixing" network; +- explicit separation of ADAU1467 input and output clock domains; +- use of ADAU1467 internal clock-domain architecture rather than electrically tying unrelated clock signals together. + +This document is an **implementation document**: it defines how the clock architecture shall be translated into the KiCad schematic and PCB. + +--- + +# 2. Architectural Principle + +The fundamental design principle is: + +> **Each external I²S peripheral receives its own BCLK/LRCLK pair from the corresponding ADAU1467 serial-port clock domain.** + +The PCB shall **not electrically combine BCLK or LRCLK signals belonging to different serial ports**. + +The ADAU1467 internally generates and manages the required audio clock domains. + +Therefore, the PCB must not contain a global: + +```text +BCLK ─┬─ Device 1 + ├─ Device 2 + ├─ Device 3 + └─ Device 4 + +or: + + +LRCLK ─┬─ Device 1 + ├─ Device 2 + ├─ Device 3 + └─ Device 4 + +unless a specific group of peripherals has deliberately been assigned to the same physical clock source and the electrical topology has been explicitly designed for that purpose. +The default DigiRadio implementation is one BCLK/LRCLK pair per I²S interface. + +3. Master Reference Clock +3.1 Primary reference +The DigiRadio primary audio reference is: + + +12.288 MHz + +generated by a passive crystal connected to the ADAU1467 oscillator/MCLK input. +Architecture: + + +12.288 MHz crystal + │ + ▼ + ADAU1467 MCLK/XTAL + │ + ▼ + PLL + │ + ▼ + Clock Generators + │ + ├── audio clock domains + └── CLKOUT + +The 12.288 MHz reference is appropriate for a 48 kHz audio system because: + + +12.288 MHz / 256 = 48 kHz + + +4. ADAU1467 Clock Architecture +The ADAU1467 contains the clock-generation infrastructure required for a multi-peripheral audio system. +The important architectural distinction is: + + +ADAU1467 INPUT CLOCK DOMAINS + ≠ +ADAU1467 OUTPUT CLOCK DOMAINS + +Even if two domains are configured to exactly the same nominal frequency, they are not to be treated as the same physical PCB clock net. +The ADAU1467 provides multiple serial input and output ports and multiple clock domains, allowing different peripherals to be assigned independently. +This is the reason a separate BCLK/LRCLK splitter IC is not required by the baseline architecture. + +5. Primary Audio Rate +The primary DigiRadio audio rate is: + + +Fs = 48 kHz + +For stereo I²S with 32-bit slots: + + +BCLK = 48,000 × 32 × 2 + = 3,072,000 Hz + = 3.072 MHz + +Therefore the baseline values are: +Signal +Frequency +Master reference +12.288 MHz +LRCLK / WCLK +48 kHz +BCLK +3.072 MHz +I²S slot width +32 bit +Channels +2 +These values are the baseline. Individual devices must still be configured according to their own I²S timing and supported formats. + +6. Global Clock Tree +The logical architecture is: + + + 12.288 MHz + passive crystal + │ + ▼ + ┌────────────────┐ + │ ADAU1467 │ + │ │ + │ MCLK / PLL │ + │ Clock Generators│ + │ │ + │ DSP @ 48 kHz │ + └───────┬────────┘ + │ + ┌───────────────┴────────────────┐ + │ │ + ▼ ▼ + CLKOUT 12.288 MHz I²S clock domains + │ │ + ┌────┴────┐ ┌──────────┼──────────┐ + │ │ │ │ │ + ▼ ▼ ▼ ▼ ▼ + Si4684 AIC3104 Si4684 BT1035 Codec + XTALI MCLK I²S IN I²S OUT I²S + +The 12.288 MHz reference and the I²S BCLK/LRCLK signals are separate functions. + +7. Si4684 Reference Clock +7.1 External reference +The Si4684 supports an external reference clock through XTALI. +The DigiRadio design shall use: + + +ADAU1467 CLKOUT + │ + │ 12.288 MHz + ▼ +Si4684 XTALI + +The Si4684 shall be configured for the appropriate external-clock mode. +The firmware configuration must explicitly set: + + +XTAL_FREQ = 12,288,000 Hz + +and the correct external-clock CLK_MODE. +The Si4684 crystal oscillator configuration parameters shall not be blindly reused for external-clock operation. +7.2 Crystal removal +The Si4684's dedicated crystal is therefore not part of the baseline design. +The only primary 12.288 MHz crystal in the DigiRadio design is the one associated with the ADAU1467. +7.3 Electrical validation +Before schematic/PCB freeze, verify: + • ADAU1467 CLKOUT output level; + • Si4684 XTALI input limits; + • frequency; + • duty cycle; + • rise/fall time; + • startup sequence; + • signal integrity; + • routing noise coupling. + +8. Si4684 I²S Input +The Si4684 audio data enters the ADAU1467. +Baseline: + + +Si4684 ADAU1467 + +DOUT ──────────────────────► Serial IN +BCLK ◄────────────────────── Serial IN clock +LRCLK ◄────────────────────── Serial IN frame clock + +The Si4684 is configured as an I²S slave. +The BCLK/LRCLK pair used by the Si4684 belongs to the selected ADAU1467 input clock domain. +It shall not be physically connected to the BCLK/LRCLK pair used by an ADAU1467 output port merely because both operate at 48 kHz. + +9. ESP32-S31-WROOM3 I²S Input +The ESP32 audio stream enters the ADAU1467. +Preferred configuration: + + +ADAU1467 = I²S clock master +ESP32 = I²S clock slave + +Physical connection: + + +ESP32 DATA ─────────────────► ADAU1467 Serial IN + +ADAU1467 BCLK_x ────────────► ESP32 BCLK +ADAU1467 LRCLK_x ───────────► ESP32 LRCLK + +The ESP32 BCLK/LRCLK pair is a dedicated clock pair for that serial interface. +It is not to be joined to the Si4684 BCLK/LRCLK pair on the PCB. +The final ESP32 firmware shall use: + + +Fs = 48 kHz +slot width = 32 bit +I²S slave mode + +where supported by the selected ESP32 I²S implementation. + +10. TLV320AIC3104 Codec +The codec is: + + +TLV320AIC3104IRHBR + +It provides: + • stereo ADC; + • stereo DAC; + • Line In; + • Line Out; + • headphone output path; + • digital I²S interface; + • internal clock/PLL circuitry. + +11. Codec MCLK +The codec can use the same 12.288 MHz clock reference. +Preferred connection: + + +ADAU1467 CLKOUT + │ + │ 12.288 MHz + ▼ +TLV320AIC3104 MCLK + +At 48 kHz: + + +12.288 MHz / 256 = 48 kHz + +This provides a clean and deterministic clock relationship between the ADAU1467 and codec. +The codec's PLL/divider configuration must be programmed according to the TLV320AIC3104 datasheet. + +12. Codec ADC — Line In to ADAU1467 +The analog input path is: + + +LINE IN + │ + ▼ +TLV320AIC3104 ADC + │ + │ DOUT + ▼ +ADAU1467 Serial IN + +The digital clock connection is: + + +ADAU1467 BCLK_CODEC_IN + │ + └──────────────► AIC3104 BCLK + +ADAU1467 LRCLK_CODEC_IN + │ + └──────────────► AIC3104 WCLK/LRCLK + +and: + + +AIC3104 DOUT ─────────► ADAU1467 Serial IN + +The codec ADC interface is therefore an ADAU1467 input serial port. + +13. Codec DAC — ADAU1467 to Line Out / Headphone +The output path is: + + +ADAU1467 Serial OUT + │ + │ DIN + ▼ +TLV320AIC3104 DAC + │ + ├──► LINE OUT + │ + └──► HEADPHONE AMPLIFIER + │ + ▼ + Headphone Jack + +Clocking: + + +ADAU1467 BCLK_CODEC_OUT + │ + └──────────────► AIC3104 BCLK + +ADAU1467 LRCLK_CODEC_OUT + │ + └──────────────► AIC3104 WCLK/LRCLK + +Data: + + +ADAU1467 Serial OUT DATA ──► AIC3104 DIN + +The codec output clock pair is a dedicated ADAU1467 output clock-domain pair. + +14. Important: Codec Input and Output Clocks +Even though the codec ADC and DAC operate at the same nominal: + + +48 kHz / 3.072 MHz + +the schematic shall not assume that the codec ADC and DAC automatically share one physical BCLK/LRCLK net. +The preferred implementation is: + + +ADAU1467 INPUT CLOCK DOMAIN + │ + ├── BCLK_CODEC_IN + └── LRCLK_CODEC_IN + │ + ▼ + AIC3104 ADC + + +ADAU1467 OUTPUT CLOCK DOMAIN + │ + ├── BCLK_CODEC_OUT + └── LRCLK_CODEC_OUT + │ + ▼ + AIC3104 DAC + +Whether the final AIC3104 implementation can safely use one common physical clock pair for both directions is a specific codec-interface configuration decision and must be made from the TLV320AIC3104 timing/master/slave requirements. +The architecture does not require us to tie the two domains together. + +15. BT1035 +The BT1035 is an I²S output peripheral. +Preferred configuration: + + +ADAU1467 = I²S master +BT1035 = I²S slave + +Physical connections: + + +ADAU1467 BCLK_BT + └──────────────► BT1035 BCLK + +ADAU1467 LRCLK_BT + └──────────────► BT1035 LRCLK + +ADAU1467 DATA_BT + └──────────────► BT1035 I²S DATA + +Baseline: + + +48 kHz +32 bit +BCLK = 3.072 MHz + +The BT1035 interface is an ADAU1467 output clock domain. +It shall not share a PCB BCLK/LRCLK net with the codec unless deliberately configured and electrically verified. + +16. S/PDIF Input +S/PDIF is handled by the dedicated ADAU1467 S/PDIF input. + + +S/PDIF IN + │ + ▼ +ADAU1467 S/PDIF RX + │ + ▼ +ASRC / DSP clock domain + +There is no external BCLK/LRCLK connection. +The recovered S/PDIF clock is not physically combined with the I²S clock network. + +17. S/PDIF Output +Likewise: + + +ADAU1467 S/PDIF TX + │ + ▼ +S/PDIF OUT + +No external BCLK/LRCLK is required. + +18. Clock-Domain Allocation +The following is the proposed logical allocation. +Input side +Device +ADAU interface +Clock ownership +Si4684 +Serial IN 0 +ADAU1467 input clock domain +ESP32-S31-WROOM3 +Serial IN 1 +ADAU1467 input clock domain +AIC3104 ADC +Serial IN 2 +ADAU1467 input clock domain +S/PDIF +Dedicated S/PDIF IN +Recovered S/PDIF clock / ASRC +Output side +Device +ADAU interface +Clock ownership +BT1035 +Serial OUT 0 +ADAU1467 output clock domain +AIC3104 DAC +Serial OUT 1 +ADAU1467 output clock domain +S/PDIF +Dedicated S/PDIF OUT +ADAU1467 S/PDIF subsystem +The exact serial-port numbers are implementation assignments and shall be finalized against the ADAU1467 pinout and PCB placement. + +19. No Clock "Mishmash" +The following shall be considered a design rule: +Do not electrically connect unrelated BCLK or LRCLK signals merely because they have the same frequency. +For example, these are logically different: + + +BCLK_SI4684 +BCLK_ESP32 +BCLK_CODEC_IN +BCLK_BT +BCLK_CODEC_OUT + +Even if all are: + + +3.072 MHz + +they are separate clock nets. +Likewise: + + +LRCLK_SI4684 +LRCLK_ESP32 +LRCLK_CODEC_IN +LRCLK_BT +LRCLK_CODEC_OUT + +remain separate nets. +This provides: + • deterministic ownership; + • no contention between clock drivers; + • cleaner PCB routing; + • easier debugging; + • easier clock-domain changes; + • easier future support for different sample rates. + +20. Internal ADAU1467 Clock Relationship +The important distinction is: + + +PHYSICAL PCB CONNECTION + ≠ +LOGICAL CLOCK RELATIONSHIP + +The ADAU1467 can derive several clock domains from the same master reference. +Therefore: + + +BCLK_A = 3.072 MHz +BCLK_B = 3.072 MHz +BCLK_C = 3.072 MHz + +does not imply: + + +BCLK_A = physical net BCLK_B = physical net BCLK_C + +They are independently generated/assigned clock-domain signals. +The synchronization relationship is established by the ADAU1467 clock-generation architecture. + +21. PCB Net Naming +The schematic shall use explicit net names. +Recommended names: + + +MCLK_12M288 +SI4684_BCLK +SI4684_LRCLK +SI4684_SDOUT + +ESP32_BCLK +ESP32_LRCLK +ESP32_SDOUT + +CODEC_ADC_BCLK +CODEC_ADC_LRCLK +CODEC_ADC_SDOUT + +BT_BCLK +BT_LRCLK +BT_SDIN + +CODEC_DAC_BCLK +CODEC_DAC_LRCLK +CODEC_DAC_SDIN + +SPDIF_IN +SPDIF_OUT + +Do not use a generic: + + +BCLK +LRCLK + +label for the entire board unless that net is intentionally a single shared physical clock. + +22. PCB Routing Rules +22.1 MCLK_12M288 +Route: + + +ADAU1467 CLKOUT + │ + ├──► Si4684 XTALI + └──► AIC3104 MCLK + +The two loads may be fed from the same source only after checking the ADAU1467 CLKOUT drive capability and total input capacitance. +Keep the clock routes short and away from switching-regulator nodes. +22.2 BCLK/LRCLK +Each clock pair shall be routed independently: + + +ADAU1467 + │ + ├── SI4684_BCLK / LRCLK + │ + ├── ESP32_BCLK / LRCLK + │ + ├── CODEC_ADC_BCLK / LRCLK + │ + ├── BT_BCLK / LRCLK + │ + └── CODEC_DAC_BCLK / LRCLK + +Avoid unnecessary stubs. +Use source termination if required by signal-integrity analysis. + +23. Why No External Clock Splitter? +A clock splitter is not required simply because several peripherals use 48 kHz. +The ADAU1467 already provides the required clock-generation architecture. +Adding an external clock splitter would introduce: + • another active clock component; + • additional propagation delay; + • additional jitter; + • additional power consumption; + • another configuration dependency; + • another possible failure point. +It should therefore be added only if electrical analysis proves that a specific fanout requirement cannot be met by the ADAU1467 clock outputs. + +24. Why Not Share BCLK/LRCLK Everywhere? +Sharing clock signals is technically possible in some I²S designs, but it is not the baseline DigiRadio architecture. +The risks of indiscriminate sharing are: + • conflicting clock drivers; + • accidental master/master configuration; + • long PCB branches; + • uncontrolled stubs; + • difficult debugging; + • inability to independently change one interface; + • confusion between ADAU input and output clock domains. +The ADAU1467 gives us enough clock-domain infrastructure to avoid these problems. +Therefore the design deliberately favors independent clock pairs. + +25. Master/Slave Policy +The baseline policy is: +Device +I²S role +ADAU1467 +Master +Si4684 +Slave +ESP32-S31-WROOM3 +Slave +TLV320AIC3104 +Slave where supported/configured +BT1035 +Slave +This avoids multiple external clock masters. +Any deviation must be documented as an explicit architecture change. + +26. Sample-Rate Conversion +If an external source operates at a sample rate different from 48 kHz: + + +External clock domain + │ + ▼ +ADAU1467 Serial Port + │ + ▼ + ASRC + │ + ▼ +48 kHz DSP domain + +The external BCLK/LRCLK must remain local to that interface. +It shall not be forced onto the main 48 kHz clock net. + +27. Final Logical Architecture + + + 12.288 MHz + ADAU CRYSTAL + │ + ▼ + ┌───────────────┐ + │ ADAU1467 │ + │ │ + │ PLL │ + │ Clock Gen. │ + │ DSP │ + └───────┬───────┘ + │ + ┌──────────────┼───────────────┐ + │ │ │ + ▼ ▼ ▼ + CLKOUT INPUT DOMAINS OUTPUT DOMAINS + 12.288 MHz │ │ + │ │ │ + ┌─────┴─────┐ │ ┌────┼─────┐ + │ │ │ │ │ + ▼ ▼ ▼ ▼ ▼ + Si4684 AIC3104 Si4684 BT1035 AIC3104 + XTALI MCLK I²S IN I²S OUT I²S OUT + ▲ │ │ + │ │ │ + ESP32 I²S BCLK/LR BCLK/LR + ▲ + │ + ESP32 DATA + +S/PDIF remains on the dedicated ADAU1467 interfaces. + +28. Implementation Sequence +The schematic implementation shall proceed in this order: + 1 Place ADAU1467. + 2 Place the 12.288 MHz crystal and its oscillator network. + 3 Define ADAU1467 PLL and clock-generator configuration. + 4 Define serial input clock domains. + 5 Assign Si4684 to an input serial port. + 6 Assign ESP32 to an input serial port. + 7 Assign AIC3104 ADC to an input serial port. + 8 Define output clock domains. + 9 Assign BT1035 to an output serial port. + 10 Assign AIC3104 DAC to an output serial port. + 11 Connect ADAU1467 CLKOUT to Si4684 XTALI. + 12 Connect ADAU1467 CLKOUT to AIC3104 MCLK if the final loading analysis permits. + 13 Route every BCLK/LRCLK pair as a separate named net. + 14 Verify that no two clock outputs are accidentally shorted. + 15 Verify all master/slave settings. + 16 Verify SigmaStudio serial-port and clock-domain assignments against the schematic. + 17 Perform signal-integrity review before PCB release. + +29. Verification Checklist +Master clock + • 12.288 MHz crystal connected to ADAU1467. + • ADAU1467 PLL configuration verified. + • 12.288 MHz CLKOUT configuration verified. + • CLKOUT loading verified. +Si4684 + • Dedicated crystal removed. + • XTALI driven from ADAU1467 CLKOUT. + • External-clock mode configured. + • XTAL_FREQ = 12,288,000 Hz. + • I²S slave mode configured. + • Dedicated SI4684_BCLK net. + • Dedicated SI4684_LRCLK net. +ESP32 + • I²S slave mode verified. + • Dedicated ESP32_BCLK net. + • Dedicated ESP32_LRCLK net. + • 48 kHz / selected slot format verified. +TLV320AIC3104 + • MCLK = 12.288 MHz verified. + • ADC serial input assigned. + • DAC serial output assigned. + • Master/slave mode verified. + • ADC BCLK/LRCLK routing verified. + • DAC BCLK/LRCLK routing verified. + • Headphone path verified. +BT1035 + • I²S slave mode verified. + • 48 kHz / 32-bit configuration verified. + • Dedicated BT_BCLK. + • Dedicated BT_LRCLK. +S/PDIF + • Dedicated ADAU1467 S/PDIF IN. + • Dedicated ADAU1467 S/PDIF OUT. + • No BCLK/LRCLK connection required. +PCB + • No unintended common BCLK net. + • No unintended common LRCLK net. + • No master/master connection. + • Clock routes kept short. + • Switching-node coupling checked. + • Signal integrity checked. + +30. Design Decision +The DigiRadio clock architecture is therefore based on the following definitive principles: + 1 One primary 12.288 MHz crystal on the ADAU1467. + 2 ADAU1467 is the central audio clock master. + 3 Main audio rate is 48 kHz. + 4 Baseline I²S BCLK is 3.072 MHz for stereo 32-bit slots. + 5 Si4684 receives 12.288 MHz externally from ADAU1467 CLKOUT. + 6 The Si4684 dedicated crystal is removed. + 7 TLV320AIC3104 may receive the same 12.288 MHz master reference on MCLK. + 8 Each I²S peripheral receives its own BCLK/LRCLK pair. + 9 Input and output ADAU1467 clock domains are treated as distinct. + 10 BCLK/LRCLK signals are not electrically mixed on the PCB. + 11 No generic BCLK/LRCLK splitter is required by the architecture. + 12 S/PDIF uses the dedicated ADAU1467 interfaces. + 13 ASRC is used when an external source belongs to an incompatible/asynchronous clock domain. + 14 All clock-domain assignments must be explicitly reflected in both SigmaStudio and KiCad. + +31. References +Primary references to be kept with the DigiRadio repository: + • Analog Devices — ADAU1463/ADAU1467 Data Sheet. + • Analog Devices — ADAU1467 product and evaluation-board documentation. + • Silicon Labs — Si468x Receiver Programming Guide (AN649). + • Silicon Labs — Si4684 hardware/reference documentation. + • Texas Instruments — TLV320AIC3104 Data Sheet. + • Feasycom — BT1035 Programming User Guide. + • DigiRadio SigmaStudio project and generated DSP configuration. +Vendor documents stored in the repository shall be treated as the implementation references. If a newer revision is added, this architecture document shall be reviewed before schematic freeze. diff --git a/docs/architecture/HubAudio-ESP31-S31-WROOM3-PinUsage.md b/docs/architecture/HubAudio-ESP31-S31-WROOM3-PinUsage.md new file mode 100644 index 0000000..0a5af2b --- /dev/null +++ b/docs/architecture/HubAudio-ESP31-S31-WROOM3-PinUsage.md @@ -0,0 +1,65 @@ +# Mappatura Hardware e Pinout: ESP32-S31-WROOM-3 + +Questo documento raccoglie la configurazione completa e definitiva dei pin per il modulo **ESP32-S31-WROOM-3** utilizzata nel layout del PCB. + +--- + +## 1. Tabella Definitiva Mappatura Hardware + +| Periferica / Blocco | Segnale Hardware | GPIO ESP32-S31 | Pin Schema | Note e Connessioni Hardware | +| :--- | :--- | :--- | :--- | :--- | +| **ETHERNET (RMII / LAN8720A)** | `ETH_50MHZ_CLOCK` | **GPIO13** | **Pin 19** | Ingresso Clock 50 MHz da oscillatore | +| | `ETH_TXD0` | **GPIO8** | **Pin 14** | Dati TX Bit 0 | +| | `ETH_TXD1` | **GPIO9** | **Pin 15** | Dati TX Bit 1 | +| | `ETH_TXEN` | **GPIO12** | **Pin 18** | Transmit Enable | +| | `ETH_RXD0` | **GPIO19** | **Pin 25** | Dati RX Bit 0 | +| | `ETH_RXD1` | **GPIO18** | **Pin 24** | Dati RX Bit 1 | +| | `ETH_CRS_DV` | **GPIO15** | **Pin 21** | Carrier Sense / Data Valid | +| | `ETH_MDC` | **GPIO5** | **Pin 11** | Clock Gestione PHY | +| | `ETH_MDIO` | **GPIO6** | **Pin 12** | Dati Gestione PHY (Pull-up 1.5 kΩ ~ 4.7 kΩ) | +| | `ETH_RST#` | **GPIO7** | **Pin 13** | Reset Hardware LAN8720A | +| | `ETH_RXER` | **GPIO10** | **Pin 16** | Receive Error / Config. Indirizzo PHY0 | +| | `ETH_INT#` | **GPIO4** | **Pin 10** | Interruzione PHY (Pull-up 10 kΩ) | +| **SPI BUS (Master)** | `SPI_MOSI` | **GPIO2** | **Pin 6** | Dati in Uscita (Condiviso Si4684 + ADAU1467)[cite: 1] | +| | `SPI_MISO` | **GPIO3** | **Pin 7** | Dati in Ingresso (Condiviso Si4684 + ADAU1467)[cite: 1] | +| | `SPI_CLK` | **GPIO1** | **Pin 9** | Clock Serial SPI[cite: 1] | +| | `SPI_SI4684_CS` | **GPIO16** | **Pin 22** | Chip Select Radio Si4684[cite: 1] | +| | `SPI_ADAU1467_CS` | **GPIO17** | **Pin 23** | Chip Select DSP ADAU1467[cite: 1] | +| **I2C BUS (Master)** | `I2C_SDA` | **GPIO50** | **Pin 60** | (Pull-up 4.7 kΩ) | +| | `I2C_SCL` | **GPIO51** | **Pin 61** | (Pull-up 4.7 kΩ) | +| **I2S_0 (Slave)** | `I2S0_BCLK` | **GPIO42** | **Pin 52** | Bit Clock (Ingresso da Master esterno)[cite: 1] | +| | `I2S0_LRCLK` | **GPIO43** | **Pin 53** | Frame Sync / WS (Ingresso da Master)[cite: 1] | +| | `I2S0_DATA` | **GPIO44** | **Pin 54** | Dati Audio 1[cite: 1] | +| **I2S_1 (Slave)** | `I2S1_BCLK` | **GPIO46** | **Pin 56** | Bit Clock (Ingresso da Master esterno)[cite: 1] | +| | `I2S1_LRCLK` | **GPIO47** | **Pin 57** | Frame Sync / WS (Ingresso da Master)[cite: 1] | +| | `I2S1_DATA` | **GPIO48** | **Pin 58** | Dati Audio 2[cite: 1] | +| **UART BT1035** | `BT_TX` | **GPIO52** | **Pin 62** | Collegare a **RXD** del modulo BT1035 | +| | `BT_RX` | **GPIO53** | **Pin 63** | Collegare a **TXD** del modulo BT1035 | +| | `BT_RTS` *(Opz.)* | **GPIO54** | **Pin 64** | Controllo di flusso (Collegare a **CTS** del BT1035) | +| | `BT_CTS` *(Opz.)* | **GPIO55** | **Pin 65** | Controllo di flusso (Collegare a **RTS** del BT1035) | +| **INTERRUPTS & IO** | `PCA_POWER_INT` | **GPIO11** | **Pin 17** | Interruzione da espansore I2C PCA9555 (Power Unit)[cite: 1] | +| | `SPARE_IO0` | **GPIO16** | **Pin 22** | GPIO libero / Riserva[cite: 1] | +| | `SPARE_IO1` | **GPIO17** | **Pin 23** | GPIO libero / Riserva[cite: 1] | +| **SYSTEM & BOOT** | `ESP_EN` | **EN** | **Pin 5** | Reset Hardware (Pull-up 10 kΩ + Cap 1 µF verso GND)[cite: 1] | +| | `ESP_BOOT` | **GPIO61** | **Pin 71** | Strapping Pin / Pulsante BOOT (Pull-up interno)[cite: 1] | +| | `USB_DP` | **USB_DP** | **Pin 40** | USB Data+ (Coppia differenziale 90 Ω)[cite: 1] | +| | `USB_DM` | **USB_DM** | **Pin 41** | USB Data- (Coppia differenziale 90 Ω)[cite: 1] | + +--- + +## 2. Note di Progettazione Hardware + +### USB Serial / JTAG Integrato +* Per programmazione e debug è sufficiente un singolo connettore **USB Type-C** direttamente collegato a `USB_DP` (Pin 40) e `USB_DM` (Pin 41)[cite: 1]. +* Inserire **due resistenze da 5.1 kΩ** su CC1 e CC2 verso GND sul connettore Type-C. + +### Bus SPI +* I dispositivi controllati in SPI sono 2: **Si4684** (`CS0` su `GPIO13`) e **ADAU1467** (`CS1` su `GPIO14`)[cite: 1]. +* Aggiungere resistori di **pull-up esterni da 10 kΩ a 3.3V** sulle linee CS per garantire lo stato HIGH durante il boot. + +### Bus I2C +* Il codec **TLV320AIC3104** (indirizzo `0x18`) è controllato via I2C (`GPIO50` per SDA e `GPIO51` per SCL). +* Prevedere due resistori di pull-up esterni da **2.2 kΩ a 4.7 kΩ** verso 3.3V. + +### Interfacce I2S Audio +* Entrambi i canali I2S sono configurati in modalità **Slave**. I segnali di clock `BCLK` e `LRCLK` provengono dai rispettivi dispositivi Master esterni[cite: 1]. diff --git a/docs/architecture/I2C-Addressing b/docs/architecture/I2C-Addressing index 2c788bc..214fcce 100644 --- a/docs/architecture/I2C-Addressing +++ b/docs/architecture/I2C-Addressing @@ -10,4 +10,5 @@ | TLV320AIC3104 | Audio Codec | ADDR = GND | 0x18 | | SC16IS740 | RX | A1=GND, A0=GND | 0x48 | | SC16IS740 | TX | A1=GND, A0=VCC | 0x49 | -| BQ27441 | Fuel Gauge | Indirizzo fisso | 0x55 | \ No newline at end of file +| BQ27441 | Fuel Gauge | Indirizzo fisso | 0x55 | +| BQ25896 | Fuel manager. | Indirizzo fissi | 0x6B \ No newline at end of file diff --git a/hardware/kicad/HubAudio/.gitignore b/hardware/kicad/HubAudio/.gitignore index 4d8aa36..5318cb7 100644 --- a/hardware/kicad/HubAudio/.gitignore +++ b/hardware/kicad/HubAudio/.gitignore @@ -1,2 +1,9 @@ +# KiCad lock / temporary files +*.lck *.kicad_prl -*.kicad_pro.lck + +# KiCad history +.history/ + +# KiCad automatic restore/backup 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1.27 1.27) + ) + ) + ) + (property "Description" "0805W8F2201T5E" + (at 135.89 90.17 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (pin "1" + (uuid "39ae54a7-f6f7-4de2-a928-9369b3cdd052") + ) + (pin "2" + (uuid "6f728199-89ce-4e09-b9dc-20a118894112") + ) + (instances + (project "HubAudio" + (path "/841d8022-3a94-443e-97aa-a99a12889684/81d9e142-f3fa-46a0-96de-196a5f9efcbd" + (reference "R74") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "MIKILAB_power:GND") + (at 135.89 123.19 0) + (unit 1) + (body_style 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (in_pos_files yes) + (dnp no) + (fields_autoplaced yes) + (uuid "f790a9af-3fa6-4658-a2fd-78e2d0b71e0f") + (property "Reference" "#PWR0175" + (at 135.89 129.54 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "GND" + (at 135.89 128.27 0) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "" + (at 135.89 123.19 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" "" + (at 135.89 123.19 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "Power symbol creates a global label with name \"GND\" , ground" + (at 135.89 123.19 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (pin "1" + (uuid "be442722-f2bc-450a-a61e-ac05b1f86142") + ) + (instances + (project "HubAudio" + (path "/841d8022-3a94-443e-97aa-a99a12889684/81d9e142-f3fa-46a0-96de-196a5f9efcbd" + (reference "#PWR0175") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "power:GND") + (at 40.64 55.88 0) + (unit 1) + (body_style 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (in_pos_files yes) + (dnp no) + (fields_autoplaced yes) + (uuid "ff3e3c6c-ac5e-4548-8022-6e96bb0238ab") + (property "Reference" "#PWR035" + (at 40.64 62.23 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "GND" + (at 40.64 60.96 0) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "" + (at 40.64 55.88 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" "" + (at 40.64 55.88 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "Power symbol creates a global label with name \"GND\" , ground" + (at 40.64 55.88 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (pin "1" + (uuid "fe0b521a-e98c-443e-aff1-fc1b3a0fd58c") + ) + (instances + (project "HubAudio" + (path "/841d8022-3a94-443e-97aa-a99a12889684/81d9e142-f3fa-46a0-96de-196a5f9efcbd" + (reference "#PWR035") + (unit 1) + ) + ) + ) + ) +) diff --git a/hardware/kicad/HubAudio/HubAudio.kicad_pcb b/hardware/kicad/HubAudio/HubAudio.kicad_pcb index ccd82d6..5e2a0b4 100644 --- a/hardware/kicad/HubAudio/HubAudio.kicad_pcb +++ b/hardware/kicad/HubAudio/HubAudio.kicad_pcb @@ -1,2 +1,91 @@ -(kicad_pcb (version 20260206) (generator "pcbnew") (generator_version "10.0") -) \ No newline at end of file +(kicad_pcb + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (general + (thickness 1.6) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting + (front yes) + (back yes) + ) + (covering + (front no) + (back no) + ) + (plugging + (front no) + (back no) + ) + (capping no) + (filling no) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12) + (dashed_line_gap_ratio 3) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (embedded_fonts no) +) diff --git a/hardware/kicad/HubAudio/HubAudio.kicad_pro b/hardware/kicad/HubAudio/HubAudio.kicad_pro index 630e3ad..4bc0c36 100644 --- a/hardware/kicad/HubAudio/HubAudio.kicad_pro +++ b/hardware/kicad/HubAudio/HubAudio.kicad_pro @@ -1,6 +1,238 @@ { "board": { "3dviewports": [], + "design_settings": { + "defaults": { + "apply_defaults_to_fp_barcodes": false, + "apply_defaults_to_fp_dimensions": false, + "apply_defaults_to_fp_fields": false, + "apply_defaults_to_fp_shapes": false, + "apply_defaults_to_fp_text": false, + "board_outline_line_width": 0.05, + "copper_line_width": 0.2, + "copper_text_italic": false, + "copper_text_size_h": 1.5, + "copper_text_size_v": 1.5, + "copper_text_thickness": 0.3, + "copper_text_upright": false, + "courtyard_line_width": 0.05, + "dimension_precision": 4, + "dimension_units": 3, + "dimensions": { + "arrow_length": 1270000, + "extension_offset": 500000, + "keep_text_aligned": true, + "suppress_zeroes": true, + "text_position": 0, + "units_format": 0 + }, + "fab_line_width": 0.1, + "fab_text_italic": false, + "fab_text_size_h": 1.0, + "fab_text_size_v": 1.0, + "fab_text_thickness": 0.15, + "fab_text_upright": false, + "other_line_width": 0.1, + "other_text_italic": false, + "other_text_size_h": 1.0, + "other_text_size_v": 1.0, + "other_text_thickness": 0.15, + "other_text_upright": false, + "pads": { + "drill": 0.8, + "height": 1.27, + "width": 1.27 + }, + "silk_line_width": 0.1, + "silk_text_italic": false, + "silk_text_size_h": 1.0, + "silk_text_size_v": 1.0, + "silk_text_thickness": 0.1, + "silk_text_upright": false, + "zones": { + "border_display_style": 2, + "border_hatch_pitch": 0.5, + "corner_radius": 0.0, + "corner_smoothing": 0, + "fill_mode": 0, + "hatch_gap": 1.5, + "hatch_orientation": 0.0, + "hatch_smoothing_level": 0, + "hatch_smoothing_value": 0.1, + "hatch_thickness": 1.0, + "min_clearance": 0.5, + "min_island_area": 10.0, + "min_thickness": 0.25, + "pad_connection": 1, + "remove_islands": 0, + "thermal_relief_gap": 0.5, + "thermal_relief_spoke_width": 0.5 + } + }, + "diff_pair_dimensions": [], + "drc_exclusions": [], + "meta": { + "version": 2 + }, + "rule_severities": { + "annular_width": "error", + "clearance": "error", + "connection_width": "warning", + "copper_edge_clearance": "error", + "copper_sliver": "warning", + "courtyards_overlap": "error", + "creepage": "error", + "diff_pair_gap_out_of_range": "error", + "diff_pair_uncoupled_length_too_long": "error", + "drill_out_of_range": "error", + "duplicate_footprints": "warning", + "extra_footprint": "warning", + "footprint": "error", + "footprint_filters_mismatch": "ignore", + "footprint_symbol_field_mismatch": "warning", + "footprint_symbol_mismatch": "warning", + "footprint_type_mismatch": "ignore", + "hole_clearance": "error", + "hole_to_hole": "warning", + "holes_co_located": "warning", + "invalid_outline": "error", + "isolated_copper": "warning", + "item_on_disabled_layer": "error", + "items_not_allowed": "error", + "length_out_of_range": "error", + "lib_footprint_issues": "warning", + "lib_footprint_mismatch": "warning", + "malformed_courtyard": "error", + "microvia_drill_out_of_range": "error", + "mirrored_text_on_front_layer": "warning", + "missing_courtyard": "ignore", + "missing_footprint": "warning", + "missing_tuning_profile": "warning", + "net_conflict": "warning", + "nonmirrored_text_on_back_layer": "warning", + "npth_inside_courtyard": "error", + "padstack": "warning", + "pth_inside_courtyard": "error", + "shorting_items": "error", + "silk_edge_clearance": "warning", + "silk_over_copper": "warning", + "silk_overlap": "warning", + "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_on_edge_cuts": "error", + "text_thickness": "warning", + "through_hole_pad_without_hole": "error", + "too_many_vias": "error", + "track_angle": "error", + "track_dangling": "warning", + "track_not_centered_on_via": "ignore", + "track_on_post_machined_layer": "error", + "track_segment_length": "error", + "track_width": "error", + "tracks_crossing": "error", + "tuning_profile_track_geometries": "ignore", + "unconnected_items": "error", + "unresolved_variable": "error", + "via_dangling": "warning", + "zones_intersect": "error" + }, + "rules": { + "max_error": 0.005, + "min_clearance": 0.0, + "min_connection": 0.0, + "min_copper_edge_clearance": 0.5, + "min_groove_width": 0.0, + "min_hole_clearance": 0.25, + "min_hole_to_hole": 0.25, + "min_microvia_diameter": 0.2, + "min_microvia_drill": 0.1, + "min_resolved_spokes": 2, + "min_silk_clearance": 0.0, + "min_text_height": 0.8, + "min_text_thickness": 0.08, + "min_through_hole_diameter": 0.3, + "min_track_width": 0.2, + "min_via_annular_width": 0.1, + "min_via_diameter": 0.5, + "solder_mask_to_copper_clearance": 0.0, + "use_height_for_length_calcs": true + }, + "teardrop_options": [ + { + "td_onpthpad": true, + "td_onroundshapesonly": false, + "td_onsmdpad": true, + "td_ontrackend": false, + "td_onvia": true + } + ], + "teardrop_parameters": [ + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_round_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_rect_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_track_end", + "td_width_to_size_filter_ratio": 0.9 + } + ], + "track_widths": [], + "tuning_pattern_settings": { + "diff_pair_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 1.0 + }, + "diff_pair_skew_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + }, + "single_track_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + } + }, + "via_dimensions": [], + "zones_allow_external_fillets": false + }, "ipc2581": { "bom_rev": "", "dist": "", @@ -27,6 +259,230 @@ "cvpcb": { "equivalence_files": [] }, + "erc": { + "erc_exclusions": [], + "meta": { + "version": 0 + }, + "pin_map": [ + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 2, + 0, + 1, + 0, + 0, + 1, + 0, + 2, + 2, + 2, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 2 + ], + [ + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 2, + 1, + 1, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2 + ], + [ + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 2 + ], + [ + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 2, + 1, + 2, + 0, + 0, + 1, + 0, + 2, + 2, + 2, + 2 + ], + [ + 0, + 2, + 0, + 1, + 0, + 0, + 1, + 0, + 2, + 0, + 0, + 2 + ], + [ + 0, + 2, + 1, + 1, + 0, + 0, + 1, + 0, + 2, + 0, + 0, + 2 + ], + [ + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2 + ] + ], + "rule_severities": { + "bus_definition_conflict": "error", + "bus_entry_needed": "error", + "bus_to_bus_conflict": "error", + "bus_to_net_conflict": "error", + "different_unit_footprint": "error", + "different_unit_net": "error", + "duplicate_reference": "error", + "duplicate_sheet_names": "error", + "endpoint_off_grid": "warning", + "extra_units": "error", + "field_name_whitespace": "warning", + "footprint_filter": "ignore", + "footprint_link_issues": "warning", + "four_way_junction": "ignore", + "ground_pin_not_ground": "warning", + "hier_label_mismatch": "error", + "isolated_pin_label": "warning", + "label_dangling": "error", + "label_multiple_wires": "warning", + "lib_symbol_issues": "warning", + "lib_symbol_mismatch": "warning", + "missing_bidi_pin": "warning", + "missing_input_pin": "warning", + "missing_power_pin": "error", + "missing_unit": "warning", + "multiple_net_names": "warning", + "net_not_bus_member": "warning", + "no_connect_connected": "warning", + "no_connect_dangling": "warning", + "pin_not_connected": "error", + "pin_not_driven": "error", + "pin_to_pin": "warning", + "power_pin_not_driven": "error", + "same_local_global_label": "warning", + "similar_label_and_power": "warning", + "similar_labels": "warning", + "similar_power": "warning", + "simulation_model_issue": "ignore", + "single_global_label": "ignore", + "stacked_pin_name": "warning", + "unannotated": "error", + "unconnected_wire_endpoint": "warning", + "undefined_netclass": "error", + "unit_value_mismatch": "error", + "unresolved_variable": "error", + "wire_dangling": "error" + } + }, "libraries": { "pinned_footprint_libs": [], "pinned_symbol_libs": [] @@ -61,7 +517,20 @@ "version": 5 }, "net_colors": null, - "netclass_assignments": null, + "netclass_assignments": { + "unconnected-(R1-Pad1)": [ + "3V3_DIGITAL" + ], + "unconnected-(R10-Pad2)": [ + "3V3_DIGITAL" + ], + "unconnected-(R3-Pad1)": [ + "3V3_DIGITAL" + ], + "unconnected-(R7-Pad2)": [ + "3V3_DIGITAL" + ] + }, "netclass_patterns": [] }, "pcbnew": { @@ -75,12 +544,336 @@ "page_layout_descr_file": "" }, "schematic": { + "annotate_start_num": 0, + "annotation": { + "method": 0, + "sort_order": 0 + }, + "bom_export_filename": "${PROJECTNAME}.csv", + "bom_fmt_presets": [], + "bom_fmt_settings": { + "field_delimiter": ",", + "keep_line_breaks": false, + "keep_tabs": false, + "name": "CSV", + "ref_delimiter": ",", + "ref_range_delimiter": "", + "string_delimiter": "\"" + }, + "bom_presets": [], + "bom_settings": { + "exclude_dnp": false, + "fields_ordered": [ + { + "group_by": false, + "label": "Reference", + "name": "Reference", + "show": true + }, + { + "group_by": false, + "label": "Qty", + "name": "${QUANTITY}", + "show": true + }, + { + "group_by": true, + "label": "Value", + "name": "Value", + "show": true + }, + { + "group_by": true, + "label": "DNP", + "name": "${DNP}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from BOM", + "name": "${EXCLUDE_FROM_BOM}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from Board", + "name": "${EXCLUDE_FROM_BOARD}", + "show": true + }, + { + "group_by": true, + "label": "Footprint", + "name": "Footprint", + "show": true + }, + { + "group_by": false, + "label": "Datasheet", + "name": "Datasheet", + "show": true + }, + { + "group_by": false, + "label": "Arrow Price/Stock", + "name": "Arrow Price/Stock", + "show": false + }, + { + "group_by": false, + "label": "Availability", + "name": "Availability", + "show": false + }, + { + "group_by": false, + "label": "Check_prices", + "name": "Check_prices", + "show": false + }, + { + "group_by": false, + "label": "Description_1", + "name": "Description_1", + "show": false + }, + { + "group_by": false, + "label": "DIGIKEY-PURCHASE-URL", + "name": "DIGIKEY-PURCHASE-URL", + "show": false + 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"Datasheet" "" + (at 195.58 53.34 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "Power symbol creates a global label with name \"GND\" , ground" + (at 195.58 53.34 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (pin "1" + (uuid "4be0e9d9-b1ec-4deb-b5a5-31c2432a910d") + ) + (instances + (project "HubAudio" + (path "/841d8022-3a94-443e-97aa-a99a12889684/be5acd16-8a33-4b43-9869-78b6acaaceab" + (reference "#PWR015") + (unit 1) + ) + ) + ) + ) +) diff --git a/hardware/kicad/HubAudio/Si4684.kicad_sch b/hardware/kicad/HubAudio/Si4684.kicad_sch new file mode 100644 index 0000000..d3c7ab7 --- /dev/null +++ b/hardware/kicad/HubAudio/Si4684.kicad_sch @@ -0,0 +1,5757 @@ +(kicad_sch + (version 20260306) + (generator "eeschema") + (generator_version "10.0") + (uuid "32a3482a-4088-4d5b-b499-3280d56a18b9") + (paper "A4") + (lib_symbols + (symbol "Device:C" + (pin_numbers + (hide yes) + ) + (pin_names + (offset 0.254) + ) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (in_pos_files yes) + (duplicate_pin_numbers_are_jumpers no) + (property "Reference" "C" + (at 0.635 2.54 0) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Value" "C" + (at 0.635 -2.54 0) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "" + (at 0.9652 -3.81 0) + (show_name no) + (do_not_autoplace no) + (hide yes) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (show_name no) + (do_not_autoplace no) + (hide yes) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 0 0 0) + (show_name no) + (do_not_autoplace no) + (hide yes) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "ki_keywords" "cap capacitor" + (at 0 0 0) + (show_name no) + (do_not_autoplace no) + (hide yes) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "ki_fp_filters" "C_*" + (at 0 0 0) + (show_name no) + (do_not_autoplace no) + (hide yes) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (symbol "C_0_1" + (polyline + (pts + (xy -2.032 0.762) (xy 2.032 0.762) + ) + (stroke + (width 0.508) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy -2.032 -0.762) (xy 2.032 -0.762) + ) + (stroke + (width 0.508) + (type default) + ) + (fill + (type none) + ) + ) + ) + (symbol "C_1_1" + (pin passive line + (at 0 3.81 270) + (length 2.794) + (name "" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 0 -3.81 90) + (length 2.794) + (name "" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "2" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + ) + (embedded_fonts no) + ) + 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private "KLC_S3.3" "The rectangle is not a symbol body but a graphical element" + (at 0 -12.7 0) + (show_name yes) + (do_not_autoplace no) + (hide yes) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property private "KLC_S4.1" "Some pins are on 50mil grid to make the symbol small" + (at 0 -15.24 0) + (show_name yes) + (do_not_autoplace no) + (hide yes) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "ki_keywords" "quartz ceramic resonator oscillator" + (at 0 0 0) + (show_name no) + (do_not_autoplace no) + (hide yes) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "ki_fp_filters" "Crystal*" + (at 0 0 0) + (show_name no) + (do_not_autoplace no) + (hide yes) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (symbol "Crystal_GND24_0_1" + (polyline + (pts + (xy -2.54 2.286) (xy -2.54 3.556) (xy 2.54 3.556) (xy 2.54 2.286) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy -2.54 0) (xy -2.032 0) + ) + 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b/hardware/kicad/HubAudio/antenna.kicad_sch new file mode 100644 index 0000000..0ef0a25 --- /dev/null +++ b/hardware/kicad/HubAudio/antenna.kicad_sch @@ -0,0 +1,7125 @@ +(kicad_sch + (version 20260306) + (generator "eeschema") + (generator_version "10.0") + (uuid "c163461d-48d7-4ec5-bf62-99ea753fa005") + (paper "A4") + (lib_symbols + (symbol "Device:C" + (pin_numbers + (hide yes) + ) + (pin_names + (offset 0.254) + ) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (in_pos_files yes) + (duplicate_pin_numbers_are_jumpers no) + (property "Reference" "C" + (at 0.635 2.54 0) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Value" "C" + (at 0.635 -2.54 0) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "" + (at 0.9652 -3.81 0) + (show_name no) + (do_not_autoplace no) + (hide yes) + (effects + (font + (size 1.27 1.27) + ) + ) + ) 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a/hardware/kicad/HubAudio/audiodomaincontroller.kicad_sch b/hardware/kicad/HubAudio/audiodomaincontroller.kicad_sch new file mode 100644 index 0000000..44925c4 --- /dev/null +++ b/hardware/kicad/HubAudio/audiodomaincontroller.kicad_sch @@ -0,0 +1,8 @@ +(kicad_sch + (version 20260306) + (generator "eeschema") + (generator_version "10.0") + (uuid "e5b037e0-04a1-4d53-8166-a7c319cdf4c3") + (paper "A4") + (lib_symbols) +) diff --git a/hardware/kicad/HubAudio/device-manager.kicad_sch b/hardware/kicad/HubAudio/device-manager.kicad_sch new file mode 100644 index 0000000..dbdd478 --- /dev/null +++ b/hardware/kicad/HubAudio/device-manager.kicad_sch @@ -0,0 +1,6690 @@ +(kicad_sch + (version 20260306) + (generator "eeschema") + (generator_version "10.0") + (uuid "5f819611-9355-4c22-a829-31ef23e46df5") + (paper "A4") + (lib_symbols + (symbol "Device:C" + (pin_numbers + (hide yes) + ) + (pin_names + (offset 0.254) + ) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (in_pos_files yes) + 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