micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
186 lines
8.4 KiB
Plaintext
186 lines
8.4 KiB
Plaintext
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 72/43848 0%
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Info: logic LUTs: 24/43848 0%
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Info: carry LUTs: 0/43848 0%
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Info: RAM LUTs: 32/ 5481 0%
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Info: RAMW LUTs: 16/10962 0%
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Info: Total DFFs: 72/43848 0%
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Info: Packing IOs..
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 40 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0x16931407
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Info: Device utilisation:
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Info: TRELLIS_IO: 18/ 245 7%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 0/ 108 0%
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Info: MULT18X18D: 0/ 72 0%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 72/ 43848 0%
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Info: TRELLIS_COMB: 74/ 43848 0%
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Info: TRELLIS_RAMW: 8/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 57 cells, random placement wirelen = 5935.
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Info: at initial placer iter 0, wirelen = 1543
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Info: at initial placer iter 1, wirelen = 1188
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Info: at initial placer iter 2, wirelen = 1004
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Info: at initial placer iter 3, wirelen = 976
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Info: Running main analytical placer, max placement attempts per cell = 10000.
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Info: at iteration #1, type ALL: wirelen solved = 974, spread = 1053, legal = 1110; time = 0.00s
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Info: HeAP Placer Time: 0.02s
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Info: of which solving equations: 0.00s
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Info: of which spreading cells: 0.00s
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Info: of which strict legalisation: 0.00s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 14, wirelen = 1110
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Info: at iteration #5: temp = 0.000000, timing cost = 33, wirelen = 896
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Info: at iteration #10: temp = 0.000000, timing cost = 28, wirelen = 896
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Info: at iteration #10: temp = 0.000000, timing cost = 26, wirelen = 885
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Info: SA placement time 0.01s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 456.83 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.94 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.36 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 10311, 10383) |**+
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Info: [ 10383, 10455) |****+
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Info: [ 10455, 10527) |
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Info: [ 10527, 10599) |
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Info: [ 10599, 10671) |****+
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Info: [ 10671, 10743) |**+
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Info: [ 10743, 10815) |****+
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Info: [ 10815, 10887) |*****************************+
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Info: [ 10887, 10959) |**+
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Info: [ 10959, 11031) |**********************+
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Info: [ 11031, 11103) |*****************************+
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Info: [ 11103, 11175) |***********************+
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Info: [ 11175, 11247) |************************************************************
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Info: [ 11247, 11319) |
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Info: [ 11319, 11391) |****************+
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Info: [ 11391, 11463) |****+
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Info: [ 11463, 11535) |**************+
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Info: [ 11535, 11607) |+
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Info: [ 11607, 11679) |****+
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Info: [ 11679, 11751) |*******+
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Info: Checksum: 0x1b42f28c
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 531 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 667 | 126 533 | 126 533 | 0| 0.05 0.05|
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Info: Routing complete.
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Info: Router1 time 0.05s
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Info: Checksum: 0x96dc7282
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source dut.GEN_SLOT[1].rd_data_reg_TRELLIS_FF_Q_3.Q
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Info: routing 0.85 1.25 Net rd_data_flat[65] (37,42) -> (36,41)
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Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_ALUT_LUT4_Z.C
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Info: Defined in:
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Info: hardware/v2/nms/rtl/nms_weight_direct.v:28.50-28.62
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Info: logic 0.18 1.43 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_ALUT_LUT4_Z.F
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Info: routing 0.00 1.43 Net chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_ALUT (36,41) -> (36,41)
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Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_BLUT_LUT4_Z.F1
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24
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Info: logic 0.13 1.55 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_BLUT_LUT4_Z.OFX
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Info: routing 0.46 2.02 Net chk_TRELLIS_FF_Q_DI[1] (36,41) -> (37,41)
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Info: Sink chk_TRELLIS_FF_Q_1.M
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Info: setup 0.00 2.02 Source chk_TRELLIS_FF_Q_1.M
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Info: 0.70 ns logic, 1.32 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source seed[6]$tr_io.O
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Info: routing 2.93 2.93 Net seed[6]$TRELLIS_IO_IN (42,0) -> (38,41)
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Info: Sink seed_LUT4_B_Z_LUT4_Z_3.B
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:14.23-14.27
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Info: logic 0.18 3.11 Source seed_LUT4_B_Z_LUT4_Z_3.F
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Info: routing 0.12 3.23 Net seed_LUT4_B_Z[6] (38,41) -> (38,41)
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Info: Sink lfsr_TRELLIS_FF_Q_1.DI
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Info: setup 0.00 3.23 Source lfsr_TRELLIS_FF_Q_1.DI
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Info: 0.18 ns logic, 3.05 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_5.Q
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Info: routing 2.87 3.26 Net checksum[5]$TRELLIS_IO_OUT (38,44) -> (42,0)
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Info: Sink checksum[5]$tr_io.I
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:40.15-40.18
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Info: 0.40 ns logic, 2.87 ns routing
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 496.03 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.23 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.26 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 10484, 10550) |*
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Info: [ 10550, 10616) |**
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Info: [ 10616, 10682) |***********
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Info: [ 10682, 10748) |**********
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Info: [ 10748, 10814) |********
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Info: [ 10814, 10880) |*********
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Info: [ 10880, 10946) |***
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Info: [ 10946, 11012) |************
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Info: [ 11012, 11078) |******
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Info: [ 11078, 11144) |**************************************
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Info: [ 11144, 11210) |*********************
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Info: [ 11210, 11276) |********************
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Info: [ 11276, 11342) |*******************************
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Info: [ 11342, 11408) |***********************************************
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Info: [ 11408, 11474) |************
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Info: [ 11474, 11540) |***************************
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Info: [ 11540, 11606) |*********
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Info: [ 11606, 11672) |*
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Info: [ 11672, 11738) |************
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Info: [ 11738, 11804) |****
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Info: Program finished normally.
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