Info: Logic utilisation before packing: Info: Total LUT4s: 72/43848 0% Info: logic LUTs: 24/43848 0% Info: carry LUTs: 0/43848 0% Info: RAM LUTs: 32/ 5481 0% Info: RAMW LUTs: 16/10962 0% Info: Total DFFs: 72/43848 0% Info: Packing IOs.. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 40 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0x16931407 Info: Device utilisation: Info: TRELLIS_IO: 18/ 245 7% Info: DCCA: 1/ 56 1% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 72/ 43848 0% Info: TRELLIS_COMB: 74/ 43848 0% Info: TRELLIS_RAMW: 8/ 5481 0% Info: Placed 0 cells based on constraints. Info: Creating initial analytic placement for 57 cells, random placement wirelen = 5935. Info: at initial placer iter 0, wirelen = 1543 Info: at initial placer iter 1, wirelen = 1188 Info: at initial placer iter 2, wirelen = 1004 Info: at initial placer iter 3, wirelen = 976 Info: Running main analytical placer, max placement attempts per cell = 10000. Info: at iteration #1, type ALL: wirelen solved = 974, spread = 1053, legal = 1110; time = 0.00s Info: HeAP Placer Time: 0.02s Info: of which solving equations: 0.00s Info: of which spreading cells: 0.00s Info: of which strict legalisation: 0.00s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 14, wirelen = 1110 Info: at iteration #5: temp = 0.000000, timing cost = 33, wirelen = 896 Info: at iteration #10: temp = 0.000000, timing cost = 28, wirelen = 896 Info: at iteration #10: temp = 0.000000, timing cost = 26, wirelen = 885 Info: SA placement time 0.01s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 456.83 MHz (PASS at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.94 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 4.36 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 10311, 10383) |**+ Info: [ 10383, 10455) |****+ Info: [ 10455, 10527) | Info: [ 10527, 10599) | Info: [ 10599, 10671) |****+ Info: [ 10671, 10743) |**+ Info: [ 10743, 10815) |****+ Info: [ 10815, 10887) |*****************************+ Info: [ 10887, 10959) |**+ Info: [ 10959, 11031) |**********************+ Info: [ 11031, 11103) |*****************************+ Info: [ 11103, 11175) |***********************+ Info: [ 11175, 11247) |************************************************************ Info: [ 11247, 11319) | Info: [ 11319, 11391) |****************+ Info: [ 11391, 11463) |****+ Info: [ 11463, 11535) |**************+ Info: [ 11535, 11607) |+ Info: [ 11607, 11679) |****+ Info: [ 11679, 11751) |*******+ Info: Checksum: 0x1b42f28c Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 531 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 667 | 126 533 | 126 533 | 0| 0.05 0.05| Info: Routing complete. Info: Router1 time 0.05s Info: Checksum: 0x96dc7282 Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: type curr total name Info: clk-to-q 0.40 0.40 Source dut.GEN_SLOT[1].rd_data_reg_TRELLIS_FF_Q_3.Q Info: routing 0.85 1.25 Net rd_data_flat[65] (37,42) -> (36,41) Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_ALUT_LUT4_Z.C Info: Defined in: Info: hardware/v2/nms/rtl/nms_weight_direct.v:28.50-28.62 Info: logic 0.18 1.43 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_ALUT_LUT4_Z.F Info: routing 0.00 1.43 Net chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_ALUT (36,41) -> (36,41) Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_BLUT_LUT4_Z.F1 Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24 Info: logic 0.13 1.55 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_BLUT_LUT4_Z.OFX Info: routing 0.46 2.02 Net chk_TRELLIS_FF_Q_DI[1] (36,41) -> (37,41) Info: Sink chk_TRELLIS_FF_Q_1.M Info: setup 0.00 2.02 Source chk_TRELLIS_FF_Q_1.M Info: 0.70 ns logic, 1.32 ns routing Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: type curr total name Info: source 0.00 0.00 Source seed[6]$tr_io.O Info: routing 2.93 2.93 Net seed[6]$TRELLIS_IO_IN (42,0) -> (38,41) Info: Sink seed_LUT4_B_Z_LUT4_Z_3.B Info: Defined in: Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:14.23-14.27 Info: logic 0.18 3.11 Source seed_LUT4_B_Z_LUT4_Z_3.F Info: routing 0.12 3.23 Net seed_LUT4_B_Z[6] (38,41) -> (38,41) Info: Sink lfsr_TRELLIS_FF_Q_1.DI Info: setup 0.00 3.23 Source lfsr_TRELLIS_FF_Q_1.DI Info: 0.18 ns logic, 3.05 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': Info: type curr total name Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_5.Q Info: routing 2.87 3.26 Net checksum[5]$TRELLIS_IO_OUT (38,44) -> (42,0) Info: Sink checksum[5]$tr_io.I Info: Defined in: Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:40.15-40.18 Info: 0.40 ns logic, 2.87 ns routing Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 496.03 MHz (PASS at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.23 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 3.26 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 10484, 10550) |* Info: [ 10550, 10616) |** Info: [ 10616, 10682) |*********** Info: [ 10682, 10748) |********** Info: [ 10748, 10814) |******** Info: [ 10814, 10880) |********* Info: [ 10880, 10946) |*** Info: [ 10946, 11012) |************ Info: [ 11012, 11078) |****** Info: [ 11078, 11144) |************************************** Info: [ 11144, 11210) |********************* Info: [ 11210, 11276) |******************** Info: [ 11276, 11342) |******************************* Info: [ 11342, 11408) |*********************************************** Info: [ 11408, 11474) |************ Info: [ 11474, 11540) |*************************** Info: [ 11540, 11606) |********* Info: [ 11606, 11672) |* Info: [ 11672, 11738) |************ Info: [ 11738, 11804) |**** Info: Program finished normally.