micheleandClaude Sonnet 5
a20f1ecd73
Adds the consolidated, authoritative record for the 64MB memory upgrade and N_SLOTS=8 investigation (real datasheet family comparison, RTL changes, both timing fixes with real P&R data, honest N=8 clock- closure status, real DigiKey availability for the frozen part). Marks HARDWARE_FREEZE.md/MEMORY_ARCHITECTURE.md/PRE_PCB_VERIFICATION.md/ PRE_PCB_CLOSURE_4POINT.md's own SDRAM-specific sections as superseded (they describe the previous 8MB AS4C4M16SA-6TIN part) with pointers to the new document, rather than rewriting each individually. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
119 lines
7.2 KiB
Markdown
119 lines
7.2 KiB
Markdown
# FPGA-Neural V2 — HARDWARE FREEZE (FASE #1, single external SDRAM)
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**PARTIALLY SUPERSEDED (DEC-0039).** The SDRAM part number below
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(AS4C4M16SA-6TIN, 8MB) was upgraded to **AS4C32M16SB-7BIN (64MB)**,
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and N_PROCESSORS=8 is no longer merely a "future evolution" — it is
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now real, synthesized, P&R-verified (functionally correct, with a
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disclosed, real 64MHz timing-closure gap at 5/8 tested seeds). See
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`MEMORY_UPGRADE_64MB_N8.md` for the current, authoritative state. The
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rest of this document (Neural Processor, dataflow architecture) is
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still accurate.
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## Frozen reference configuration
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```
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FPGA: LFE5U-45F-8BG381, ECP5U, speed grade -8
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Neural Processor: P_IN=8, INT8 operands, INT32 accumulator,
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8 parallel MAC, balanced adder tree (neural_processor.v,
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UNCHANGED since before this freeze)
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Multiprocessor: N_PROCESSORS=4 (N4/P8 is the frozen reference; N2 also
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validated; N8 is a FUTURE EVOLUTION, not part of this freeze)
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Architecture: Neural Multiprocessor -> Dataflow -> Neural Director ->
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Dependency Manager -> Memory Manager -> streaming tile
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delivery (STEP13 architecture, intact, unchanged)
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External memory: ONE SDRAM ONLY -- Alliance Memory AS4C4M16SA-6TIN,
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serving weights, activations, AND results (DEC-0031/
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0032/0033/0034). No PSRAM, no second memory device.
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Weight path: PACK128 (BURST_LEN=8, N_ENTRIES=4 cache, STEP18/STEP19)
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Target clock: 80 MHz minimum (real oscillator/PLL source: OPEN, see
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CLOCK_ARCHITECTURE.md)
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V1: golden/reference implementation, untouched (confirmed:
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zero modifications; V2 no longer instantiates ANY V1
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RTL at all, since psram_controller.v was removed from
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the physical path -- DEC-0034)
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Frozen top-level: nms_neural_multiprocessor_sdram_unified
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(hardware/v2/nms/rtl/nms_neural_multiprocessor_sdram_unified.v)
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```
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N4/P8 is the frozen V2.0 hardware reference. This does not mean N4 is
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the final or maximum architecture — N8, higher clocks, or new datapath
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ideas are explicitly FUTURE EVOLUTIONS, out of scope for this freeze.
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## Repository audit summary
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Full detail: see the audit performed for this step (repository
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structure, V1/V2 boundary, top-level candidates, dead-code
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classification, PSRAM-dependency confirmation, LPF/docs/scripts
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inventory). Key findings:
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- `hardware/v1/**`: complete, self-contained, untouched. Real
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synthesized/certified golden reference (`spi_neuron_top.v`).
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- `hardware/v2/rtl/` + `hardware/v2/nms/rtl/`: the frozen top-level
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(`nms_neural_multiprocessor_sdram_unified.v`) instantiates
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`nms_dataflow_core_sdram.v`, `sdram_unified_backend.v` (STEP19, new),
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`sdram_controller.v`, `nms_memory_manager_stream_wide.v`,
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`weight_prefetch_engine_wide.v`, `nms_activation_replicated.v`,
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`nms_activation_fill_ctrl_v3.v`, `nms_weight_packed.v`,
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`dependency_manager.v`, `neural_director.v`, `neural_processor.v`,
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`slot_mem_arbiter.v`, `slot_mem_arbiter_wide.v`, `prefetch_engine.v`
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— **zero V1 files**, confirmed by successful lint/synthesis with no
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V1 RTL in the file list.
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- Every other `nms_neural_multiprocessor_*.v`/`nms_dataflow_core_*.v`
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variant (plain, `_pf`, `_stream`, `_actfix`, `_actfix2`, `_dual32`,
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`_sdram`, `_sdram_pack128`) is real, historical, superseded-but-
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documented project experiment history — dead relative to the frozen
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top, NOT deleted (each remains the subject of its own STEP report).
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- `hardware/v2/constraints/` was empty before this step; now contains
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`v2_unified.lpf` (partial — see PINOUT.md).
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- The referenced sibling pinout repository (`../basic-ecp5-pcb`) does
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not exist on disk, BUT the real Lattice pinout CSV itself
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(`FPGA-SC-02034-3-0-ECP5U-45-Pinout.csv`, rev 3.0) is present at
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`~/Downloads/` and was found during this step's own pre-commit
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review, with a real summary already at `docs/pinouts.md` (repo
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root). This corrected an earlier draft of this freeze that
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wrongly assumed no real pinout data existed — see PINOUT.md.
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## Status table
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| Area | Status | Evidence | Blocker |
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|---|---|---|---|
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| RTL | PASS | Strict Verilator lint (latches/multi-driver/comb-loops/case-completeness): zero findings across the full frozen hierarchy | No |
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| Simulation | PASS | Isolated `tb_sdram_controller.v` (461/461, 9 freq/burst configs), isolated `tb_sdram_unified_backend.v` (40/40) | No |
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| Bit-exact | PASS | Full N=4 AND N=2 D-Stress (256/256 neurons each), golden software model comparison | No |
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| SDRAM | PASS | Real init/refresh/read/write/burst/masked-write, 40 real AUTO REFRESH events interleaved with zero corruption across a ~50,000-cycle run | No |
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| Synthesis | PASS | Real Yosys 0.68+post synthesis, N=4: TRELLIS_FF=6425, TRELLIS_COMB=6023, MULT18X18D=32, DP16KD=0 | No |
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| P&R | PASS (fits) | Real nextpnr-ecp5 0.11.1, TRELLIS_IO=149/245 (fits with headroom) | No |
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| Timing | **MARGINAL** | 8 real seeds: 66.97/74.00/74.45/74.92/79.23/79.53/79.80/81.84 MHz — only 1/8 ≥80MHz | **CRITICAL** |
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| Pinout | PARTIAL | 39/149 signals real, sourced, P&R-verified (clk/rst + full 37-signal SDRAM bus); 110-signal host bus unassigned | **BLOCKER (host bus only)** |
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| Clock | INCOMPLETE | Single-clock-domain RTL confirmed (no CDC); no PLL exists; oscillator-vs-PLL decision not made | **CRITICAL** |
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| Power | INCOMPLETE | Real rail voltages known from datasheets; no regulator selection, no current budget | OPEN |
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| Configuration | INCOMPLETE | Standard ECP5 JTAG/config pins identified; no flash part chosen, no V2 config LPF beyond the partial `v2_unified.lpf` | OPEN |
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| Host | INCOMPLETE | 110-pin raw parallel bus exists at the RTL boundary; no physical protocol, no serializer RTL | **BLOCKER** |
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| PCB | NOT READY | See SCHEMATIC_READINESS.md's own checklist | Multiple (host, pinout, power) |
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| Bring-up | READY (procedure only) | FIRST_POWER_ON.md defines the full 12-step test sequence | Cannot execute until host/pinout blockers close |
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## Single-SDRAM verification (this step's own core mandate)
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- PSRAM dependency: **REMOVED** — confirmed by successful synthesis/
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P&R with zero V1 files in the compile list, and a real, measured
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45-pin I/O reduction (194→149/245 TRELLIS_IO) exactly matching the
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removed PSRAM interface's own pin count.
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- Weights/activations/results: **all confirmed sharing the single
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physical SDRAM**, real bit-exact traffic at three distinct,
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non-overlapping memory-map regions, simultaneously, under real N=4
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contention (see MEMORY_ARCHITECTURE.md).
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- Real bugs found and fixed during this consolidation (ERR-0023): a
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full deadlock and a subsequent off-by-one data-shift bug in the new
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arbitration logic, both caught via full-system (not merely isolated)
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testing before being accepted — see errors.log for the complete
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root-cause writeups.
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## Deliverables produced by this step
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`HARDWARE_FREEZE.md` (this file), `CHIP_READINESS.md`,
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`MEMORY_ARCHITECTURE.md`, `PINOUT.md`, `POWER_ARCHITECTURE.md`,
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`CLOCK_ARCHITECTURE.md`, `SCHEMATIC_READINESS.md`,
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`FIRST_POWER_ON.md`, `OPEN_ITEMS.md` (all under `hardware/v2/docs/`),
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plus `hardware/v2/constraints/v2_unified.lpf` and new RTL/testbenches
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under `hardware/v2/nms/rtl/` and `hardware/v2/nms/sim/`.
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