FPGA-Neural

T

micheleandClaude Sonnet 5 fd6cc7a2fa docs: log final re-verified real P&R signoff after SPI fix + reg file (EXP-0076)

Confirms EXP-0075's fixes (SPI physical-layer bug, register file,
real pin constraints) don't regress timing: WNS +0.056ns (slightly
better than EXP-0074's +0.040ns), 0 failing endpoints, 5173 LUTs,
16 DSP48E1. User confirmed board plan: both JTAG and Master SPI boot
(Winbond W25Q32JVSSIQ config flash, verified in-stock on LCSC) will
be present on the custom PCB.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-19 19:22:32 +02:00

benchmark_results

feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results

2026-09-02 19:48:03 +02:00

docs

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze

2026-09-07 05:30:17 +02:00

hardware

docs: log final re-verified real P&R signoff after SPI fix + reg file (EXP-0076)

2026-09-19 19:22:32 +02:00

sim

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze