micheleandClaude Sonnet 5
eb0b0f9170
Adds hardware/v2/docs/PRE_PCB_VERIFICATION.md as the single authoritative pre-schematic verification record: RTL/ERR-0025/ regression re-verification, clock/reset, synthesis/P&R re-audit, setup/hold timing status, the real SDRAM datasheet-parameter audit table (Alliance Memory AS4C4M16SA-6TIN Table 17), SPI host bridge protocol documentation, FPGA power/pinout tables, first-board bring-up and benchmark status, and cross-domain consistency audit. Freezes the FPGA configuration flash: Winbond W25Q32JVSSIQ (32Mbit, SOIC-8, 2.7-3.6V, standard SPI, ECP5 Master-SPI-boot compatible) -- this was the one section-11 item the governing mandate required not be left OPEN. Marks CHIP_READINESS.md/OPEN_ITEMS.md/PINOUT.md/CLOCK_ARCHITECTURE.md/ POWER_ARCHITECTURE.md/SCHEMATIC_READINESS.md as superseded (they predate the SPI host bridge, PLL, and this session's SDRAM datasheet audit) with pointers to the new consolidated document, rather than rewriting each individually. Updates the V2 LaTeX datasheet's status/roadmap chapter to reflect the SDRAM datasheet audit and configuration-flash decisions, rebuilds the PDF (clean compile, 16 pages). Classification: PRE-PCB VERIFIED. Schematic and PCB implementation remain user-owned and not started. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
58 lines
2.6 KiB
TeX
58 lines
2.6 KiB
TeX
\chapter{Chip readiness and roadmap}
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\label{ch:status}
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\section{Precise readiness checklist}
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Per this project's own standing rule: no item below is checked unless
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genuinely verified; no OPEN item is masked as a future enhancement.
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\begin{tabularx}{\textwidth}{L{6.4cm}Y}
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\toprule
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\rowh \thd{Item} & \thd{Status} \\
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\midrule
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RTL frozen, zero V1 dependency & \OK \\
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\rowa Bit-exact regression (N=2, N=4) & \OK\ (256/256, Verilator) \\
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Real SPI host interface, end-to-end & \OK\ (11/11, zero regression) \\
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\rowa SDRAM validation (init/refresh/masked-write) & \OK \\
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Synthesis (final top, real Yosys run) & \OK\ (0 CHECK-pass problems) \\
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\rowa Place\&route (8 real seeds) & \OK\ (8/8 fit, routed, zero errors) \\
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Timing closure @ 64\,MHz & \OK\ (8/8 seeds PASS, worst 68.51\,MHz) \\
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\rowa Final pinout (44/44 top-level signals) & \OK\ (real balls, P\&R-confirmed) \\
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Hold-time analysis & OPEN (tool limitation, see PRE\_PCB\_VERIFICATION.md \S6) \\
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\rowa Power: rail voltages & OK (real datasheet values) \\
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Power: regulator selection / current budget & OPEN \\
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\rowa SDRAM datasheet-parameter cross-check & \OK\ (real AS4C4M16SA-6TIN Table 17 audit; found and fixed ERR-0026, tMRD unit mismatch) \\
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Configuration flash selection & \OK\ (Winbond \code{W25Q32JVSSIQ}, SOIC-8, frozen) \\
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\rowa Real KiCad schematic + ERC & NOT STARTED \\
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PCB layout & NOT STARTED \\
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\rowa BOM (sourced, purchasable parts) & NOT STARTED \\
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Physical board bring-up & NOT APPLICABLE (no board fabricated) \\
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\rowa Real embedded-target (ESP32) software baseline & NOT AVAILABLE (no hardware) \\
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\bottomrule
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\end{tabularx}
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\section{Final answer}
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\begin{center}
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\Large\bfseries\color{fnRed}NOT SILICON READY
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\end{center}
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The RTL, simulation, synthesis, place-and-route, timing, and pinout
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gates are all genuinely closed for the final board-level top. The
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remaining, real, disclosed blockers are entirely in the physical
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domain -- schematic capture, PCB layout, sourced BOM, and (necessarily)
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physical fabrication and bring-up -- none of which were claimed
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complete in this revision.
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\section{Roadmap}
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\begin{itemize}
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\item Real KiCad schematic capture + ERC.
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\item PCB layout (BGA escape, SDRAM routing, power integrity).
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\item Sourced, purchasable BOM (regulators, configuration flash,
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connectors).
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\item Real power current-budget estimate against the actual
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synthesized netlist.
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\item First physical board fabrication and the 15-step bring-up
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procedure already documented in \code{FIRST\_POWER\_ON.md}.
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\item A real embedded-target (ESP32-class) software baseline, once
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hardware is available, to replace this revision's honestly-labeled
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desktop-CPU illustrative comparison.
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\end{itemize}
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