\chapter{Chip readiness and roadmap}
\label{ch:status}

\section{Precise readiness checklist}
Per this project's own standing rule: no item below is checked unless
genuinely verified; no OPEN item is masked as a future enhancement.

\begin{tabularx}{\textwidth}{L{6.4cm}Y}
\toprule
\rowh \thd{Item} & \thd{Status} \\
\midrule
RTL frozen, zero V1 dependency & \OK \\
\rowa Bit-exact regression (N=2, N=4) & \OK\ (256/256, Verilator) \\
Real SPI host interface, end-to-end & \OK\ (11/11, zero regression) \\
\rowa SDRAM validation (init/refresh/masked-write) & \OK \\
Synthesis (final top, real Yosys run) & \OK\ (0 CHECK-pass problems) \\
\rowa Place\&route (8 real seeds) & \OK\ (8/8 fit, routed, zero errors) \\
Timing closure @ 64\,MHz & \OK\ (8/8 seeds PASS, worst 68.51\,MHz) \\
\rowa Final pinout (44/44 top-level signals) & \OK\ (real balls, P\&R-confirmed) \\
Hold-time analysis & OPEN (tool limitation, see PRE\_PCB\_VERIFICATION.md \S6) \\
\rowa Power: rail voltages & OK (real datasheet values) \\
Power: regulator selection / current budget & OPEN \\
\rowa SDRAM datasheet-parameter cross-check & \OK\ (real AS4C4M16SA-6TIN Table 17 audit; found and fixed ERR-0026, tMRD unit mismatch) \\
Configuration flash selection & \OK\ (Winbond \code{W25Q32JVSSIQ}, SOIC-8, frozen) \\
\rowa Real KiCad schematic + ERC & NOT STARTED \\
PCB layout & NOT STARTED \\
\rowa BOM (sourced, purchasable parts) & NOT STARTED \\
Physical board bring-up & NOT APPLICABLE (no board fabricated) \\
\rowa Real embedded-target (ESP32) software baseline & NOT AVAILABLE (no hardware) \\
\bottomrule
\end{tabularx}

\section{Final answer}
\begin{center}
\Large\bfseries\color{fnRed}NOT SILICON READY
\end{center}
The RTL, simulation, synthesis, place-and-route, timing, and pinout
gates are all genuinely closed for the final board-level top. The
remaining, real, disclosed blockers are entirely in the physical
domain -- schematic capture, PCB layout, sourced BOM, and (necessarily)
physical fabrication and bring-up -- none of which were claimed
complete in this revision.

\section{Roadmap}
\begin{itemize}
\item Real KiCad schematic capture + ERC.
\item PCB layout (BGA escape, SDRAM routing, power integrity).
\item Sourced, purchasable BOM (regulators, configuration flash,
  connectors).
\item Real power current-budget estimate against the actual
  synthesized netlist.
\item First physical board fabrication and the 15-step bring-up
  procedure already documented in \code{FIRST\_POWER\_ON.md}.
\item A real embedded-target (ESP32-class) software baseline, once
  hardware is available, to replace this revision's honestly-labeled
  desktop-CPU illustrative comparison.
\end{itemize}