micheleandClaude Sonnet 5
d6376e8f2a
Real synthesis and place-and-route of the actual final board-level
top (fpga_neural_v2_top.v -- SPI bridge, real EHXPLLL, reset_sync,
compute+memory core), against a real, fully ball-assigned LPF. Also
ports the V2 datasheet to LaTeX using V1's own preamble/macros/
typography, and records a real (non-ESP32, honestly labeled) software
reference comparison.
Synthesis (Yosys, real run): 0 CHECK-pass problems, 38 unique warnings
(43 total), all matching this project's own previously-reviewed benign
set (neural_processor.v's known genvar multi-driver artifact, small-
array-to-register unrolling, the real SDRAM DQ tristate bus) -- no new
warnings from the SPI bridge, PLL, or reset synchronizer.
TRELLIS_FF=6322, TRELLIS_COMB=7084, MULT18X18D=32, EHXPLLL=1 (real PLL
confirmed present), DP16KD=0 (all small SRAMs -> distributed RAM).
Place-and-route (nextpnr-ecp5, real runs, 8 seeds, new
v2_board_top.lpf with all 44 top-level signals ball-assigned from the
official Lattice pinout CSV -- no placeholders): 8/8 PASS at 64MHz.
Worst 68.51MHz (seed 4), best 74.17MHz (seed 7), mean 71.16MHz. Zero
unrouted nets, zero placement/routing errors, TRELLIS_IO=44/245 (17%).
Critical path alternates between dependency_manager's own priority
encoder and sdram_unified_backend's own weight-cache hit-index logic,
matching this project's own prior documented timing investigations --
not a new defect.
New: hardware/v2/constraints/v2_board_top.lpf (final LPF, supersedes
v2_unified.lpf for the board-level top), hardware/v2/reports/
step_final_{synthesis,pnr_worst_seed4,timing}.* (raw evidence),
hardware/v2/docs/DatasheetLatex/ (V2 datasheet, real LaTeX build,
16 pages, visually inspected, ported from hardware/v1/docs/
DatasheetLatex/'s own preamble and macros).
Real, honestly-labeled software baseline: the D-Stress arithmetic
(256 neurons x 128 INT8 MACs) compiled and run on THIS development
machine (Apple M4, arm64, NOT an embedded target, NOT ESP32) --
1.28us/inference, included in the datasheet with an explicit
disclosure that no physical ESP32 hardware was available for a real
embedded-target comparison.
Remaining, disclosed, NOT-yet-closed items (this commit does NOT
claim silicon readiness): real KiCad schematic + ERC, PCB layout,
sourced BOM, real power current-budget estimate, SDRAM-datasheet-
parameter cross-check, configuration-flash selection, and (necessarily)
physical fabrication/bring-up. See hardware/v2/docs/DatasheetLatex/
chapters/08-status-roadmap.tex for the complete, itemized checklist.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
68 lines
3.0 KiB
TeX
68 lines
3.0 KiB
TeX
\chapter{Benchmarks}
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\section{Internal benchmark: D-Stress workload}
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256 independent neurons, 128 inputs each (16 tiles of \code{P\_IN}=8),
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one shared activation vector -- the project's own existing, reused
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benchmark, run against the final, frozen RTL via Verilator.
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\begin{tabularx}{\textwidth}{L{2cm}L{2.4cm}L{2.4cm}Y}
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\toprule
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\rowh \thd{Config} & \thd{Cycles} & \thd{Correctness} & \thd{Latency @ 64\,MHz} \\
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\midrule
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N=2 & 49\,788 & 256/256 \PASS & 777.9\,\textmu s \\
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\rowa N=4 & 49\,771 & 256/256 \PASS & 777.7\,\textmu s \\
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\bottomrule
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\end{tabularx}
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Cycle counts are \textbf{simulation-verified} (Verilator, bit-exact)
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and unchanged before/after the ERR-0025 read-timing fix. Latency at
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64\,MHz is a \textbf{derived} figure (cycles~/~clock), not an
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independently re-simulated wall-clock measurement, and is not a
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measured-hardware number (no fabricated board exists).
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N=4 barely improves over N=2 on this specific workload
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($49\,771$ vs.\ $49\,788$ cycles) because the workload is dominated by
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shared-SDRAM and shared-activation-fill traffic, not by raw MAC
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throughput -- consistent with this project's own prior STEP17/18
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memory-bound-vs-compute-bound findings, not a new anomaly.
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\section{Host-interface pacing benchmark}
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The board-level SPI smoke test (\S\ref{sec:host}) exercises single-job,
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back-to-back, and gap-swept (100\,ns/5\,000\,ns/50\,000\,ns/$\sim$85\,\textmu s)
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dispatch patterns -- all 11/11 bit-exact -- establishing that realistic
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host pacing does not, itself, change correctness (only the STEP19-era
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registered-read bug did, and that is fixed).
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\section{Software reference comparison}
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\textbf{No physical ESP32 (or other embedded MCU) hardware is
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available in this environment.} A real ESP32 benchmark was
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\emph{not} performed, and no ESP32 number is estimated or invented
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here -- this is a disclosed OPEN item, not a claimed result.
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As an honest, clearly-labeled illustrative data point only, the
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identical D-Stress arithmetic (256 neurons $\times$ 128 INT8 MACs,
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ReLU + INT8 saturate) was compiled (\code{cc~-O2}) and run on the
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\emph{development machine itself} (Apple M4, arm64 -- \textbf{not}
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an embedded target):
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\begin{tabularx}{\textwidth}{L{4.4cm}Y}
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\toprule
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\rowh \thd{Metric} & \thd{Value} \\
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\midrule
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Platform & Apple M4 (arm64), \code{cc -O2}, single-threaded scalar C \\
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\rowa Latency, full 256-neuron batch & 1.28\,\textmu s \\
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Throughput & $2.56\times10^{10}$ MAC/s \\
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\bottomrule
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\end{tabularx}
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On this specific, tiny workload, a modern, auto-vectorizing,
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multi-GHz superscalar CPU outperforms the current FPGA design's
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\emph{simulated} cycle count in raw latency. This is reported
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honestly rather than omitted: FPGA-Neural V2's real value proposition
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is a deterministic, low-power, standalone SDRAM-attached accelerator
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for hosts that do \emph{not} have this class of CPU (e.g.\ an
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ESP32-class microcontroller) -- not a claim of outperforming a
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desktop-class processor on this workload size. A real, meaningful
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software baseline for THAT comparison requires the actual embedded
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target hardware, which remains unavailable this revision.
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