micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
70 lines
3.0 KiB
Verilog
70 lines
3.0 KiB
Verilog
// ============================================================
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// Neural Memory System (NMS) -- STEP 3: banked activation SRAM
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// contention model. SIMULATION-ONLY, NEVER SYNTHESIZED.
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//
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// Models a single shared activation vector striped across N_BANKS
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// banks by tile index (bank = tile_idx % N_BANKS). Each bank can serve
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// ONE DISTINCT address per cycle, but BROADCASTS that address's data
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// to every requester currently wanting it (a shared-producer, many-
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// consumer read costs exactly one read, not one per consumer -- see
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// hardware/v2/nms/rtl.. STEP2's own architecture.log note and the
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// user's own NMS spec §11). A cycle where two+ requesters mapped to
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// the same bank want DIFFERENT tile indices serves only one of them
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// (lowest-index requester wins this round); the others simply retry
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// next cycle (idempotent -- an ideal SRAM read has no state cost).
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//
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// Read latency is modeled as ZERO cycles (grant and data-available
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// are the same cycle) -- this file isolates the BANK CONTENTION
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// question specifically, decoupled from backing-store latency, which
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// STEP1 (hardware/v2/nms/rtl/ideal_memory_model.v, EXP-0017) already
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// characterized separately. Fill-from-PSRAM is out of scope here too
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// (the vector is assumed already resident, i.e. steady-state
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// consumption after prefetch -- the question this file answers is
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// "does the on-chip organization itself let N_SLOTS scale", not
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// "how do we hide PSRAM latency" (already answered by STEP1).
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// ============================================================
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module ideal_banked_activation #(
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parameter NREQ = 4,
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parameter N_BANKS = 2,
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parameter AW = 32
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)(
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input [NREQ-1:0] req_valid,
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input [NREQ*AW-1:0] req_addr_flat,
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output reg [NREQ-1:0] ack
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);
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integer b, i;
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reg [AW-1:0] req_addr [0:NREQ-1];
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reg [AW-1:0] served_addr;
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reg have_served;
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integer bank_of_i;
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always @* begin
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for (i = 0; i < NREQ; i = i + 1)
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req_addr[i] = req_addr_flat[i*AW +: AW];
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ack = {NREQ{1'b0}};
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for (b = 0; b < N_BANKS; b = b + 1) begin
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have_served = 1'b0;
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served_addr = {AW{1'b0}};
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// first pass: lowest-index valid requester in this bank sets
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// the address served this cycle
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for (i = 0; i < NREQ; i = i + 1) begin
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bank_of_i = req_addr[i] % N_BANKS;
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if (req_valid[i] && (bank_of_i == b) && !have_served) begin
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served_addr = req_addr[i];
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have_served = 1'b1;
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end
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end
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// second pass: broadcast ack to every requester in this bank
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// that wants the SAME address (free, one read serves all)
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if (have_served) begin
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for (i = 0; i < NREQ; i = i + 1) begin
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bank_of_i = req_addr[i] % N_BANKS;
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if (req_valid[i] && (bank_of_i == b) && (req_addr[i] == served_addr))
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ack[i] = 1'b1;
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end
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end
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end
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end
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endmodule
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