micheleandClaude Sonnet 5
8890b0abc2
Real Alliance Memory AS4C4M16SA-6TIN datasheet (Rev 5.0, Table 17) specifies tMRD as a fixed 2-tCK cycle count, not an ns value. sdram_controller.v modeled it via ns_to_cycles(12), which rounded to 2 cycles by coincidence at every previously-tested frequency (100/133/166MHz) but rounds to only 1 cycle at the real 64MHz board target -- an under-provisioned one-time init sequence. Fixed by hardcoding T_MRD=2, matching how CAS_LATENCY is already modeled. Verified zero regression: full 9-config legacy sweep + a new dedicated 64MHz config (461/461 PASS each), N=2/N=4 D-Stress (identical cycle counts), board-level smoke test (11/11 PASS). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v