micheleandClaude Sonnet 5
d6376e8f2a
Real synthesis and place-and-route of the actual final board-level
top (fpga_neural_v2_top.v -- SPI bridge, real EHXPLLL, reset_sync,
compute+memory core), against a real, fully ball-assigned LPF. Also
ports the V2 datasheet to LaTeX using V1's own preamble/macros/
typography, and records a real (non-ESP32, honestly labeled) software
reference comparison.
Synthesis (Yosys, real run): 0 CHECK-pass problems, 38 unique warnings
(43 total), all matching this project's own previously-reviewed benign
set (neural_processor.v's known genvar multi-driver artifact, small-
array-to-register unrolling, the real SDRAM DQ tristate bus) -- no new
warnings from the SPI bridge, PLL, or reset synchronizer.
TRELLIS_FF=6322, TRELLIS_COMB=7084, MULT18X18D=32, EHXPLLL=1 (real PLL
confirmed present), DP16KD=0 (all small SRAMs -> distributed RAM).
Place-and-route (nextpnr-ecp5, real runs, 8 seeds, new
v2_board_top.lpf with all 44 top-level signals ball-assigned from the
official Lattice pinout CSV -- no placeholders): 8/8 PASS at 64MHz.
Worst 68.51MHz (seed 4), best 74.17MHz (seed 7), mean 71.16MHz. Zero
unrouted nets, zero placement/routing errors, TRELLIS_IO=44/245 (17%).
Critical path alternates between dependency_manager's own priority
encoder and sdram_unified_backend's own weight-cache hit-index logic,
matching this project's own prior documented timing investigations --
not a new defect.
New: hardware/v2/constraints/v2_board_top.lpf (final LPF, supersedes
v2_unified.lpf for the board-level top), hardware/v2/reports/
step_final_{synthesis,pnr_worst_seed4,timing}.* (raw evidence),
hardware/v2/docs/DatasheetLatex/ (V2 datasheet, real LaTeX build,
16 pages, visually inspected, ported from hardware/v1/docs/
DatasheetLatex/'s own preamble and macros).
Real, honestly-labeled software baseline: the D-Stress arithmetic
(256 neurons x 128 INT8 MACs) compiled and run on THIS development
machine (Apple M4, arm64, NOT an embedded target, NOT ESP32) --
1.28us/inference, included in the datasheet with an explicit
disclosure that no physical ESP32 hardware was available for a real
embedded-target comparison.
Remaining, disclosed, NOT-yet-closed items (this commit does NOT
claim silicon readiness): real KiCad schematic + ERC, PCB layout,
sourced BOM, real power current-budget estimate, SDRAM-datasheet-
parameter cross-check, configuration-flash selection, and (necessarily)
physical fabrication/bring-up. See hardware/v2/docs/DatasheetLatex/
chapters/08-status-roadmap.tex for the complete, itemized checklist.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
87 lines
4.0 KiB
TeX
87 lines
4.0 KiB
TeX
\chapter{Architecture}
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\section{Compute: Neural Multiprocessor}
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Each of the \code{N\_PROCESSORS} Neural Processors is an independent
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INT8 datapath: \code{P\_IN}=8 parallel multipliers feeding a balanced
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binary adder tree into a 32-bit accumulator, followed by ReLU and INT8
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saturation -- byte-for-byte identical to \code{neural\_processor.v},
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unmodified since before the V2 single-SDRAM freeze. Job dispatch is a
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real dependency-graph pipeline:
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\begin{center}
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\begin{tikzpicture}[node distance=5mm and 6mm,font=\scriptsize]
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\node[fnreg] (host) {SPI host\\bridge};
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\node[fnreg,right=of host] (dm) {Dependency\\Manager};
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\node[fnreg,right=of dm] (dir) {Neural\\Director};
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\node[fnreg,below=of dir] (mm) {Memory Manager\\(per slot)};
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\node[fnreg,left=of mm] (np) {Neural\\Processor};
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\draw[fnarrow] (host) -- (dm);
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\draw[fnarrow] (dm) -- (dir);
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\draw[fnarrow] (dir) -- (mm);
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\draw[fnarrow] (mm) -- (np);
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\end{tikzpicture}
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\end{center}
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The Dependency Manager holds a per-node table (state, required/
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resolved producer count, job descriptor fields) and hands READY nodes
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to the Director one at a time (valid/ready, backpressure-safe). The
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Director allocates the first free processor slot (first-free, not
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load-balanced) and frees it the instant that slot's job completes.
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\section{Unified single-SDRAM memory}
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\begin{center}
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\begin{tikzpicture}[node distance=6mm and 10mm,font=\footnotesize]
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\node[fnblockT,minimum width=50mm,minimum height=20mm] (fpga){};
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\node[anchor=north,font=\bfseries,text=fnDark] at (fpga.north){FPGA};
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\node[fnreg,fill=white] (np) at ([yshift=2mm]fpga.center){4$\times$ Neural Processor};
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\node[fnreg,fill=white,below=2mm of np] (be){Unified SDRAM Backend / Arbiter};
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\node[fnblock,right=16mm of fpga,minimum height=20mm] (ram){\code{AS4C4M16SA-6TIN}\\Weights\\Activations\\Results};
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\draw[fnbus] (fpga.east|-be) -- node[fnlbl,above]{16-bit SDRAM bus} (ram);
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\end{tikzpicture}
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\end{center}
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\code{sdram\_unified\_backend.v} owns exactly one \code{sdram\_
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controller.v} instance and presents two logical ports:
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\begin{itemize}
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\item \textbf{W} (weight fetch): 64-bit, read-only, a 4-entry
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fully-associative ``other half'' cache (round-robin eviction --
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safe under any sizing, since an evicted-too-early entry only costs
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an extra real fetch, never wrong data).
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\item \textbf{AR} (activation fill + result write-back): 16-bit,
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read/write, byte-maskable via real SDR SDRAM DQM semantics
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(\code{lb\_n}/\code{ub\_n}).
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\end{itemize}
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Both ports are, in turn, each arbitrated across the N\_PROCESSORS
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slots by a generic, reused \code{slot\_mem\_arbiter} (a proven,
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pending-latch-based, single-owner-until-ready design used identically
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throughout this project).
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\subsection*{Official V2 memory map}
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\begin{tabularx}{\textwidth}{L{3.2cm}L{3.2cm}Y}
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\toprule
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\rowh \thd{Region} & \thd{Base address} & \thd{Notes} \\
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\midrule
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Weights & \code{0x010000} & 1\,MB-aligned \\
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\rowa Activations & \code{0x200000} & 1\,MB-aligned \\
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Results & \code{0x300000} & 1\,MB-aligned \\
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\bottomrule
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\end{tabularx}
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All three regions are non-overlapping within the single 8\,MB
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(\code{0x000000}--\code{0x7FFFFF}) SDRAM address space. Base addresses
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are host-programmable per job (via \code{WRITE\_JOB}'s own
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\code{x\_base}/\code{w\_base}/\code{result\_addr} fields), not hard-coded
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in the datapath.
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\section{Read-timing discipline (ERR-0025)}
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The shared weight and activation SRAMs (\code{nms\_weight\_packed.v},
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\code{nms\_activation\_replicated.v}) use \textbf{combinational} read
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ports, matching the exact 1-cycle latency assumption of the per-slot
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Memory Manager's own pipelined read-ahead consumer. An earlier,
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registered-read implementation added one uncounted cycle of latency
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that a busy, multi-tile job's own prefetch lead time always absorbed
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invisibly, but that an uncontested single-tile job exposed on its
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first (only) tile -- found and fixed via this revision's own
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board-level SPI integration testing, with zero regression to the
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existing bit-exact regression suite (identical cycle counts before and
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after the fix).
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