micheleandClaude Sonnet 5
dc0b331d3e
Begins the V2 Neural Multiprocessor / Dataflow architecture per docs/v2-description.md, per explicit user request to freeze V1 and start V2 development, copying from V1 what's needed. Scaffold: - hardware/v1/: byte-exact, read-only copy of the current V1 codebase (rtl, testbenches, tools, constraints, a representative subset of synthesis results, and reference docs) -- verified identical via diff/cmp against the live top-level tree before being made filesystem-read-only. The live top-level tree is untouched and remains the project's "production" V1 (see hardware/v1/README.md and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move). - hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/ reports/scripts/logs/docs) plus the full logging system required by the spec (development/architecture/simulation/synthesis/timing/ benchmark/decisions/experiments/errors.log). M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v): - 8-stage pipelined perceptron unit (P_IN=8): input align, 8 multipliers, 3-level adder tree, accumulator, bias+activation, INT8 saturation. Genuine 1-tile/cycle throughput, not just a wider combinational datapath. - 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with 4 baseline states merged into NP_WAIT_OPERANDS -- see decisions.log DEC-0002); valid/ready/data/last stream interfaces per §7. - Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v), covering regular/mixed-sign/extreme-INT8 vectors, both activations, a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile job -- verified with Verilator (see below for why). - Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24 (a user-requested comparison experiment, also bit-exact-verified; see experiments.log EXP-0001/EXP-0002 and benchmark.log). Three real bugs found and resolved during M1 development (full diagnostic record in errors.log): - Two independent, reproducible Icarus Verilog v13.0 scheduling defects (ERR-0001, ERR-0002) that silently produced wrong simulation results for standard sequential Verilog -- confirmed via Verilator 5.050 giving correct results on the same minimal repros. Verilator is now the trusted simulator for hardware/v2/ (decisions.log DEC-0004); Icarus's affected protocol-violation check was removed from the RTL and deferred architecturally to the Neural Director (DEC-0003) rather than chased further. - One real RTL bug (ERR-0003): last0 wasn't gated like valid0, letting a "last tile" tag leak into the pipeline ahead of its actual valid tile on back-to-back jobs. Fixed and verified. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
372 lines
16 KiB
Verilog
372 lines
16 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// SPI_FLASH_MASTER
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//
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// SPI MASTER toward the boot/persistence NOR flash (Winbond
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// W25Q128JV, confirmed part per docs/FPGA-Neural-Hardware-Design.md
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// §6/§7 -- see sim/flash_model.v's header for the JEDEC-ID variant
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// caveat). This is the FPGA's *only* path to that flash: the host
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// never touches these pins directly (see the phase-plan's §0
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// constraint) -- it issues opcodes through spi_engine, which this
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// module (and, in later phases, the copy engine built on top of it)
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// serves.
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//
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// Everything the existing design talks to (rtl/spi_slave.v) is an
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// SPI SLAVE toward the host. This module is the mirror image: an
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// SPI MASTER toward the flash, mode 0 (CPOL=0, CPHA=0), MSB-first,
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// matching every timing diagram in the W25Q128JV datasheet (Fig.
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// 7/28/30/43a): MOSI driven on the falling edge of SCLK (one edge
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// ahead of the flash's own rising-edge sample), MISO sampled on the
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// rising edge (the flash drove it on the previous falling edge).
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//
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// ----------------------------------------------------------------
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// DEDICATED BUS, NO CCLK/USRMCLK SHARING (revised 2026-09-04)
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// ----------------------------------------------------------------
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// This master's 4 pins (sclk/mosi/miso/cs_n) are ALL ordinary GPIO,
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// wired to a second, independent connection on the same flash chip
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// -- the runtime persistence path is fully separate from the boot
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// config-SPI path (which still uses the dedicated CCLK/DQ0/DQ1/CS
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// sysCONFIG pins on their own, untouched by this module). No pin is
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// shared between the two, and no ECP5 config-primitive (`USRMCLK`)
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// is involved: `sclk` is driven the same way `mosi`/`cs_n` already
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// are, a plain synchronous output, real from simulation straight
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// through to place&route -- one identical `.lpf` entry like every
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// other signal in this design, not a special MCLK-site placement.
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//
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// This design was originally built reusing the CCLK pad via
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// `USRMCLK` (see git history / WORKLOG.md's Phase F1 entry for that
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// version) to save one pin. That coupling was dropped: sharing the
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// boot clock pad made the "exclusive flash SPI bus" claim misleading
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// (electrically it wasn't independent of the config engine at all),
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// and it carried a real unresolved verification gap (`USRMCLKTS`
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// pad-enable timing was never checked against the primary Lattice
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// sysCONFIG Usage Guide, FPGA-TN-02039 -- not present in this
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// project's local document set). A 4th ordinary GPIO ball costs
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// nothing on this part (huge pin headroom, docs/FPGA-Neural-
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// Hardware-Design.md §2) and removes the coupling and the
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// verification gap entirely.
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// ----------------------------------------------------------------
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//
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// Command interface (byte-oriented, req/valid handshakes matching
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// this codebase's existing conventions -- see rtl/spi_slave.v's
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// rx_valid/tx_byte_req and rtl/mem_arbiter.v's req/ready):
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//
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// start -- one-cycle pulse, transaction accepted iff !busy
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// opcode[7:0] -- flash instruction byte (RDID/READ/WREN/PP/SE/RDSR1)
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// has_addr -- 1: send 3 address bytes (A23-A0) after opcode
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// addr[23:0] -- address, sent MSB-first (matches every W25Q128JV
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// instruction diagram: A23-A16, A15-A8, A7-A0)
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// dir[1:0] -- DIR_NONE (opcode/addr only, e.g. WREN/SE),
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// DIR_WRITE (stream n_data bytes TO the flash,
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// e.g. PP), DIR_READ (stream n_data bytes FROM
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// the flash, e.g. READ/RDID/RDSR1)
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// n_data[15:0] -- byte count for the data phase (0 for DIR_NONE)
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//
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// wdata_req -- one-cycle pulse: master needs the next write
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// byte now; caller responds (same cycle or later,
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// this module simply waits, sclk idles low with
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// CS still held low -- a legal SPI technique, no
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// deselect-time constraint applies mid-transaction)
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// with wdata_valid+wdata.
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// wdata_valid -- one-cycle pulse, wdata is valid this cycle
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// wdata[7:0]
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//
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// rdata_valid -- one-cycle pulse: rdata holds a freshly-received
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// byte; master pauses (sclk idle, CS still low)
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// until the caller acks.
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// rdata[7:0]
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// rdata_ack -- one-cycle pulse from caller: byte consumed,
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// resume shifting.
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//
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// busy, done (one-cycle pulse on transaction completion)
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//
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// SCLK RATE -- §1 of the phase-plan prompt requires citing timing:
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// the W25Q128JV(-DTR) datasheet's §9.6 AC Electrical Characteristics
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// (p.90) caps the Read Data (03h) instruction specifically at
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// fR=50MHz (all OTHER standard-SPI instructions allow up to
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// 104-133MHz depending on VCC). Since this master uses one fixed
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// divider for every instruction, it must honor the TIGHTEST of
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// those limits. Default SCLK_DIV=2 at CLK_FREQ_MHZ=80 gives
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// sclk = 80/(2*2) = 20MHz, comfortably under the 50MHz Read Data cap
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// with margin for the rise/fall-time and setup/hold non-idealities
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// this digital model does not represent (§A.6) -- correctness over
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// speed, per the phase-plan's own §A.6/§8 guidance (this is an
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// init/persistence path, not the inference hot path).
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// ================================================================
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module spi_flash_master #(
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parameter CLK_FREQ_MHZ = 80,
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parameter SCLK_DIV = 2 // sclk = CLK_FREQ_MHZ / (2*SCLK_DIV) MHz
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)(
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input wire clk,
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input wire rst,
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// ------------------------------------------------------------
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// Physical pins toward the flash
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// ------------------------------------------------------------
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output reg mosi,
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input wire miso,
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output reg cs_n,
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output wire sclk, // ordinary GPIO, real in both sim and synthesis -- see header
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// ------------------------------------------------------------
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// Command interface
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// ------------------------------------------------------------
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input wire start,
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input wire [7:0] opcode,
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input wire has_addr,
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input wire [23:0] addr,
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input wire [1:0] dir,
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input wire [15:0] n_data,
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output reg wdata_req,
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input wire [7:0] wdata,
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input wire wdata_valid,
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output reg rdata_valid,
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output reg [7:0] rdata,
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input wire rdata_ack,
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output wire busy,
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output reg done
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);
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localparam DIR_NONE = 2'd0;
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localparam DIR_WRITE = 2'd1;
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localparam DIR_READ = 2'd2;
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// ============================================================
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// SCLK generator: free-running divider, gated by `shifting`
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// (asserted only while actively clocking a bit; held with sclk
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// low and CS still low during the WAIT_W/EMIT_R handshake
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// pauses between data bytes).
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// ============================================================
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reg [15:0] div_cnt;
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reg sclk_reg;
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reg shifting;
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wire sclk_half_reached = (div_cnt == SCLK_DIV - 1);
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always @(posedge clk) begin
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if (rst || !shifting) begin
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div_cnt <= 16'd0;
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sclk_reg <= 1'b0;
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end else if (sclk_half_reached) begin
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div_cnt <= 16'd0;
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sclk_reg <= ~sclk_reg;
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end else begin
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div_cnt <= div_cnt + 16'd1;
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end
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end
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wire sclk_will_rise = shifting & sclk_half_reached & ~sclk_reg; // about to go 0->1
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wire sclk_will_fall = shifting & sclk_half_reached & sclk_reg; // about to go 1->0
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assign sclk = sclk_reg;
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// ============================================================
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// Main FSM
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// ============================================================
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localparam ST_IDLE = 4'd0;
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localparam ST_CS_SETTLE = 4'd1; // one clk cycle: CS asserted, sclk still idle (setup margin)
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localparam ST_HDR = 4'd2; // shifting opcode (+ addr) out
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localparam ST_DATA_WAIT_W = 4'd3; // paused: need next write byte from caller
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localparam ST_DATA_SHIFT = 4'd4; // shifting one data byte (either direction)
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localparam ST_DATA_EMIT_R = 4'd5; // paused: present a received byte, wait ack
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localparam ST_CS_RELEASE = 4'd6; // one clk cycle: CS deasserted, settle
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localparam ST_DONE = 4'd7;
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reg [3:0] state;
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reg [31:0] hdr_shift; // up to 32 bits: 8 opcode + 24 addr
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reg [5:0] hdr_len; // total header bits for this transaction
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reg [5:0] bit_idx; // bit position within the current chunk (header or one data byte)
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reg [7:0] byte_shift; // current data byte, shifting
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reg [15:0] data_idx; // completed data bytes so far
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reg [15:0] data_total;
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reg [1:0] cur_dir;
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assign busy = (state != ST_IDLE);
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always @(posedge clk) begin
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if (rst) begin
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state <= ST_IDLE;
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cs_n <= 1'b1;
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mosi <= 1'b0;
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shifting <= 1'b0;
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wdata_req <= 1'b0;
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rdata_valid <= 1'b0;
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rdata <= 8'h00;
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done <= 1'b0;
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hdr_shift <= 32'h0;
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hdr_len <= 6'd0;
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bit_idx <= 6'd0;
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byte_shift <= 8'h00;
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data_idx <= 16'd0;
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data_total <= 16'd0;
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cur_dir <= DIR_NONE;
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end else begin
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wdata_req <= 1'b0;
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rdata_valid <= 1'b0;
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done <= 1'b0;
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case (state)
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// --------------------------------------------
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ST_IDLE: begin
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shifting <= 1'b0;
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if (start) begin
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cs_n <= 1'b0;
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hdr_shift <= has_addr ? {opcode, addr} : {opcode, 24'h0};
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hdr_len <= has_addr ? 6'd32 : 6'd8;
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bit_idx <= 6'd0;
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data_idx <= 16'd0;
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data_total <= n_data;
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cur_dir <= dir;
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mosi <= opcode[7]; // bit index 0, preloaded ahead of the first rising edge
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state <= ST_CS_SETTLE;
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end
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end
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// --------------------------------------------
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ST_CS_SETTLE: begin
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shifting <= 1'b1;
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state <= ST_HDR;
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end
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// --------------------------------------------
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// Generic bit shifter for the header (opcode+addr).
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// MOSI updated on the falling edge (one edge ahead
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// of the flash's rising-edge sample); bit_idx
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// advances on the rising edge (the edge on which
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// the flash actually captures the bit we set up on
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// the PRECEDING falling edge).
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// --------------------------------------------
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ST_HDR: begin
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if (sclk_will_fall) begin
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// At this point bit_idx already equals the
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// number of bits sampled so far (updated by
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// the preceding rising edge, below), which
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// is exactly the index of the NEXT bit to
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// put on MOSI ahead of its own rising-edge
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// sample -- e.g. after the 1st rising edge
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// samples bit 0, bit_idx==1 and this falling
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// edge must prepare bit 1 = hdr_shift[31-1].
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if (bit_idx < hdr_len)
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mosi <= hdr_shift[31 - bit_idx];
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end
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if (sclk_will_rise) begin
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if (bit_idx == hdr_len - 1) begin
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// Header done. Move to data phase or
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// straight to CS release (DIR_NONE).
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bit_idx <= 6'd0;
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if (cur_dir == DIR_NONE || data_total == 16'd0) begin
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shifting <= 1'b0;
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state <= ST_CS_RELEASE;
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end else if (cur_dir == DIR_WRITE) begin
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shifting <= 1'b0;
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wdata_req <= 1'b1;
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state <= ST_DATA_WAIT_W;
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end else begin // DIR_READ
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state <= ST_DATA_SHIFT;
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end
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end else begin
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bit_idx <= bit_idx + 6'd1;
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end
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end
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end
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// --------------------------------------------
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ST_DATA_WAIT_W: begin
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if (wdata_valid) begin
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byte_shift <= wdata;
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mosi <= wdata[7];
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bit_idx <= 6'd0;
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shifting <= 1'b1;
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state <= ST_DATA_SHIFT;
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end
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end
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// --------------------------------------------
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// One data byte, either direction.
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// --------------------------------------------
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ST_DATA_SHIFT: begin
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if (sclk_will_rise) begin
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if (cur_dir == DIR_READ)
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byte_shift <= {byte_shift[6:0], miso};
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if (bit_idx == 6'd7) begin
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data_idx <= data_idx + 16'd1;
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if (cur_dir == DIR_READ) begin
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shifting <= 1'b0;
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rdata <= {byte_shift[6:0], miso};
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rdata_valid <= 1'b1;
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state <= ST_DATA_EMIT_R;
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end else begin
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if (data_idx + 16'd1 == data_total) begin
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shifting <= 1'b0;
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state <= ST_CS_RELEASE;
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end else begin
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shifting <= 1'b0;
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wdata_req <= 1'b1;
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state <= ST_DATA_WAIT_W;
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end
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end
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end else begin
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bit_idx <= bit_idx + 6'd1;
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end
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end
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if (sclk_will_fall && cur_dir == DIR_WRITE) begin
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// Same indexing rationale as ST_HDR above.
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if (bit_idx < 6'd8)
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mosi <= byte_shift[7 - bit_idx];
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end
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end
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// --------------------------------------------
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ST_DATA_EMIT_R: begin
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if (rdata_ack) begin
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if (data_idx == data_total) begin
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state <= ST_CS_RELEASE;
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end else begin
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bit_idx <= 6'd0;
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shifting <= 1'b1;
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state <= ST_DATA_SHIFT;
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end
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end
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end
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// --------------------------------------------
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ST_CS_RELEASE: begin
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cs_n <= 1'b1;
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state <= ST_DONE;
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end
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// --------------------------------------------
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ST_DONE: begin
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done <= 1'b1;
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state <= ST_IDLE;
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end
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default: state <= ST_IDLE;
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endcase
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end
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end
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endmodule
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