micheleandClaude Sonnet 5
e25e4a1506
New hardware/v3/rtl/mig_native_adapter.v: adapts this project's established req/wr/addr/wdata/wmask->rdata/ready/busy contract to the real MIG 7-series native app interface (app_addr/app_cmd/app_en, app_wdf_data/app_wdf_mask/app_wdf_wren/app_wdf_end, app_rd_data/ app_rd_data_valid/app_rd_data_end), derived from this project's own real generated mig_7series_0.v port widths, not assumed. Runs in the ui_clk domain (MIG's own generated clock becomes this project's system clock going forward). Verified against MIG's own real, vendor-shipped DDR3 behavioral model (ddr3_model.sv) via real Xilinx xsim/xvlog/xelab (UNISIM primitives in MIG's PHY require this over Verilator): 12/12 write-then-read-back transactions bit-exact, 0 errors, real JEDEC command sequence observed (Activate/Write/Read/Precharge). Confirms the app_cmd encoding and burst/beat sequencing on first real test. Also adds hardware/v3/rtl/sdram_arbiter_n.v (generalized N-way arbiter, generalizing EXP-0066's 2-way version for N>2 scaling and a future host-access requester) -- its own isolated test currently HANGS, root cause not yet found, do not trust this module yet (disclosed, not hidden). Full writeup in hardware/v2/logs/experiments.log EXP-0068. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC