micheleandClaude Sonnet 5
eb0b0f9170
Adds hardware/v2/docs/PRE_PCB_VERIFICATION.md as the single authoritative pre-schematic verification record: RTL/ERR-0025/ regression re-verification, clock/reset, synthesis/P&R re-audit, setup/hold timing status, the real SDRAM datasheet-parameter audit table (Alliance Memory AS4C4M16SA-6TIN Table 17), SPI host bridge protocol documentation, FPGA power/pinout tables, first-board bring-up and benchmark status, and cross-domain consistency audit. Freezes the FPGA configuration flash: Winbond W25Q32JVSSIQ (32Mbit, SOIC-8, 2.7-3.6V, standard SPI, ECP5 Master-SPI-boot compatible) -- this was the one section-11 item the governing mandate required not be left OPEN. Marks CHIP_READINESS.md/OPEN_ITEMS.md/PINOUT.md/CLOCK_ARCHITECTURE.md/ POWER_ARCHITECTURE.md/SCHEMATIC_READINESS.md as superseded (they predate the SPI host bridge, PLL, and this session's SDRAM datasheet audit) with pointers to the new consolidated document, rather than rewriting each individually. Updates the V2 LaTeX datasheet's status/roadmap chapter to reflect the SDRAM datasheet audit and configuration-flash decisions, rebuilds the PDF (clean compile, 16 pages). Classification: PRE-PCB VERIFIED. Schematic and PCB implementation remain user-owned and not started. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
111 lines
5.4 KiB
Markdown
111 lines
5.4 KiB
Markdown
# FPGA-Neural V2 — CLOCK ARCHITECTURE
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**SUPERSEDED.** This document predates the real EHXPLLL PLL
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(`ecp5_pll_sys_clk.v`) that resolves the mismatch described below. See
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`PRE_PCB_VERIFICATION.md` \S3 for the current, verified clock/reset
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status (PASS). Left in place as a historical record of the
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architectural decision that led to adding the PLL.
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## Status (HISTORICAL): CRITICAL — real, unresolved oscillator/clock-input mismatch
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## What the RTL actually assumes
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Every module in the frozen hierarchy (`nms_neural_multiprocessor_
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sdram_unified.v` down to `sdram_controller.v`) takes a **single** `clk`
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input and treats it directly as both the system clock AND the SDRAM
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clock (`CLK_FREQ_MHZ=80` is a pure timing-derivation parameter fed
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into `sdram_controller.v`'s own `ns_to_cycles()` function — it does
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NOT configure a PLL; there is no PLL anywhere in this hierarchy).
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Confirmed mechanically: every real synthesis run this project has
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performed (STEP16 through this freeze) reports `EHXPLLL: 0/4 0%` in
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nextpnr's own device-utilisation output — **zero PLL primitives are
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instantiated**, in any variant, ever.
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**This means the design requires a real, external 80MHz (or faster)
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clock source wired directly to the FPGA's clock input pin.**
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## The real gap
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This project's own memory notes (established in an earlier session,
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before the SDRAM decision) record the confirmed hardware target board
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as using a **16MHz** oscillator. 16MHz ≠ 80MHz, and there is no PLL in
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the current RTL to bridge that gap. **Two mutually exclusive
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resolutions exist, and neither has been chosen:**
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1. **Source an oscillator that directly provides ≥80MHz** (a
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commodity part — plain crystal oscillators at 80, 100, or higher
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MHz are standard, low-risk components) and retire the 16MHz
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assumption. Zero RTL change required. Simplest, lowest-risk path.
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2. **Keep the 16MHz oscillator and add a real PLL** (ECP5's own
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`EHXPLLL` primitive, e.g. 16MHz→80MHz = ×5) to the RTL, with its
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own real timing constraints (lock time, jitter, generated-clock
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declaration in the constraints file) — genuinely new RTL/constraint
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work, not yet done, and not exercised by any of this project's own
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real synthesis/timing-closure runs to date (every Fmax number in
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STEP16-18 assumes a clean, ideal `clk` input, not a PLL output with
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its own jitter/lock-time budget).
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**This is an OPEN, real architectural decision, not a detail** — it
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determines whether a new oscillator needs sourcing or a PLL needs
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designing, and affects the CLOCK_SOURCE→FPGA_CLOCK diagram below,
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which cannot be finalized until it is made.
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## Clock tree (as far as it CAN be stated today)
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```
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[UNRESOLVED: either an 80MHz+ oscillator, or a 16MHz oscillator + PLL]
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v
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FPGA clk pin (ball location: BLOCKER, see PINOUT.md)
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v
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single system clock domain, 80 MHz target
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+--> Neural Multiprocessor / Dependency Manager / Director /
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| Memory Manager / Neural Processors (all synchronous,
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| single clock domain — confirmed, no clock-domain-crossing
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| logic exists anywhere in the frozen hierarchy)
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+--> SDRAM controller (same clock, no separate SDRAM clock
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domain — sdram_controller.v drives the SDRAM chip's own
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CLK pin combinationally/directly from the same system
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clock; real board layout must still budget for the
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SDRAM's own real clock-to-pin round-trip delay, which
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was NOT part of this project's own RTL-simulation/P&R
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timing closure — flagged as an OPEN ITEM for board bring-
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up, see FIRST_POWER_ON.md)
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```
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## Reset
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A single `rst` input, synchronous to `clk` in every module observed
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(no asynchronous reset assertion/de-assertion synchronizer chain was
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found in this session's own lint pass). **Reset release timing/
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synchronization to a real external reset source (power-on reset chip,
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button, or host-driven) has not been designed** — this is a normal,
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solvable board-level concern (a standard POR/supervisor IC), not
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flagged as a blocker, but not yet decided (OPEN ITEM).
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## Clock constraints used so far
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Every P&R run in STEP16-18 used `nextpnr-ecp5 --freq 80` (a target
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frequency for the placer's own timing-driven effort), NOT a real `.lpf`
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`FREQUENCY` constraint tied to a real pin — because no `.lpf` exists at
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all for any V2 top-level (see PINOUT.md). A real constraints file with
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a proper `FREQUENCY PORT "clk" 80 MHZ;` (or the real achieved-vs-
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required frequency once the oscillator/PLL decision above is made)
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must be written before this can be considered a genuine, board-ready
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clock constraint.
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## Summary
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| Item | Status |
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| Single-clock-domain RTL, no CDC logic found | Confirmed by lint, real |
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| PLL present in RTL | **No — confirmed absent (0/4 EHXPLLL in every P&R run)** |
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| Oscillator frequency vs required system clock | **CRITICAL — 16MHz (prior project memory) vs 80MHz (RTL requirement), unresolved** |
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| Oscillator-vs-PLL decision | **OPEN — not made** |
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| Real `.lpf` clock constraint | Partial — `hardware/v2/constraints/v2_unified.lpf` now exists with a frequency constraint and clk/rst ball reuse from V1; full ball-level pinout for the remaining 147 signals is still blocked (see PINOUT.md) |
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| Reset synchronization to a real external source | OPEN, not yet designed (not a hard blocker) |
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| SDRAM clock-to-pin board-level timing budget | OPEN — not part of RTL-level timing closure |
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