micheleandClaude Sonnet 5
dc0b331d3e
Begins the V2 Neural Multiprocessor / Dataflow architecture per docs/v2-description.md, per explicit user request to freeze V1 and start V2 development, copying from V1 what's needed. Scaffold: - hardware/v1/: byte-exact, read-only copy of the current V1 codebase (rtl, testbenches, tools, constraints, a representative subset of synthesis results, and reference docs) -- verified identical via diff/cmp against the live top-level tree before being made filesystem-read-only. The live top-level tree is untouched and remains the project's "production" V1 (see hardware/v1/README.md and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move). - hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/ reports/scripts/logs/docs) plus the full logging system required by the spec (development/architecture/simulation/synthesis/timing/ benchmark/decisions/experiments/errors.log). M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v): - 8-stage pipelined perceptron unit (P_IN=8): input align, 8 multipliers, 3-level adder tree, accumulator, bias+activation, INT8 saturation. Genuine 1-tile/cycle throughput, not just a wider combinational datapath. - 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with 4 baseline states merged into NP_WAIT_OPERANDS -- see decisions.log DEC-0002); valid/ready/data/last stream interfaces per §7. - Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v), covering regular/mixed-sign/extreme-INT8 vectors, both activations, a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile job -- verified with Verilator (see below for why). - Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24 (a user-requested comparison experiment, also bit-exact-verified; see experiments.log EXP-0001/EXP-0002 and benchmark.log). Three real bugs found and resolved during M1 development (full diagnostic record in errors.log): - Two independent, reproducible Icarus Verilog v13.0 scheduling defects (ERR-0001, ERR-0002) that silently produced wrong simulation results for standard sequential Verilog -- confirmed via Verilator 5.050 giving correct results on the same minimal repros. Verilator is now the trusted simulator for hardware/v2/ (decisions.log DEC-0004); Icarus's affected protocol-violation check was removed from the RTL and deferred architecturally to the Neural Director (DEC-0003) rather than chased further. - One real RTL bug (ERR-0003): last0 wasn't gated like valid0, letting a "last tile" tag leak into the pipeline ahead of its actual valid tile on back-to-back jobs. Fixed and verified. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
35 lines
2.1 KiB
Markdown
35 lines
2.1 KiB
Markdown
# C.9 — Pinout / `.lpf`
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Data: 2026-09-04. Certificato per citazione di lavoro reale già svolto in questa stessa
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sessione (non di sessioni precedenti prese sulla parola) — nessuna nuova verifica necessaria
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oltre a quanto già fatto durante il lavoro sul sottosistema flash (Fasi F1-F7) subito prima
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di questa campagna.
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## Evidenza
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- **`.lpf` reale, non pianificato**: `synth/ecp5/spi_neuron_top.lpf`, generato da
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`tools/pinout/gen_lpf.py` contro `iodb.json` di Project Trellis (lo stesso database che
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usa `nextpnr-ecp5`), non da un foglio di calcolo/assunzione.
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- **Place&route reale a 0 errori**, senza `--lpf-allow-unconstrained`: 57 segnali piazzati
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su vincoli reali, confermato in questa sessione con la ri-sintesi completa di Fase F7
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(`synth/ecp5/spi_neuron_top_flash/nextpnr.log`).
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- **Cross-check indipendente contro il datasheet Lattice reale** (non solo Trellis):
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conteggi GPIO per banco confrontati con la §4.3.2 del datasheet ufficiale
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`FPGA-DS-02012-3-4-ECP5-ECP5G-Family-Data-Sheet.pdf` fornito dall'utente — coincidenza
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esatta su 6 banchi su 7.
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- **`USRMCLK` verificato contro il blackbox reale di yosys** (`cells_bb.v`), non
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un'assunzione sull'API — e poi, in Fase F7, **rimosso interamente** dal percorso del bus
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flash proprio perché quella dipendenza era un gap di verifica dichiarato (mai confermato
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contro la guida Lattice primaria) — chiuso eliminando la dipendenza, non colmando la
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verifica mancante. Confermato dalla stessa sintesi: `USRMCLK` 0/1 (0%) nel build corrente.
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- **Bitstream reale generato per il build corrente** (non solo per un build più vecchio,
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pre-flash): `ecppack --compress synth/ecp5/spi_neuron_top_flash/top.config
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/tmp/current_full_system.bit` → 0 errori, header verificato byte-per-byte
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(`Part: LFE5U-45F-8CABGA381`, il part number reale del target, non un placeholder).
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## Verdetto
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**CERTIFICATO.** Nessuna riserva aggiuntiva oltre a quelle già dichiarate esplicitamente
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nel lavoro di sessione (ball di JTAG/config-SPI di boot non pinnate su ball specifiche —
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dichiarato, non un difetto: sono pin dedicati senza porta RTL, non richiesti da nextpnr).
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