micheleandClaude Sonnet 5
dc0b331d3e
Begins the V2 Neural Multiprocessor / Dataflow architecture per docs/v2-description.md, per explicit user request to freeze V1 and start V2 development, copying from V1 what's needed. Scaffold: - hardware/v1/: byte-exact, read-only copy of the current V1 codebase (rtl, testbenches, tools, constraints, a representative subset of synthesis results, and reference docs) -- verified identical via diff/cmp against the live top-level tree before being made filesystem-read-only. The live top-level tree is untouched and remains the project's "production" V1 (see hardware/v1/README.md and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move). - hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/ reports/scripts/logs/docs) plus the full logging system required by the spec (development/architecture/simulation/synthesis/timing/ benchmark/decisions/experiments/errors.log). M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v): - 8-stage pipelined perceptron unit (P_IN=8): input align, 8 multipliers, 3-level adder tree, accumulator, bias+activation, INT8 saturation. Genuine 1-tile/cycle throughput, not just a wider combinational datapath. - 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with 4 baseline states merged into NP_WAIT_OPERANDS -- see decisions.log DEC-0002); valid/ready/data/last stream interfaces per §7. - Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v), covering regular/mixed-sign/extreme-INT8 vectors, both activations, a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile job -- verified with Verilator (see below for why). - Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24 (a user-requested comparison experiment, also bit-exact-verified; see experiments.log EXP-0001/EXP-0002 and benchmark.log). Three real bugs found and resolved during M1 development (full diagnostic record in errors.log): - Two independent, reproducible Icarus Verilog v13.0 scheduling defects (ERR-0001, ERR-0002) that silently produced wrong simulation results for standard sequential Verilog -- confirmed via Verilator 5.050 giving correct results on the same minimal repros. Verilator is now the trusted simulator for hardware/v2/ (decisions.log DEC-0004); Icarus's affected protocol-violation check was removed from the RTL and deferred architecturally to the Neural Director (DEC-0003) rather than chased further. - One real RTL bug (ERR-0003): last0 wasn't gated like valid0, letting a "last tile" tag leak into the pipeline ahead of its actual valid tile on back-to-back jobs. Fixed and verified. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
62 lines
3.6 KiB
Plaintext
62 lines
3.6 KiB
Plaintext
# V2 development log — solo append, mai troncato/sovrascritto (vedi README.md)
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[2026-09-05T11:14:08Z] commit=07a48e4 session=v2-kickoff
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module: scaffold
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action: creato hardware/v1/ (baseline V1 congelata, sola lettura) e
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hardware/v2/ (struttura obbligatoria: rtl/ sim/ constraints/ synthesis/
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reports/{simulation,synthesis,timing,experiments}/ scripts/sweep/ logs/
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docs/), per iniziare lo sviluppo V2 richiesto da docs/v2-description.md.
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reason: richiesta utente esplicita -- "Crea un v1 con tutto il codice
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attuale che non deve essere modificato per nessun motivo e lavora su
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una v2 copiando quello che ti serve. Aggiornami frequentemente e crea
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un log nuovo."
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command: cp rtl/*.v sim/*.v tools/ synth/ecp5/{p2,p4,p8,post_fix_verify}
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synth/ecp5/*.lpf docs/validation/*.md WORKLOG.md
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docs/FPGA-NeuralNetwork-Engine.md docs/FPGA-Neural-Datapatch-Benchmark.md
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docs/FPGA-Neural-Hardware-Design.md -> hardware/v1/{rtl,sim,tools,
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constraints,synthesis,docs}; chmod -R a-w su tutto hardware/v1/.
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result: verificato bit-esatto (`diff -rq rtl/ hardware/v1/rtl/` e cmp
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file-per-file su sim/*.v, 0 differenze). hardware/v1/ reso sola lettura
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a livello filesystem come ulteriore salvaguardia oltre alla policy.
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hardware/v2/ vuoto tranne logs/ (questo file + README.md).
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errors: nessuno.
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decision: copia (non spostamento) dell'albero top-level rtl/sim/synth/
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tools -- l'albero principale del repository resta la "produzione" V1
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invariata; hardware/v1/ e' una seconda copia frozen dedicata al
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confronto V2, per minimizzare il rischio di rompere riferimenti/path
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esistenti in WORKLOG.md, docs/, altri script. Vedi decisions.log
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DEC-0001 per la motivazione completa.
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next_action: M1 (docs/v2-description.md §33) -- implementare
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hardware/v2/rtl/neural_processor.v (P_IN=8), pipeline 8 stage,
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bit-exact contro hardware/v1/rtl/neuron_parallel.v + mac8.v,
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testbench hardware/v2/sim/tb_neural_processor.v.
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[2026-09-05T12:03:12Z] commit=07a48e4 session=v2-M1-neural-processor
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module: hardware/v2/rtl/neural_processor.v + hardware/v2/sim/
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tb_neural_processor.v
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action: implementato M1 (docs/v2-description.md §33) -- Neural
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Processor P_IN=8, pipeline a 8 stadi (input align -> 8 moltiplicatori
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-> 3 livelli di albero di somma -> accumulatore -> bias/activation ->
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saturazione INT8), FSM a 7 stati (§6, con 4 stati assorbiti in
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NP_WAIT_OPERANDS per il vero throughput pipeline -- vedi
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decisions.log DEC-0002), interfacce valid/ready/data/last (§7).
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Aritmetica bit-esatta con hardware/v1/rtl/neuron_parallel.v +
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mac8.v + mac_unit.v.
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reason: roadmap M1, richiesta esplicita utente di iniziare lo sviluppo
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V2 copiando da V1 quanto necessario.
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result: 3 bug reali incontrati e risolti durante lo sviluppo (vedi
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errors.log ERR-0001/0002/0003) -- due erano bug del toolchain Icarus
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Verilog v13.0 (non del RTL), confermati installando e usando
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Verilator 5.050 come secondo simulatore indipendente (decisions.log
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DEC-0004); uno era un bug RTL reale (gating mancante su `last0`,
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fix verificato). Testbench finale: 7/7 test PASS, bit-exact contro
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V1, sia a ACC_WIDTH=32 che ACC_WIDTH=24 (esperimento richiesto
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dall'utente, experiments.log EXP-0002). Sintesi reale Yosys + P&R
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reale nextpnr-ecp5: 0 problemi CHECK, Fmax 183.12 MHz (ACC_WIDTH=32)
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/ 176.21 MHz (ACC_WIDTH=24) -- entrambi PASS a 80MHz con ampio
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margine, ~3x il Fmax isolato di V1 a PARALLEL=8 (61.71 MHz).
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errors: vedi errors.log ERR-0001, ERR-0002, ERR-0003, ERR-0004.
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decision: vedi decisions.log DEC-0002, DEC-0003, DEC-0004.
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next_action: M2 -- neural_processor_array.v, sweep N_PROCESSORS
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(1,2,4,8), misura timing/risorse/throughput/utilization reali.
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