micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
7 lines
617 B
CSV
7 lines
617 B
CSV
config,n_slots,physical_bus_bits,internal_width_bits,burst_len,cache_entries,cycles,fmax_mhz_best,mb_s,mac_per_cycle,bit_exact,classification
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baseline,2,16,64,4,0,52161,103.99,50.26,0.6282,PASS,INTEGRATED BENCHMARK / POST-P&R
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baseline,4,16,64,4,0,49430,81.55,53.04,0.6629,PASS,INTEGRATED BENCHMARK / POST-P&R
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pack128_1entry_REJECTED,4,16,128,8,1,74004,not_synthesized,35.32,0.4428,PASS,INTEGRATED BENCHMARK (real regression, not accepted -- ERR-0022)
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pack128,2,16,128,8,4,47399,86.04,55.30,0.6913,PASS,INTEGRATED BENCHMARK / POST-P&R
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pack128,4,16,128,8,4,44935,81.47,58.34,0.7292,PASS,INTEGRATED BENCHMARK / POST-P&R
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