micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
110 lines
6.8 KiB
Markdown
110 lines
6.8 KiB
Markdown
# FPGA-Neural V2 — SCHEMATIC READINESS
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## Status: NOT READY
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## Block diagram (what a hardware designer needs to know)
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```
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┌─────────────┐ ┌──────────────────────────────┐
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│ Clock │ clk │ │
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│ BLOCK ├───────►│ │
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│ (OPEN item: │ │ │
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│ 16MHz osc │ rst │ FPGA BLOCK │
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│ vs 80MHz ├───────►│ LFE5U-45F-8BG381/CABGA381 │
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│ needed -- │ │ │
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│ see CLOCK_ │ │ nms_neural_multiprocessor_ │
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│ ARCHITECTURE│ │ sdram_unified (N_SLOTS=4) │
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│ .md) │ │ │
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└─────────────┘ │ ┌────────────────────────┐ │ ┌───────────────┐
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│ │ SDRAM interface (37 pins)├──────►│ SDRAM BLOCK │
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│ │ sdram_cke/cs_n/ras_n/ │ │ │ AS4C4M16SA-6TIN│
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│ │ cas_n/we_n/ba/a/dq/dqm │ │ │ (ONE chip -- │
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│ └────────────────────────┘ │ │ weights+ │
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│ │ │ activations+ │
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│ ┌────────────────────────┐ │ │ results ALL │
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│ │ Host bus (110 pins, │ │ │ here) │
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│ │ BLOCKER -- raw parallel, │ │ └───────────────┘
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│ │ not a real protocol yet) │ │
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│ └────────────────────────┘ │
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│ │
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┌─────────────┐ │ ┌────────────────────────┐ │
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│ CONFIG BLOCK │ JTAG │ │ TDI/TDO/TCK/TMS/ │ │
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│ (OPEN: no ├────────►│ │ PROGRAMN/INITN/DONE/ │ │
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│ flash part │ SPI │ │ CCLK (standard ECP5, │ │
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│ chosen) ├────────►│ │ ball location BLOCKED) │ │
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└─────────────┘ │ └────────────────────────┘ │
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└──────────────────────────────┘
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│
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┌───────────┴───────────┐
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│ POWER BLOCK │
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│ VCC 1.1V / VCCAUX 2.5V / │
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│ VCCIO 3.3V / SDRAM 3.3V │
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│ (OPEN: regulators not │
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│ selected) │
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└──────────────────────────┘
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┌─────────────┐
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│ HOST BLOCK │ <-- BLOCKER: does not exist yet as real RTL.
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│ (a real MCU/ │ Must serialize the 110-pin reg_* bus into
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│ SPI/UART │ a real physical protocol (SPI, matching V1's
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│ interface) │ own spi_neuron_top.v precedent, or similar)
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└─────────────┘
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┌─────────────┐
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│ DEBUG/JTAG │ <-- standard ECP5 JTAG chain; no V2-specific
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│ BLOCK │ debug infrastructure beyond that identified
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└─────────────┘ this round.
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```
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## Interconnections a schematic designer needs (real, from the RTL)
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- **FPGA ↔ SDRAM**: 37 real signals (`sdram_cke`, `sdram_cs_n`,
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`sdram_ras_n`, `sdram_cas_n`, `sdram_we_n`, `sdram_ba[1:0]`,
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`sdram_a[11:0]`, `sdram_dq[15:0]` bidirectional, `sdram_dqm[1:0]`) —
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a single-chip, direct point-to-point connection (no bus sharing, no
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second memory device). Real bank/ball assignment is BLOCKED (see
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PINOUT.md) but the SIGNAL LIST itself is complete and final.
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- **FPGA ↔ Clock**: one clock input pin (ball H5, reused from V1's own
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real, validated assignment) — the SOURCE feeding that pin (direct
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80MHz+ oscillator, or 16MHz oscillator + internal PLL) is an OPEN
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decision (see CLOCK_ARCHITECTURE.md); the schematic cannot be
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finalized for this block until that choice is made.
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- **FPGA ↔ Reset**: one reset input pin (ball B4, reused from V1) —
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real synchronization to a power-on-reset supervisor or button is
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OPEN (not designed).
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- **FPGA ↔ Configuration**: standard ECP5 JTAG/config pins exist by
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device definition; whether the board ALSO includes an SPI
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configuration flash (for standalone, non-JTAG boot) is an OPEN
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decision (see CHIP_READINESS.md and OPEN_ITEMS.md).
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- **FPGA ↔ Host**: **BLOCKER**. The real RTL currently exposes a
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110-pin raw parallel bus with no serializing interface. A schematic
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cannot meaningfully route "the host connection" until a real
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physical protocol (and its own RTL bridge) exists.
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- **FPGA ↔ Power**: standard ECP5 rail requirements (VCC/VCCAUX/VCCIO)
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plus the SDRAM's own 3.3V rail — real regulator selection is OPEN
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(see POWER_ARCHITECTURE.md).
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## What IS ready
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- The FPGA/package/speed-grade target is fixed and unambiguous
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(LFE5U-45F-8BG381, CABGA381, -8).
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- The external memory device is fixed and unambiguous (ONE
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AS4C4M16SA-6TIN, no second chip).
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- The complete, real signal list for the SDRAM interface is final (37
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signals, confirmed by real POST-P&R synthesis).
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- Real rail VOLTAGES (not currents) are known from device datasheets.
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## What blocks starting the schematic today
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1. Host interface: no real physical protocol exists (BLOCKER).
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2. Ball-level pinout: no real assignment exists for SDRAM or host
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signals (BLOCKER, same root cause as PINOUT.md's own finding).
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3. Clock source decision: oscillator-only vs oscillator+PLL (CRITICAL,
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OPEN).
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4. Power regulator selection and current budget (OPEN).
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5. Configuration-flash decision (OPEN).
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**Conclusion: NOT READY.** A hardware designer could begin laying out
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the SDRAM-to-FPGA net list today (that part is real and complete), but
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could not close the schematic without resolving items 1–5 above.
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