micheleandClaude Sonnet 5
68f3c5e403
Root-causes and fixes the real, disclosed defect left open at the end of the previous STEP20 commit: the board-level SPI host interface produced wrong compute results when jobs were dispatched with realistic (widely time-separated) pacing, even though job registration itself was already confirmed correct at the dependency_manager handshake. Root cause: nms_weight_packed.v and nms_activation_replicated.v both used a REGISTERED SRAM read (rd_data_reg <= mem[addr], one full clock of latency), but nms_memory_manager_stream_wide.v's own read-ahead pipeline (its `rd_pending` bit) is designed around a COMBINATIONAL read -- a request issued this cycle produces data already valid to capture the very next cycle. A busy, multi-tile job (e.g. the STEP19 D-Stress regression, 16 tiles/neuron) never exposes the mismatch, since its own weight/activation prefetch always runs far enough ahead that any given tile has been sitting stable in the SRAM for many cycles by the time it's actually consumed. An uncontested single-tile job has zero such margin: its one tile's read fires on the exact edge the data nominally becomes ready, landing squarely on the missing cycle and permanently latching stale/zero data. Fixed by making both SRAMs' reads combinational, with an explicit same-cycle fill/read address-match bypass for the one hazard a plain combinational read alone would still miss. No FSM, arbiter, or SDRAM controller logic was touched. Verified (Verilator, per this project's own standing DEC-0004 protocol): - tb_fpga_neural_v2_top_smoke.v: 11/11 PASS -- single job, back-to-back jobs, a realistic ~85us-gap job pair, and a parametric sweep of inter-job gaps (100ns/5000ns/50000ns). - STEP19 D-Stress N=2: 49788 cycles, 256/256 bit-exact -- identical cycle count to before this fix (zero regression). - STEP19 D-Stress N=4: 49771 cycles, 256/256 bit-exact -- identical cycle count to before this fix (zero regression). - tb_sdram_unified_backend.v (40/40) and tb_spi_host_bridge.v (18/18) reconfirmed unaffected. The physical SPI host interface is now verified correct end-to-end. Real synthesis/P&R of the board-level top (fpga_neural_v2_top.v) is the deliberate next step, not yet performed this round. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
90 lines
6.6 KiB
Markdown
90 lines
6.6 KiB
Markdown
# FPGA-Neural V2 — CHIP READINESS
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Precise, non-vague criteria per the governing spec's own definition:
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V2 hardware is READY only when EVERY box below is checked. If even one
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fundamental item is missing, **HARDWARE READY = NO** — no OPEN ITEM is
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masked.
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```
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[x] RTL frozen -- nms_neural_multiprocessor_sdram_unified.v,
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zero V1 dependency, strict lint clean
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[x] regression PASS -- 461/461 (isolated controller, 9 configs),
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40/40 (isolated unified backend)
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[x] bit-exact PASS -- 256/256 neurons, N=2 AND N=4, single SDRAM
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[x] SDRAM validation PASS -- init/refresh/read/write/burst/masked-write,
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40 real refresh events, zero corruption
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[x] N4 synthesis PASS -- real Yosys 0.68+post, zero errors
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[ ] N4 timing >= 80 MHz -- MARGINAL: only 1/8 real P&R seeds pass
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[ ] constraints complete -- v2_unified.lpf exists, REAL and P&R-verified
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for 39/149 signals (clk/rst + full SDRAM bus);
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110-signal host bus still unassigned
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[ ] pinout complete -- 149-signal inventory complete; SDRAM+clk/rst
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(39 signals) REALLY assigned from the official
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Lattice CSV and P&R-confirmed; host bus (110
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signals) deliberately unassigned (see below)
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[ ] clock defined -- real EHXPLLL RTL now exists (STEP20,
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ecp5_pll_sys_clk.v, 16MHz->64MHz), NOT yet
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confirmed by synthesis/P&R of the board top
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[ ] power defined -- rail voltages known; regulators NOT selected
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[ ] FPGA configuration defined -- standard pins identified; flash NOT chosen
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[x] host interface defined -- STEP20: real SPI protocol engine
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(spi_host_bridge.v), verified correct
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end-to-end (11/11, board-level smoke test),
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zero regression to the STEP19 baseline
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[x] schematic requirements complete -- SCHEMATIC_READINESS.md's own block diagram
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and interconnection list are complete
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[x] first-power-on test defined -- FIRST_POWER_ON.md's own 12-step procedure
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[ ] bitstream reproducible -- NOT verified: no ball-assigned LPF exists to
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produce a REAL, board-usable bitstream from;
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the free-placement bitstreams used for
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verification this round are reproducible
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AS SIMULATION/FIT PROOFS ONLY, not as a
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real board-programmable artifact
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```
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**8 of 14 items checked. HARDWARE READY = NO.**
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**STEP20 update:** a real SPI host interface (`spi_host_bridge.v` +
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`fpga_neural_v2_top.v`) now exists AND is verified correct end-to-end
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(errors.log's "ERR-0025 Part B — RESOLUTION": a registered- vs
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combinational-read SRAM timing bug, found via the board-level smoke
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test, root-caused, fixed with zero regression to the STEP19 baseline)
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— "host interface defined" is now checked. A real EHXPLLL clock
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wrapper also now exists (`ecp5_pll_sys_clk.v`) but has not yet been
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through synthesis/P&R of the board-level top, so "clock defined"
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remains unchecked for that specific, narrower reason. The STEP19 core
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(raw `reg_*` interface) remains bit-exact verified and was reconfirmed
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fresh this session via Verilator after an unrelated Icarus Verilog
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v13.0 toolchain regression was found and ruled out (ERR-0024).
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## Why each unchecked item is unchecked (no vague language)
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| Item | Why NOT checked |
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|---|---|
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| N4 timing ≥80MHz | 8 real P&R seeds measured; only 1 (81.84MHz) clears 80MHz. This is a real MARGINAL result, not a PASS, per the governing spec's own explicit classification rule (some seeds pass, most do not). |
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| Constraints complete | `v2_unified.lpf` real and P&R-verified for 39/149 signals (clock frequency + clk/rst + the full 37-signal SDRAM bus, sourced from the real Lattice pinout CSV found at `~/Downloads/` during this step's own pre-commit review). The 110-signal host bus is deliberately left unassigned. |
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| Pinout complete | Signal inventory is complete (149, exactly matching real P&R); SDRAM+clk/rst (39 signals, 26%) are now really assigned and P&R-confirmed; the 110-signal host bus is unassigned, not because pin data is missing, but because that bus is not yet a real physical protocol (see below) — assigning it balls now would be premature. |
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| Clock defined | A real EHXPLLL wrapper now exists (`ecp5_pll_sys_clk.v`, STEP20, real Project Trellis `ecppll`-generated parameters, 16MHz->64MHz) and is instantiated in the board-level top, but has NOT yet been confirmed by synthesis/P&R of that top — deliberately deferred until ERR-0025 Part B was resolved (decisions.log DEC-0037). |
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| Power defined | Rail VOLTAGES are known from real datasheets; regulator SELECTION, CURRENT budget, and decoupling are not — no real power-estimation tool was run, and the previously-referenced board power-tree design is not accessible this session to confirm as a concrete plan. |
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| FPGA configuration defined | Standard ECP5 config pins (TDI/TDO/TCK/TMS/PROGRAMN/INITN/DONE/CCLK) are correctly identified as existing and standard, but no configuration-flash part number or SPI-vs-JTAG-only bring-up approach has been chosen for V2 specifically. |
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| Bitstream reproducible | Every P&R run this project has performed used free (unconstrained) I/O placement — a real, valid way to prove the design FITS the package, but not a way to produce a bitstream a real board's own fixed wiring could actually use. |
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## What this means, precisely
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The V2 hardware architecture itself — SDRAM device, controller,
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memory subsystem, compute datapath, N4/P8 configuration — is **real,
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validated, and correct**: bit-exact simulation, real synthesis, real
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place-and-route all confirm this. What remains is **entirely physical-
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integration work**: a real host interface, a real ball-level pinout, a
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real clock source decision, and real power/configuration component
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selection. None of these are memory-architecture, datapath, or
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correctness questions anymore — they are the next, concrete, well-
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defined engineering tasks, precisely enumerated in OPEN_ITEMS.md.
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## Final answer
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```
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HARDWARE FREEZE: PASS (architectural decision + RTL correctness)
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CHIP READY: NO
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```
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