micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
93 lines
4.3 KiB
Markdown
93 lines
4.3 KiB
Markdown
# NMS Activation Fill Controller Timing (STEP14 Part B)
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Status: fixed, real post-P&R verified, bit-exact, adopted. Full data:
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`hardware/v2/reports/step14_activation_timing.csv`. Full narrative:
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`hardware/v2/logs/experiments.log` (EXP-0029, 0030, 0031),
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`decisions.log` (DEC-0026, DEC-0027).
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## B1 — Exact critical path (not assumed)
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Mined directly from the real nextpnr-ecp5 P&R report for
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`nms_neural_multiprocessor_stream.v` at N_SLOTS=4
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(Fmax=55.22 MHz, FAIL @ 80 MHz). Full path, 18.11 ns total (6.25 ns
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logic + 11.85 ns routing):
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```
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SOURCE: u_act_fill.resident_tag[11] (register Q)
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-> COMBINATIONAL, chained, NO register in between:
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(1) max_n_tiles computation, nms_activation_fill_ctrl.v:92
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(N_SLOTS-wide running-max fold, each iteration gated by a
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23-bit tag-equality check) -- long CCU2C carry chain
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(2) resident_count < max_n_tiles comparison, line 165
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(the ST_IDLE refill/continue decision) -- ANOTHER 16-bit
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magnitude-comparison carry chain, feeding directly off (1)
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in the SAME cycle
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(3) into pf_start's own next-state logic
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DESTINATION: u_act_fill.pf_addr's clock-enable (CE) pin
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```
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Two full 16-bit magnitude comparisons sit in **one** combinational
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cone across **one** clock edge. This confirms, at the exact RTL-line
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level, the failure class DEC-0016/EXP-0022 predicted analytically
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("O(N_SLOTS) unpipelined combinational scan feeding directly into a
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control decision") — but precisely localizes it to the comparison
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logic (lines 92 and 165), *not* the priority-encoder
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(`desired_valid`/`desired_x_base`, lines 77-86), which does not appear
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in this critical path at all.
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## B2 — Scaling behavior
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The bottleneck is the `max_n_tiles` running-max fold: an imperative
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`for` loop creates a data dependency between iterations (`max_n_tiles`
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after iteration *i* depends on iteration *i-1*), which Yosys
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synthesizes as a sequentially-chained carry structure — inherently
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O(N_SLOTS) deep, not O(log N_SLOTS). At N_SLOTS=4 the chain reached
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6.25 ns logic + 11.85 ns routing; at N_SLOTS=8 it doubles again (see
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below).
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## B3 — Minimum fix (two iterations, evidence-driven)
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**v2** (one pipeline stage: register `max_n_tiles` before its use in
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the `resident_count` comparison): Fmax 55.22 → 72.78 MHz (+31.8%) —
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real improvement, still fails 80 MHz. Re-tracing showed the *remaining*
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critical path was entirely inside `max_n_tiles`'s own computation
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(now feeding its own register), confirming the fix needed to go one
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level deeper.
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**v3** (second stage: register each slot's tag-equality/masking result
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first — independent per-slot work, no N_SLOTS-dependent chain — *then*
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fold the already-registered, already-masked values): Fmax 55.22 →
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**106.81 MHz** (+93.4%). **PASSES** 80 MHz with real margin. Resource
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cost: LUT4 -5.5%, FF +1.4% (2 added pipeline registers), CCU2C
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unchanged.
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## B4 — No serialization reintroduced
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Verified directly: N_SLOTS=2 bit-exact regression test (D-Stress, real
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V1 PSRAM chain) gives **numerically identical** cycle count and
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sustained MAC/cycle before and after the fix (185270/185270 cycles,
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0.1769/0.1769 MAC/cycle). The 3 total cycles of added latency apply
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only to the rare, tile-refill-boundary-only decision — never to the
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real-time per-tile consumption path (already fully decoupled by
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STEP13's own streaming manager). Higher Fmax, zero throughput cost —
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satisfying B4's explicit requirement.
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## N=8 (exploratory)
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`nms_activation_fill_ctrl_v3.v` at N_SLOTS=8: DSP=64/72 (89%, FEASIBLE),
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LUT4=4653, FF=10855 (both comfortably FEASIBLE). **Fmax=52.25 MHz,
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FAILS 80 MHz** — the v3 fix's second stage (the max-fold itself) is
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still O(N_SLOTS)-deep; at N=8 it is twice as deep as at N=4 and becomes
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dominant again. This is expected: v3 shifted the crossover point, it
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did not eliminate the underlying dependency. A genuine balanced-tree
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reduction (or a pipeline scaling with log₂(N_SLOTS) rather than a flat
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2-stage split) would be required for N=8 — not undertaken this round
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(N=8 is explicitly exploratory; the limiting resource (Fmax, not
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DSP/LUT/FF/BRAM) is precisely identified and quantified, per spec).
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## Adoption
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`nms_activation_fill_ctrl_v3.v` is adopted as the reference activation
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fill controller for N_SLOTS≥4 configurations (DEC-0027). The original
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and the insufficient v2 are preserved for reference.
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