122 lines
3.0 KiB
Verilog
122 lines
3.0 KiB
Verilog
module mac8 #(
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parameter DATA_WIDTH = 16,
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parameter ACC_WIDTH = 40
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)(
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input signed [DATA_WIDTH*8-1:0] x_bus,
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input signed [DATA_WIDTH*8-1:0] w_bus,
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input signed [ACC_WIDTH-1:0] acc_in,
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output signed [ACC_WIDTH-1:0] acc_out
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);
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wire signed [ACC_WIDTH-1:0] m0;
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wire signed [ACC_WIDTH-1:0] m1;
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wire signed [ACC_WIDTH-1:0] m2;
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wire signed [ACC_WIDTH-1:0] m3;
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wire signed [ACC_WIDTH-1:0] m4;
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wire signed [ACC_WIDTH-1:0] m5;
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wire signed [ACC_WIDTH-1:0] m6;
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wire signed [ACC_WIDTH-1:0] m7;
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wire signed [ACC_WIDTH-1:0] s0;
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wire signed [ACC_WIDTH-1:0] s1;
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wire signed [ACC_WIDTH-1:0] s2;
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wire signed [ACC_WIDTH-1:0] s3;
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wire signed [ACC_WIDTH-1:0] s4;
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wire signed [ACC_WIDTH-1:0] s5;
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wire signed [ACC_WIDTH-1:0] sum;
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mac_unit #(
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.DATA_WIDTH(DATA_WIDTH),
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.ACC_WIDTH(ACC_WIDTH)
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) mac0 (
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.x(x_bus[0*DATA_WIDTH +: DATA_WIDTH]),
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.w(w_bus[0*DATA_WIDTH +: DATA_WIDTH]),
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.acc_in({ACC_WIDTH{1'b0}}),
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.acc_out(m0)
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);
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mac_unit #(
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.DATA_WIDTH(DATA_WIDTH),
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.ACC_WIDTH(ACC_WIDTH)
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) mac1 (
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.x(x_bus[1*DATA_WIDTH +: DATA_WIDTH]),
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.w(w_bus[1*DATA_WIDTH +: DATA_WIDTH]),
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.acc_in({ACC_WIDTH{1'b0}}),
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.acc_out(m1)
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);
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mac_unit #(
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.DATA_WIDTH(DATA_WIDTH),
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.ACC_WIDTH(ACC_WIDTH)
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) mac2 (
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.x(x_bus[2*DATA_WIDTH +: DATA_WIDTH]),
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.w(w_bus[2*DATA_WIDTH +: DATA_WIDTH]),
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.acc_in({ACC_WIDTH{1'b0}}),
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.acc_out(m2)
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);
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mac_unit #(
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.DATA_WIDTH(DATA_WIDTH),
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.ACC_WIDTH(ACC_WIDTH)
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) mac3 (
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.x(x_bus[3*DATA_WIDTH +: DATA_WIDTH]),
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.w(w_bus[3*DATA_WIDTH +: DATA_WIDTH]),
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.acc_in({ACC_WIDTH{1'b0}}),
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.acc_out(m3)
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);
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mac_unit #(
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.DATA_WIDTH(DATA_WIDTH),
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.ACC_WIDTH(ACC_WIDTH)
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) mac4 (
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.x(x_bus[4*DATA_WIDTH +: DATA_WIDTH]),
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.w(w_bus[4*DATA_WIDTH +: DATA_WIDTH]),
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.acc_in({ACC_WIDTH{1'b0}}),
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.acc_out(m4)
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);
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mac_unit #(
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.DATA_WIDTH(DATA_WIDTH),
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.ACC_WIDTH(ACC_WIDTH)
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) mac5 (
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.x(x_bus[5*DATA_WIDTH +: DATA_WIDTH]),
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.w(w_bus[5*DATA_WIDTH +: DATA_WIDTH]),
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.acc_in({ACC_WIDTH{1'b0}}),
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.acc_out(m5)
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);
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mac_unit #(
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.DATA_WIDTH(DATA_WIDTH),
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.ACC_WIDTH(ACC_WIDTH)
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) mac6 (
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.x(x_bus[6*DATA_WIDTH +: DATA_WIDTH]),
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.w(w_bus[6*DATA_WIDTH +: DATA_WIDTH]),
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.acc_in({ACC_WIDTH{1'b0}}),
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.acc_out(m6)
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);
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mac_unit #(
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.DATA_WIDTH(DATA_WIDTH),
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.ACC_WIDTH(ACC_WIDTH)
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) mac7 (
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.x(x_bus[7*DATA_WIDTH +: DATA_WIDTH]),
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.w(w_bus[7*DATA_WIDTH +: DATA_WIDTH]),
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.acc_in({ACC_WIDTH{1'b0}}),
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.acc_out(m7)
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);
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assign s0 = m0 + m1;
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assign s1 = m2 + m3;
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assign s2 = m4 + m5;
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assign s3 = m6 + m7;
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assign s4 = s0 + s1;
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assign s5 = s2 + s3;
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assign sum = s4 + s5;
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assign acc_out = acc_in + sum;
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endmodule |