micheleandClaude Sonnet 5
81a9619214
hardware/v1/ was created (dc0b331) as a frozen snapshot of the V1
project that then lived at the repo root (rtl/, sim/, synth/, tools/,
docs/). Root received zero further commits to those files after the
freeze -- confirmed byte-identical to the hardware/v1/ copy for every
file removed here. Root was the "before", hardware/v1/ is the
curated, canonical "after".
Removed (all verified exact-hash duplicates of hardware/v1/ content):
- rtl/ (20 files, 100% covered by hardware/v1/rtl/)
- tools/{netasm,pinout,run_regression.py,flash_catalog,validation,
fpga_benchmark.py} (19 files, 100% covered by hardware/v1/tools/;
tools/neural_sim/ kept -- unique, post-freeze, no counterpart)
- sim/*.v (47 testbenches, 100% covered by hardware/v1/sim/; the
~38 remaining sim/ entries are compiled binaries and .vcd
waveform dumps, left as a separate cleanup decision)
- synth/ecp5/{p2,p4,p8,post_fix_verify} (25 files, exact duplicates
of hardware/v1/synthesis/; the other ~84 synth/ecp5/* experiment
build directories are historical artifacts never carried into the
freeze, left as a separate decision)
- WORKLOG.md (duplicate of hardware/v1/docs/WORKLOG.md)
- docs/{FPGA-Neural-Datapatch-Benchmark,FPGA-Neural-Hardware-Design,
FPGA-NeuralNetwork-Engine}.md, docs/validation/*.md (18 files),
docs/FPGA-Neural-Datasheet-{EN,IT}.pdf -- all exact duplicates of
hardware/v1/docs/ content
- hardware/v1/docs/DatasheetLatex/ (24 files) -- exact duplicate of
hardware/v2/docs/datasheet/files/docs/datasheet/en/ (discovered
during this audit; not the same DatasheetLatex already removed
from hardware/v2/docs/ in an earlier commit)
Moved (genuine, unique, post-freeze V2 content -- not duplicated
anywhere, just living in the wrong/legacy root docs/ location):
- docs/architecture/*.md -> hardware/v2/docs/architecture/
- docs/pinouts.md, docs/FPGA_NEURAL_V2_DATASHEET.md,
docs/FPGA_NEURAL_V2_SCHEMATIC.md,
docs/FPGA-Neural-V2-Datasheet-EN.pdf -> hardware/v2/docs/
Left untouched (separate decisions, not part of this cleanup):
- docs/FPGA-Neural-Flash-Subsystem-Verification.md, docs/
v2-description.md -- orphaned root-only content, no duplicate
found anywhere, but also not part of the reviewed plan
- synth/ecp5/* experiment dirs and sim/*_sim + sim/*.vcd build
artifacts -- not literal duplicates, flagged as candidates for a
future, separate cleanup pass
Verified no functional breakage: grepped all remaining scripts/docs
for references to every removed path -- only prose/comment mentions
found, no executable imports or build-script paths broken.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
187 lines
9.1 KiB
Markdown
187 lines
9.1 KiB
Markdown
# FPGA-Neural V2 — Datasheet
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**Status: DRAFT / PRE-RELEASE.** This datasheet documents the INTENDED
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V2 board architecture as of STEP20. It does **not** certify a finished,
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release-ready design — see §11 Limitations and
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`hardware/v2/docs/OPEN_ITEMS.md` for the current, real blocker list.
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Do not read any statement here as "physically validated" unless it
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says so explicitly.
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## 1. General
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FPGA-Neural V2 is an embedded neural-network accelerator built around a
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Lattice ECP5 FPGA and a single external SDRAM. It executes small,
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dependency-graph-structured INT8 neural networks (dense layers, DAGs)
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using a Neural Multiprocessor of parallel MAC engines, streaming
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weight/activation tiles from one external SDRAM chip that also holds
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results.
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Architecture stack (top to bottom): SPI host interface → job
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registration → Dependency Manager / Neural Director → N parallel
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Neural Processors → Memory Manager / streaming tile delivery → Unified
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SDRAM Backend → one physical SDRAM.
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## 2. FPGA
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| Item | Value | Basis |
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| Part | Lattice LFE5U-45F | DESIGN DECISION |
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| Package | CABGA381 | DESIGN DECISION |
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| Speed grade | -8 | DESIGN DECISION |
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| Ordering part number | LFE5U-45F-8BG381C | DESIGN DECISION (standard Lattice ordering suffix for this grade/package; not independently cross-checked against a live distributor listing this session) |
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| Logic (post-synthesis, N=4, frozen STEP19 compute core) | TRELLIS_FF=6425, TRELLIS_COMB=6023, MULT18X18D=32, DP16KD=0 | VERIFIED (real Yosys synthesis, STEP19) |
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| I/O used (frozen STEP19 top, no physical host bus) | 149/245 TRELLIS_IO | VERIFIED (real nextpnr-ecp5 P&R, STEP19) |
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| I/O used (this step's new board-level top, SPI + osc + reset + SDRAM) | not yet synthesized this round | OPEN — see §11 |
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Operating assumption: single clock domain, no CDC beyond the SPI
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bridge's own double-flop synchronizers and the reset synchronizer
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(§5).
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## 3. Neural accelerator
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| Parameter | Value |
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|---|---|
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| N_PROCESSORS | 4 (frozen reference; N=2 also validated; N=8 is a future evolution) |
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| P_IN (MAC width) | 8 |
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| Data representation | INT8 operands |
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| Accumulator | INT32, ReLU + INT8 saturate on output |
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| MAC architecture | 8-wide parallel MAC, balanced adder tree (`neural_processor.v`, unchanged since before this freeze) |
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| Processor parallelism | N independent Neural Processors, one dependency-graph node in flight per processor |
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| Supported memory traffic | weights (read-only, 64-bit packed fetch, cached), activations (read, byte-maskable), results (write, byte-maskable) — all through the SAME single SDRAM |
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**RTL capability vs. software/API capability:** the RTL executes one
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pre-compiled dependency graph (nodes with producer/consumer edges,
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fixed tile counts) registered via 108 bits of per-job configuration
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(node id, dependency list, activation/weight/result base addresses,
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tile count). There is no on-chip graph compiler, no floating point, no
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training — job graphs and addresses are computed off-chip and loaded
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via the host interface (§9).
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## 4. Unified memory
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```
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┌─────────────────────┐
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│ FPGA ECP5 │
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│ │
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│ 4x Neural Engines │
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│ │ │
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│ v │
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│ Unified SDRAM │
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│ Backend / Arbiter │
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└─────────┬───────────┘
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│ 16-bit SDRAM bus
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v
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┌─────────────────────┐
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│ AS4C4M16SA-6TIN │
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│ Weights │
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│ Activations │
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│ Results │
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└─────────────────────┘
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```
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| Item | Value | Basis |
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| Device | Alliance Memory AS4C4M16SA-6TIN | DESIGN DECISION (STEP16-19) |
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| Capacity | 4M x 16 (8MB) | DATASHEET VALUE |
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| Data width | 16-bit (DQ[15:0]) + DQM[1:0] byte mask | DATASHEET VALUE |
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| Addressing | BA[1:0] (4 banks) + A[11:0] (row/col, multiplexed) | DATASHEET VALUE |
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| Clock | shared with FPGA system clock (§5) | DESIGN DECISION |
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| Initialization/refresh | real, RTL-implemented power-up wait + mode-register-set + periodic AUTO REFRESH (`sdram_controller.v`) | VERIFIED (real refresh events observed in simulation, STEP16-19) |
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| Arbitration | single physical port, 2-way logical split: W (weight, read-only, cached) / AR (activation+result, read/write, byte-maskable), each internally arbitrated across N processors by a generic, reused `slot_mem_arbiter` | VERIFIED (STEP19 bit-exact regression, reconfirmed via Verilator this step — see errors.log ERR-0024) |
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| Official V2 memory map | weights @0x010000, activations @0x200000, results @0x300000, all within the single 8MB space, 1MB-aligned | DESIGN DECISION |
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PSRAM is **not** part of V2. The V1 PSRAM controller (`hardware/v1/rtl/psram_controller.v`) is not instantiated anywhere in the V2 physical path.
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## 5. Clock / PLL
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```
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16 MHz OSCILLATOR
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v
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ECP5 PLL (EHXPLLL)
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CLKI_DIV=1 CLKFB_DIV=4 CLKOP_DIV=9
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FEEDBK_PATH=CLKOP VCO=576MHz
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v
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FPGA SYSTEM CLOCK
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64 MHz
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(real, tool-generated ratio: 16 * 4 / 1, CLKOP_DIV=9 -> 576/9=64)
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```
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| Item | Value | Basis |
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| Oscillator | 16 MHz (board-level, prior project record) | DESIGN DECISION (part number: TBD — not selected this session) |
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| PLL primitive | EHXPLLL (`ecp5_pll_sys_clk.v`) | VERIFIED design-time via Project Trellis `ecppll` v1.4 (real tool, real parameters) |
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| Generated system clock | 64 MHz | DESIGN DECISION, chosen over 80MHz because STEP19's own multi-seed P&R data showed only 1/8 seeds closing timing at >=80MHz on the compute-only core, and the new board-level top adds more logic still; 64MHz is not yet itself confirmed by P&R on the NEW top (see §11) |
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| PLL lock | `locked` output, feeds `reset_sync.v` | DESIGN DECISION; NOT simulatable (Lattice EHXPLLL has no open sim model) — real lock behavior is a real-hardware-only characterization, see §10 |
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| Timing constraints | none yet written for the new board-level top | OPEN — see §11 |
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## 6. Interfaces
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### SPI host interface (`spi_host_bridge.v`)
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Mode 0 (CPOL=0/CPHA=0), MSB-first, one opcode per CS-low period.
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Opcodes: `0x10` WRITE_JOB (job registration, 15-byte payload), `0x01`
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WRITE_MEM / `0x02` READ_MEM (raw, word-addressed SDRAM access via a
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second arbitrated port), `0x20` STATUS, `0x0F` RESET. Verified in
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isolation (18/18, `tb_spi_host_bridge.v`). **Not yet verified
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end-to-end under realistic multi-job pacing** — see §11/ERR-0025.
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The 110-pin `reg_*` bus used by V2's own internal simulation
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testbenches is a testbench-only convenience and is **not** the
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physical interface.
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### JTAG
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Standard ECP5 JTAG (TDI/TDO/TCK/TMS), always available regardless of
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configuration boot mode, per Lattice's own standard requirement.
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### Configuration
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Standard ECP5 PROGRAMN/INITN/DONE/CCLK. Boot-mode/flash-part decision:
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OPEN (see §11).
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## 7. Electrical
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Rail voltage requirements are DATASHEET VALUEs (from real device
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datasheets); no regulator part numbers, current budget, or decoupling
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values are finalized this round. Full detail:
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`hardware/v2/docs/POWER_ARCHITECTURE.md`.
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## 8. Pinout
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Full table: `hardware/v2/docs/PINOUT.md`. Summary: 37 real SDRAM
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signals + clk/rst are ball-assigned and P&R-verified (STEP19, against
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the STEP19 compute-only top). The board-level top added this step
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(SPI + oscillator + reset pins) has **not** had its own ball
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assignment or P&R run yet.
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## 9. Mechanical / board assumptions
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None assumed beyond the package footprint implied by CABGA381. No PCB
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dimensions, connector placement, or stack-up are specified — that is
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schematic/PCB-capture work, not yet started (see
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`hardware/v2/docs/SCHEMATIC_READINESS.md`).
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## 10. Programming / first power-on
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JTAG programming is standard. A first-power-on procedure exists at
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`hardware/v2/docs/FIRST_POWER_ON.md` (procedure only — not executed
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against real hardware, since no board has been fabricated).
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## 11. Limitations (real, current, as of this datasheet's own writing)
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- **The physical SPI host interface is NOT proven end-to-end
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correct.** A real, disclosed defect (errors.log ERR-0025 Part B)
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produces wrong results when two jobs are dispatched with realistic
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SPI pacing, even though registration itself is confirmed correct.
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This is the single largest open item.
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- The board-level top (`fpga_neural_v2_top.v`) has not been through
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synthesis or P&R this round — deliberately, since running the real
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toolchain against RTL known to compute wrong answers would not be a
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meaningful result.
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- No PCB, schematic capture, or fabricated hardware exists. Nothing in
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this document should be read as "physically validated."
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- Regulator, configuration-flash, and connector part numbers are not
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selected.
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- The STEP19 compute+memory core (raw `reg_*` interface, no SPI
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bridge) IS bit-exact verified (N=2 and N=4, 256/256, reconfirmed via
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Verilator this session) and remains the actual, working reference
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design underneath this datasheet's own described board architecture.
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