micheleandClaude Sonnet 5
cc6cfe168e
architecture.tex: document the real MAC-pipeline fix (Stage 1a/1b split) and its real result on both N8 (WNS 0.000ns -> +0.108ns) and N16 (now closed, WNS=+0.269ns) -- N16 is a real, verified candidate for a future board revision, N8 remains the configuration in current physical fabrication. tests_timing.tex: extended P&R history table, real N8/N16 signoff tables (post-fix), the new N16 critical path (Director queue logic, still route-dominated) and the negative result of a second directive attempt (confirms current result is the best found). Added a new, clearly-labeled PROJECTION (not a measurement) for N16 vs ESP32-S3 -- 30-68x range, built from real measured scaling factors (same core count as the original ECP5 comparison, real clock ratio, real 2x INT8 packing factor) -- more grounded than the old, superseded ~55-85x figure, with the same DDR3-bandwidth-bound honest caveat carried forward. datasheet.tex: N8/N16 side-by-side timing/utilization/performance tables, open items and revision history updated to reflect physical fabrication status and the N16 candidate decision. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC