micheleandClaude Sonnet 5
ca17765fe3
Found a real, previously-masked bug in spi_host_bridge_v3.v's physical layer (inherited unchanged from V1/V2): the bit_count==0 MISO bypass corrupts the last bit of any multi-byte response whose value happens to end in a 1 -- every prior test's response data coincidentally ended in 0, hiding it until the new DEVICE_ID register (0x...01) exposed it via a real bit-exact mismatch. Fixed by removing the bypass (verified unnecessary for this protocol's actual usage). Added REG_WRITE/REG_READ opcodes (0x30/0x31) and a register file (DEVICE_ID/CONTROL/STATUS/N_SLOTS) for general device control beyond job submission, per explicit user request. Full regression: 38/38 PASS, including new cases specifically targeting the bit-corruption bug for both REG_READ and READ_MEM. New hardware/v3/constraints/n2_system_ddr3_top.xdc: reserves the FPGA's dedicated Master-SPI config-flash pins (found colliding with auto-placed design ports in the real routed checkpoint) and assigns the neural-processor management SPI to real, verified-free, edge- adjacent pins on xc7a100tcsg324-2. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
Formato dei log V2
Regola non negoziabile (docs/v2-description.md §25-29): ogni attività
significativa (modifica, simulazione, sintesi, benchmark, decisione, errore)
deve essere registrata. Nessun log viene mai sovrascritto o troncato — solo
append. Nessun ID esperimento (EXP-XXXX) o decisione (DEC-XXXX) viene mai
riutilizzato, anche se il risultato è un FAIL.
File
development.log— log principale di sviluppo, un'entry per ogni sessione di lavoro/milestone (creazione file, refactor, avanzamento roadmap).architecture.log— decisioni e note di architettura a grana fine (non scelte finali — quelle vanno indecisions.log— ma esplorazioni, alternative considerate, vincoli scoperti).simulation.log— ogni run di simulazione (Icarus/Verilator): test, vettori, cicli, PASS/FAIL, confronto bit-exact con V1, stall/memory-wait.synthesis.log— ogni run Yosys: LUT/FF/DSP/BRAM, warning, problemi CHECK.timing.log— ogni run nextpnr-ecp5: Fmax, percorso critico, WNS/TNS se disponibili. Fmax "ufficiale" di una configurazione = solo da qui, mai da simulazione o stima.benchmark.log— tabelle di confronto per configurazione (Fmax, MAC/cycle, cycles/neuron, utilization, ecc.), sempre con etichetta THEORETICAL/SIMULATED/SYNTHESIZED/POST-P&R.decisions.log— decisioni architetturali importanti, formatoDEC-XXXX(vedidocs/v2-description.md§27).experiments.log— registro principale, unEXP-XXXXper ogni esperimento end-to-end (config → sim/synth/timing → risultato), rimanda areports/experiments/EXP-XXXX/.errors.log— errori/bug/regressioni incontrati durante lo sviluppo V2 stesso (non i bug V1, già chiusi inhardware/v1/docs/validation/bugs.md).
Campi minimi per entry (§26)
timestamp, experiment_id (se applicabile), git_commit, session/agent,
module, configuration, action, reason, command, result, errors, decision,
next_action
Per synthesis/timing aggiungere: LUT, FF, DSP, BRAM, Fmax, critical path, WNS/TNS. Per simulazione: test, vectors, cycles, PASS/FAIL, bit-exact result, stall cycles, memory wait, utilization.