micheleandClaude Sonnet 5
bd1fb5dc14
Adds neural_director_grouped.v, a direct extension of neural_director_ packed.v's own already-proven 2-position pairing discipline to 8-position octets (matching systolic_group.v's fixed 4 PEs x 2 lanes). Real, deliberate finding: the host-facing SPI/WRITE_JOB submission protocol needs zero changes -- the host just submits 8 jobs sharing a weight base instead of 2, the same real pattern already required today. Real out-of-context synthesis of one systolic_group.v: 32 DSP48E1 (13.3%), confirming the original brainstorm's own DSP projection exactly. Found and fixed two real bugs: (1) a wraparound-arithmetic width bug in the octet index computation (same class already flagged for address math elsewhere in this project -- needs N+1 bits before the mod-reduce compare, not N); (2) a real, generalizable testbench race -- driving stimulus on the same clock edge the DUT samples on works fine with a natural gap between pulses (every prior testbench in this project has one) but silently double-registers data when called back-to-back with zero gap, confirmed via real signal tracing. Fixed with @(negedge clk) stimulus; CLAUDE.md's existing blocking/nonblocking testbench-race lesson extended to cover this new trigger. Verified via tb_neural_director_grouped.v: 4/4 PASS (octet dispatch + per-PE addressing, stall-not-mis-dispatch on a mismatched octet, queue wraparound). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
Formato dei log V2
Regola non negoziabile (docs/v2-description.md §25-29): ogni attività
significativa (modifica, simulazione, sintesi, benchmark, decisione, errore)
deve essere registrata. Nessun log viene mai sovrascritto o troncato — solo
append. Nessun ID esperimento (EXP-XXXX) o decisione (DEC-XXXX) viene mai
riutilizzato, anche se il risultato è un FAIL.
File
development.log— log principale di sviluppo, un'entry per ogni sessione di lavoro/milestone (creazione file, refactor, avanzamento roadmap).architecture.log— decisioni e note di architettura a grana fine (non scelte finali — quelle vanno indecisions.log— ma esplorazioni, alternative considerate, vincoli scoperti).simulation.log— ogni run di simulazione (Icarus/Verilator): test, vettori, cicli, PASS/FAIL, confronto bit-exact con V1, stall/memory-wait.synthesis.log— ogni run Yosys: LUT/FF/DSP/BRAM, warning, problemi CHECK.timing.log— ogni run nextpnr-ecp5: Fmax, percorso critico, WNS/TNS se disponibili. Fmax "ufficiale" di una configurazione = solo da qui, mai da simulazione o stima.benchmark.log— tabelle di confronto per configurazione (Fmax, MAC/cycle, cycles/neuron, utilization, ecc.), sempre con etichetta THEORETICAL/SIMULATED/SYNTHESIZED/POST-P&R.decisions.log— decisioni architetturali importanti, formatoDEC-XXXX(vedidocs/v2-description.md§27).experiments.log— registro principale, unEXP-XXXXper ogni esperimento end-to-end (config → sim/synth/timing → risultato), rimanda areports/experiments/EXP-XXXX/.errors.log— errori/bug/regressioni incontrati durante lo sviluppo V2 stesso (non i bug V1, già chiusi inhardware/v1/docs/validation/bugs.md).
Campi minimi per entry (§26)
timestamp, experiment_id (se applicabile), git_commit, session/agent,
module, configuration, action, reason, command, result, errors, decision,
next_action
Per synthesis/timing aggiungere: LUT, FF, DSP, BRAM, Fmax, critical path, WNS/TNS. Per simulazione: test, vectors, cycles, PASS/FAIL, bit-exact result, stall cycles, memory wait, utilization.