micheleandClaude Sonnet 5
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Begins the V2 Neural Multiprocessor / Dataflow architecture per docs/v2-description.md, per explicit user request to freeze V1 and start V2 development, copying from V1 what's needed. Scaffold: - hardware/v1/: byte-exact, read-only copy of the current V1 codebase (rtl, testbenches, tools, constraints, a representative subset of synthesis results, and reference docs) -- verified identical via diff/cmp against the live top-level tree before being made filesystem-read-only. The live top-level tree is untouched and remains the project's "production" V1 (see hardware/v1/README.md and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move). - hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/ reports/scripts/logs/docs) plus the full logging system required by the spec (development/architecture/simulation/synthesis/timing/ benchmark/decisions/experiments/errors.log). M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v): - 8-stage pipelined perceptron unit (P_IN=8): input align, 8 multipliers, 3-level adder tree, accumulator, bias+activation, INT8 saturation. Genuine 1-tile/cycle throughput, not just a wider combinational datapath. - 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with 4 baseline states merged into NP_WAIT_OPERANDS -- see decisions.log DEC-0002); valid/ready/data/last stream interfaces per §7. - Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v), covering regular/mixed-sign/extreme-INT8 vectors, both activations, a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile job -- verified with Verilator (see below for why). - Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24 (a user-requested comparison experiment, also bit-exact-verified; see experiments.log EXP-0001/EXP-0002 and benchmark.log). Three real bugs found and resolved during M1 development (full diagnostic record in errors.log): - Two independent, reproducible Icarus Verilog v13.0 scheduling defects (ERR-0001, ERR-0002) that silently produced wrong simulation results for standard sequential Verilog -- confirmed via Verilator 5.050 giving correct results on the same minimal repros. Verilator is now the trusted simulator for hardware/v2/ (decisions.log DEC-0004); Icarus's affected protocol-violation check was removed from the RTL and deferred architecturally to the Neural Director (DEC-0003) rather than chased further. - One real RTL bug (ERR-0003): last0 wasn't gated like valid0, letting a "last tile" tag leak into the pipeline ahead of its actual valid tile on back-to-back jobs. Fixed and verified. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
31 lines
1.8 KiB
Markdown
31 lines
1.8 KiB
Markdown
# C.10 — Timing (Fmax reale, percorso critico, sweep di seed)
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Data: 2026-09-04. Certificato per citazione di lavoro reale già svolto in questa stessa
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sessione, con numeri ri-misurati (non presi dalla parola di documenti precedenti) durante il
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lavoro sul sottosistema flash e sulla sua indipendenza elettrica (Fasi F1-F7).
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## Evidenza
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- **Fmax rimisurata ad ogni cambiamento strutturale rilevante**, non una singola cifra
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presa per buona: 54.58 → 75.30 (timing closure) → 73.88 (pin attenzione host) → 66.68
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(sottosistema flash) → **67.91 MHz (bus flash reso indipendente, Fase F7, build
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corrente)** — ogni passaggio con log reale di `nextpnr-ecp5` citato, non un'affermazione.
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- **Percorso critico verificato esplicitamente identico** ad ogni ri-sintesi (non assunto
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invariato): `u_graph_engine.u_neuron.group_index → u_mac8 → catena di riporto
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dell'accumulatore in neuron_parallel.v` — stesso percorso dalla Fase 7 (timing closure)
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fino alla build corrente con sottosistema flash, confermato leggendo il report di
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`nextpnr-ecp5`, non presunto.
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- **Sweep di seed** (5 seed, P2 e P8) già eseguito e documentato in `WORKLOG.md`
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("Timing closure di `neuron_parallel`") — banda di rumore caratterizzata, usata per
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distinguere un vero guadagno/perdita da rumore di piazzamento in tutte le ri-sintesi
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successive di questa sessione (incl. la spiegazione del calo 73.88→66.68→67.91 MHz come
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rumore, non regressione, verificata contro quella banda).
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- **Margine sull'oscillatore reale (16 MHz)** ricalcolato ad ogni passaggio: attualmente
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4.24× con Fmax 67.91 MHz.
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## Verdetto
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**CERTIFICATO.** Nessun numero preso sulla parola: ogni Fmax citata in questo documento è
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stata effettivamente rimisurata con `nextpnr-ecp5` reale in questa sessione, non copiata da
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un documento precedente.
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