micheleandClaude Sonnet 5
55c827bedf
PSRAM page-mode read burst support in psram_controller.v: enables the ISSI IS66WVE4M16EBLL-70BLI's page mode via its configuration-register software-access sequence at boot (disabled by default on the real chip), then keeps CE#/OE# asserted after a read so a same-page continuation only pays tAPA (20ns) instead of a full tAA (70ns) random access, with automatic tCEM-safe session closing. Only a WRITE closes the page -- byte-enable changes do not, since int8_memory_access.v alternates them on nearly every access and an early implementation attempt that treated them as a close condition measured a real regression (53.25->61.25 cycles/edge) before being corrected (53.25->37.53 cycles/edge, +42% gather bandwidth). sim/psram_model.v gained independent tAPA/tAA and tCEM enforcement (with a real Verilog same-timestep event-ordering race found and fixed via a #0 sync) so the regression proves real timing compliance, not just data correctness. New sim/psram_page_mode_tb.v; full 26-file regression suite re-run clean. Real nextpnr-ecp5 Fmax re-measured on the full spi_neuron_top system: 75.73MHz (P2, up from 55.59MHz) and 65.13MHz (P8) -- still under the 80MHz target but not regressed, with the critical path confirmed (not assumed) to remain entirely inside neuron_parallel's accumulate chain, never psram_controller. Also includes this session's other already-validated work: the graph engine (Type #2 sparse-graph network: act_buffer, graph_engine, netasm host assembler), real CABGA381 pinout (.lpf, place&route verified) and physical IRQ_N/DATA_READY_N pins, and Phase 7 timing closure logs -- all previously uncommitted, documented in WORKLOG.md. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01LH3jPeJ3eFMfF2v8SQhpkk
391 lines
14 KiB
Verilog
391 lines
14 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// GRAPH_ENGINE TESTBENCH (Phase G3)
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//
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// End-to-end test of graph_engine through the REAL memory stack
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// (int8_memory_access + memory_interface + psram_controller +
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// psram_model), same harness style as sim/graph_format_tb.v.
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//
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// Graph under test (§3 worked example, hand-computed):
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// 4 inputs: x0=10, x1=1, x2=4, x3=0 (unused by any edge).
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// n4 (out_id=4, ACT_RELU, bias=2): 2 real edges (src=0,w=5),
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// (src=1,w=-3), PARALLEL=4 so n_conn_padded=4 -> 2 host-inserted
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// zero-weight padding edges (src=0,w=0) x2. Exercises §2.6
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// padding end to end, not just as a format detail.
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// sum = 10*5 + 1*(-3) + 0 + 0 = 47; +bias(2) = 49; relu -> 49.
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// n5 (out_id=5, ACT_NONE, bias=0), the sole OUTPUT (n_out=1): 2
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// real edges (src=4,w=2) [n4's own output, src_id<out_id holds:
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// 4<5], (src=2,w=7), same PARALLEL=4 padding (2x (src=0,w=0)).
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// sum = 49*2 + 4*7 + 0 + 0 = 126; +bias(0) = 126; none,
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// no saturation (126 <= 127) -> 126.
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//
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// Verifies (via hierarchical peeks at the DUT's private act_buffer
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// and at the psram_model backing store, consistent with this
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// repo's existing testbench style, e.g. psram_ctrl.state elsewhere):
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// - act_buf[0..3] hold the copied-in inputs.
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// - act_buf[4] == 49, act_buf[5] == 126 (gather + neuron_parallel
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// + padding all correct).
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// - the single output byte at out_base == 126 (folded WRITE_OUTPUTS
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// copy for the sink neuron).
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// - busy/done handshake behaves like the rest of the project's
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// orchestration modules.
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// ================================================================
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module tb;
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localparam ADDR_WIDTH = 23;
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localparam DATA_WIDTH = 8;
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localparam MEM_DATA_WIDTH = 16;
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localparam ACC_WIDTH = 32;
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localparam PARALLEL = 4;
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localparam MAX_CONN = 8;
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localparam N_TOTAL = 4096;
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localparam CLK_PERIOD = 12.5; // 80 MHz
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localparam ACT_NONE = 2'd0;
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localparam ACT_RELU = 2'd1;
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reg clk;
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reg rst;
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initial begin
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clk = 1'b0;
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forever #(CLK_PERIOD / 2.0) clk = ~clk;
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end
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// ============================================================
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// graph_engine
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// ============================================================
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reg run_start;
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wire busy;
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wire done;
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wire err;
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reg [ADDR_WIDTH-1:0] x_base;
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reg [ADDR_WIDTH-1:0] table_base;
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reg [ADDR_WIDTH-1:0] out_base;
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reg [15:0] n_inputs_graph;
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reg [15:0] num_neurons_graph;
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reg [15:0] n_out;
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wire ge_ram_req;
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wire ge_ram_wr;
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wire [ADDR_WIDTH-1:0] ge_ram_addr;
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wire signed [7:0] ge_ram_wdata;
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wire signed [7:0] ge_ram_rdata;
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wire ge_ram_ready;
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graph_engine #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.ACC_WIDTH(ACC_WIDTH),
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.PARALLEL(PARALLEL),
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.MAX_CONN(MAX_CONN),
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.N_TOTAL(N_TOTAL)
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) dut (
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.clk(clk), .rst(rst),
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.run_start(run_start), .busy(busy), .done(done), .err(err),
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.x_base(x_base), .table_base(table_base), .out_base(out_base),
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.n_inputs_graph(n_inputs_graph),
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.num_neurons_graph(num_neurons_graph),
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.n_out(n_out),
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.ram_req(ge_ram_req), .ram_wr(ge_ram_wr),
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.ram_addr(ge_ram_addr), .ram_wdata(ge_ram_wdata),
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.ram_rdata(ge_ram_rdata), .ram_ready(ge_ram_ready)
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);
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// ============================================================
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// Real memory stack, shared between two masters: the testbench
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// itself (for loading the graph before run_start) and
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// graph_engine (during the run). Mutually exclusive in time
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// (the tb only drives loader_* before run_start / after done),
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// so a simple wire-OR style mux keyed on `loading` is enough --
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// no arbiter needed for a unit-level testbench.
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// ============================================================
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reg loading;
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reg ld_req;
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reg ld_wr;
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reg [ADDR_WIDTH-1:0] ld_addr;
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reg signed [7:0] ld_wdata;
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wire mem_req = loading ? ld_req : ge_ram_req;
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wire mem_wr = loading ? ld_wr : ge_ram_wr;
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wire [ADDR_WIDTH-1:0] mem_addr = loading ? ld_addr : ge_ram_addr;
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wire signed [7:0] mem_wdata = loading ? ld_wdata : ge_ram_wdata;
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wire signed [7:0] mem_rdata;
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wire mem_ready;
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assign ge_ram_rdata = mem_rdata;
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assign ge_ram_ready = mem_ready;
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wire i8_mem_req, i8_mem_wr, i8_mem_lb_n, i8_mem_ub_n;
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wire [ADDR_WIDTH-1:0] i8_mem_addr;
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wire [MEM_DATA_WIDTH-1:0] i8_mem_wdata, i8_mem_rdata;
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wire i8_mem_ready;
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int8_memory_access #(
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.ADDR_WIDTH(ADDR_WIDTH)
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) u_int8_access (
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.clk(clk), .rst(rst),
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.req(mem_req), .wr(mem_wr), .addr(mem_addr), .wdata(mem_wdata),
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.rdata(mem_rdata), .ready(mem_ready),
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.mem_req(i8_mem_req), .mem_wr(i8_mem_wr), .mem_addr(i8_mem_addr),
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.mem_wdata(i8_mem_wdata), .mem_lb_n(i8_mem_lb_n), .mem_ub_n(i8_mem_ub_n),
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.mem_rdata(i8_mem_rdata), .mem_ready(i8_mem_ready)
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);
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wire psram_mem_req, psram_mem_wr, psram_mem_lb_n, psram_mem_ub_n;
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wire [ADDR_WIDTH-1:0] psram_mem_addr;
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wire [MEM_DATA_WIDTH-1:0] psram_mem_wdata, psram_mem_rdata;
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wire psram_mem_ready;
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memory_interface #(
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.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(MEM_DATA_WIDTH)
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) u_memory_if (
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.clk(clk), .rst(rst),
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.req(i8_mem_req), .wr(i8_mem_wr), .addr(i8_mem_addr), .wdata(i8_mem_wdata),
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.lb_n(i8_mem_lb_n), .ub_n(i8_mem_ub_n),
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.rdata(i8_mem_rdata), .ready(i8_mem_ready),
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.mem_req(psram_mem_req), .mem_wr(psram_mem_wr), .mem_addr(psram_mem_addr),
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.mem_wdata(psram_mem_wdata), .mem_lb_n(psram_mem_lb_n), .mem_ub_n(psram_mem_ub_n),
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.mem_rdata(psram_mem_rdata), .mem_ready(psram_mem_ready)
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);
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wire [ADDR_WIDTH-1:0] psram_a;
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wire [MEM_DATA_WIDTH-1:0] psram_dq;
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wire psram_ce_n, psram_oe_n, psram_we_n, psram_lb_n, psram_ub_n, psram_zz_n;
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psram_controller #(
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.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(MEM_DATA_WIDTH), .CLK_FREQ_MHZ(80)
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) psram_ctrl (
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.clk(clk), .rst(rst),
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.mem_req(psram_mem_req), .mem_wr(psram_mem_wr), .mem_addr(psram_mem_addr),
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.mem_wdata(psram_mem_wdata), .mem_lb_n(psram_mem_lb_n), .mem_ub_n(psram_mem_ub_n),
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.mem_rdata(psram_mem_rdata), .mem_ready(psram_mem_ready),
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.psram_a(psram_a), .psram_dq(psram_dq),
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.psram_ce_n(psram_ce_n), .psram_oe_n(psram_oe_n), .psram_we_n(psram_we_n),
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.psram_lb_n(psram_lb_n), .psram_ub_n(psram_ub_n), .psram_zz_n(psram_zz_n)
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);
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psram_model #(
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.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(MEM_DATA_WIDTH), .DEPTH(16384)
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) psram (
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.clk(clk), .a(psram_a), .dq(psram_dq),
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.ce_n(psram_ce_n), .oe_n(psram_oe_n), .we_n(psram_we_n),
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.lb_n(psram_lb_n), .ub_n(psram_ub_n), .zz_n(psram_zz_n)
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);
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// ============================================================
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// Loader tasks (testbench-side master, active only while
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// `loading` is asserted and graph_engine is idle)
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// ============================================================
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task ld_write(input [ADDR_WIDTH-1:0] a, input [7:0] d);
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begin
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@(posedge clk);
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ld_addr <= a; ld_wdata <= $signed(d); ld_wr <= 1'b1; ld_req <= 1'b1;
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@(posedge clk);
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ld_req <= 1'b0;
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wait (mem_ready);
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@(posedge clk);
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end
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endtask
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task write_graph_desc(
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input [ADDR_WIDTH-1:0] base, input [23:0] conn_ptr, input [15:0] n_conn,
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input [15:0] out_id, input [7:0] activation, input [7:0] bias
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);
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begin
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ld_write(base+0, conn_ptr[23:16]);
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ld_write(base+1, conn_ptr[15:8]);
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ld_write(base+2, conn_ptr[7:0]);
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ld_write(base+3, n_conn[15:8]);
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ld_write(base+4, n_conn[7:0]);
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ld_write(base+5, out_id[15:8]);
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ld_write(base+6, out_id[7:0]);
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ld_write(base+7, activation);
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ld_write(base+8, bias);
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ld_write(base+9, 8'h00);
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ld_write(base+10, 8'h00);
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end
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endtask
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task write_edge(input [ADDR_WIDTH-1:0] base, input [15:0] src_id, input [7:0] weight);
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begin
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ld_write(base+0, src_id[15:8]);
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ld_write(base+1, src_id[7:0]);
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ld_write(base+2, weight);
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ld_write(base+3, 8'h00);
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end
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endtask
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localparam X_BASE = 23'h001000;
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localparam TABLE_BASE = 23'h002000;
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localparam N4_EDGES = 23'h003000;
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localparam N5_EDGES = 23'h003100;
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localparam OUT_BASE = 23'h004000;
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integer errors;
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task check_word(input [ADDR_WIDTH-1:0] w_addr, input signed [15:0] expected, input [255:0] name);
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reg signed [15:0] got;
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begin
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got = psram.mem[w_addr >> 1];
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if (got !== expected) begin
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$display("FAIL %0s: word_addr=0x%06x expected=%0d got=%0d", name, w_addr>>1, expected, got);
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errors = errors + 1;
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end else begin
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$display("PASS %0s: value=%0d", name, got);
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end
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end
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endtask
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task check_act(input [11:0] id, input signed [7:0] expected, input [255:0] name);
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reg signed [7:0] got;
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begin
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got = dut.u_act_buffer.mem[id];
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if (got !== expected) begin
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$display("FAIL %0s: act_buf[%0d] expected=%0d got=%0d", name, id, expected, got);
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errors = errors + 1;
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end else begin
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$display("PASS %0s: act_buf[%0d]=%0d", name, id, got);
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end
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end
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endtask
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task check_out_byte(input [ADDR_WIDTH-1:0] byte_addr, input signed [7:0] expected, input [255:0] name);
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reg [15:0] w;
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reg signed [7:0] got;
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begin
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w = psram.mem[byte_addr >> 1];
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got = byte_addr[0] ? w[15:8] : w[7:0];
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if (got !== expected) begin
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$display("FAIL %0s: byte_addr=0x%06x expected=%0d got=%0d", name, byte_addr, expected, got);
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errors = errors + 1;
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end else begin
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$display("PASS %0s: value=%0d", name, got);
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end
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end
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endtask
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integer timeout;
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initial begin
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errors = 0;
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loading = 1'b1;
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ld_req = 1'b0; ld_wr = 1'b0; ld_addr = 0; ld_wdata = 0;
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run_start = 1'b0;
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x_base = X_BASE; table_base = TABLE_BASE; out_base = OUT_BASE;
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n_inputs_graph = 16'd4;
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num_neurons_graph = 16'd2;
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n_out = 16'd1;
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rst = 1'b1;
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repeat (5) @(posedge clk);
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rst = 1'b0;
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wait (psram_ctrl.state == psram_ctrl.STATE_IDLE);
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$display("");
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$display("========================================");
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$display("GRAPH_ENGINE CORE TEST (Phase G3)");
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$display("========================================");
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$display("");
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// ---- load inputs ----
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ld_write(X_BASE+0, 8'sd10); // x0
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ld_write(X_BASE+1, 8'sd1); // x1
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ld_write(X_BASE+2, 8'sd4); // x2
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ld_write(X_BASE+3, 8'sd0); // x3 (unused)
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// ---- descriptor table (out_id ascending: n4 then n5) ----
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write_graph_desc(TABLE_BASE+0*11, N4_EDGES, 16'd2, 16'd4, {6'b0, ACT_RELU}, 8'sd2);
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write_graph_desc(TABLE_BASE+1*11, N5_EDGES, 16'd2, 16'd5, {6'b0, ACT_NONE}, 8'sd0);
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// ---- n4 edges: 2 real + 2 host-inserted zero-weight padding ----
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write_edge(N4_EDGES+0*4, 16'd0, 8'sd5);
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write_edge(N4_EDGES+1*4, 16'd1, -8'sd3);
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write_edge(N4_EDGES+2*4, 16'd0, 8'sd0); // padding
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write_edge(N4_EDGES+3*4, 16'd0, 8'sd0); // padding
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// ---- n5 edges: 2 real (incl. src=n4's own out_id=4) + 2 padding ----
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write_edge(N5_EDGES+0*4, 16'd4, 8'sd2);
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write_edge(N5_EDGES+1*4, 16'd2, 8'sd7);
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write_edge(N5_EDGES+2*4, 16'd0, 8'sd0); // padding
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write_edge(N5_EDGES+3*4, 16'd0, 8'sd0); // padding
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loading = 1'b0;
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@(posedge clk);
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$display("-- load done, starting graph run --");
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$display("");
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// ---- run ----
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run_start <= 1'b1;
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@(posedge clk);
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run_start <= 1'b0;
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timeout = 0;
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while (!done && timeout < 5000) begin
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@(posedge clk);
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timeout = timeout + 1;
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end
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if (timeout >= 5000) begin
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$display("FAIL: TIMEOUT waiting for done (busy=%0b err=%0b)", busy, err);
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errors = errors + 1;
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end else begin
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$display("PASS: done asserted after %0d cycles (err=%0b)", timeout, err);
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end
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if (err !== 1'b0) begin
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$display("FAIL: err unexpectedly asserted on a valid graph");
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errors = errors + 1;
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end
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@(posedge clk);
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if (busy !== 1'b0) begin
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$display("FAIL: busy did not drop after done");
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errors = errors + 1;
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end
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$display("");
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$display("-- checking activation buffer --");
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check_act(0, 8'sd10, "act_buf input id0");
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check_act(1, 8'sd1, "act_buf input id1");
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check_act(2, 8'sd4, "act_buf input id2");
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check_act(3, 8'sd0, "act_buf input id3");
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check_act(4, 8'sd49, "act_buf n4 output (id4)");
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check_act(5, 8'sd126,"act_buf n5 output (id5)");
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$display("");
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$display("-- checking output copy to out_base --");
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// resume tb mastership to peek via a fresh read, but the
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// psram_model backing store can be inspected directly
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// regardless of which master last touched the bus.
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check_out_byte(OUT_BASE+0, 8'sd126, "out_base[0] (n5, the sole output)");
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$display("");
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if (errors == 0) begin
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$display("========================================");
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$display("GRAPH_ENGINE CORE TEST PASSED (0 errors)");
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$display("========================================");
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end else begin
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$display("========================================");
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$display("GRAPH_ENGINE CORE TEST FAILED (%0d errors)", errors);
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$display("========================================");
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$fatal;
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end
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$finish;
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end
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endmodule
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