micheleandClaude Sonnet 5
1a6f0ba2ef
Both Phase 2 findings (docs/FPGA-NeuralNetwork-Engine.md) shared one root cause: GROUPS = N_INPUTS / PARALLEL is integer division. When N_INPUTS is not an exact multiple of PARALLEL, the remainder inputs were silently dropped from the accumulation (wrong result, no error); when PARALLEL > N_INPUTS, GROUPS = 0 and the controller's terminal condition was never met, hanging the neuron forever. Added a single elaboration-time guard to rtl/neuron_parallel.v: a `generate` block instantiates a deliberately undefined module when N_INPUTS % PARALLEL != 0, forcing a hard failure in both simulation and synthesis instead of a silent wrong answer or a deadlock. Valid configurations are unaffected (the branch is never elaborated). The validated datapath (mac8/mac_unit/accumulation/ReLU/saturation) is untouched -- this is authorized as a scoped exception to the "core is fixed, do not touch" project policy, for this guard only. - sim/neuron_parallel_guard_negative_nonmultiple_tb.v and sim/neuron_parallel_guard_negative_degenerate_tb.v: negative tests that must fail to elaborate; verified both fail with the expected "Unknown module type" error. - sim/parameter_sweep_tb.v: rewritten to valid-configs-only (the three configs that used to demonstrate truncation/hang no longer compile, by design); added PARALLEL=2 and PARALLEL=4 configs, the two best-performing values from docs/FPGA-Neural-Datapatch-Benchmark.md. - Full regression re-run after the RTL change: all existing testbenches still pass unchanged. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt
3741 lines
72 KiB
Plaintext
3741 lines
72 KiB
Plaintext
$date
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Wed Sep 2 14:41:17 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1ps
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$end
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$scope module tb $end
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$var wire 64 ! y_bus [63:0] $end
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$var wire 1 " done $end
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$var wire 1 # busy $end
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$var parameter 32 $ ACC_WIDTH $end
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$var parameter 32 % DATA_WIDTH $end
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$var parameter 32 & N_INPUTS $end
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$var parameter 32 ' N_NEURONS $end
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$var parameter 32 ( PARALLEL $end
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$var reg 64 ) bias_bus [63:0] $end
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$var reg 1 * clk $end
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$var reg 1 + rst $end
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$var reg 1 , start $end
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$var reg 2048 - weights_bus [2047:0] $end
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$var reg 256 . x_bus [255:0] $end
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$var integer 32 / errors [31:0] $end
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$var integer 32 0 i [31:0] $end
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$scope module dut $end
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$var wire 64 1 bias_bus [63:0] $end
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$var wire 1 * clk $end
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$var wire 1 + rst $end
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$var wire 1 , start $end
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$var wire 2048 2 weights_bus [2047:0] $end
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$var wire 256 3 x_bus [255:0] $end
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$var wire 64 4 y_bus [63:0] $end
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$var wire 8 5 neuron_done [7:0] $end
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$var wire 8 6 neuron_busy [7:0] $end
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$var wire 1 " done $end
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$var wire 1 # busy $end
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$var parameter 32 7 ACC_WIDTH $end
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$var parameter 32 8 DATA_WIDTH $end
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$var parameter 32 9 N_INPUTS $end
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$var parameter 32 : N_NEURONS $end
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$var parameter 32 ; PARALLEL $end
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$scope begin GEN_NEURON[0] $end
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$var parameter 2 < n $end
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$scope module u_neuron $end
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$var wire 8 = bias [7:0] $end
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$var wire 1 * clk $end
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$var wire 1 + rst $end
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$var wire 1 , start $end
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$var wire 256 > w_bus [255:0] $end
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$var wire 256 ? x_bus [255:0] $end
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$var wire 64 @ x_group [63:0] $end
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$var wire 64 A w_group [63:0] $end
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$var wire 32 B final_acc [31:0] $end
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$var wire 32 C bias_ext [31:0] $end
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$var wire 32 D acc_next [31:0] $end
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$var parameter 32 E ACC_WIDTH $end
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$var parameter 32 F DATA_WIDTH $end
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$var parameter 32 G GROUPS $end
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$var parameter 32 H GROUP_INDEX_WIDTH $end
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$var parameter 32 I N_INPUTS $end
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$var parameter 32 J PARALLEL $end
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$var reg 32 K acc [31:0] $end
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$var reg 1 L busy $end
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$var reg 1 M done $end
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$var reg 2 N group_index [1:0] $end
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$var reg 8 O y [7:0] $end
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$scope module u_mac8 $end
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$var wire 32 P acc_in [31:0] $end
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$var wire 64 Q w_bus [63:0] $end
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$var wire 64 R x_bus [63:0] $end
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$var wire 32 S acc_out [31:0] $end
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$var parameter 32 T ACC_WIDTH $end
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$var parameter 32 U DATA_WIDTH $end
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$var parameter 32 V PARALLEL $end
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$var parameter 32 W TREE_LEVELS $end
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$scope begin GEN_MAC[0] $end
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$var parameter 2 X i $end
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$scope module u_mac $end
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$var wire 32 Y acc_in [31:0] $end
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$var wire 8 Z w [7:0] $end
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$var wire 8 [ x [7:0] $end
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$var wire 32 \ product_ext [31:0] $end
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$var wire 16 ] product [15:0] $end
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$var wire 32 ^ acc_out [31:0] $end
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$var parameter 32 _ ACC_WIDTH $end
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$var parameter 32 ` DATA_WIDTH $end
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$var parameter 64 a PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[1] $end
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$var parameter 2 b i $end
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$scope module u_mac $end
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$var wire 32 c acc_in [31:0] $end
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$var wire 8 d w [7:0] $end
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$var wire 8 e x [7:0] $end
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$var wire 32 f product_ext [31:0] $end
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$var wire 16 g product [15:0] $end
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$var wire 32 h acc_out [31:0] $end
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$var parameter 32 i ACC_WIDTH $end
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$var parameter 32 j DATA_WIDTH $end
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$var parameter 64 k PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[2] $end
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$var parameter 3 l i $end
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$scope module u_mac $end
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$var wire 32 m acc_in [31:0] $end
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$var wire 8 n w [7:0] $end
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$var wire 8 o x [7:0] $end
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$var wire 32 p product_ext [31:0] $end
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$var wire 16 q product [15:0] $end
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$var wire 32 r acc_out [31:0] $end
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$var parameter 32 s ACC_WIDTH $end
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$var parameter 32 t DATA_WIDTH $end
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$var parameter 64 u PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[3] $end
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$var parameter 3 v i $end
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$scope module u_mac $end
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$var wire 32 w acc_in [31:0] $end
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$var wire 8 x w [7:0] $end
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$var wire 8 y x [7:0] $end
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$var wire 32 z product_ext [31:0] $end
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$var wire 16 { product [15:0] $end
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$var wire 32 | acc_out [31:0] $end
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$var parameter 32 } ACC_WIDTH $end
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$var parameter 32 ~ DATA_WIDTH $end
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$var parameter 64 !" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[4] $end
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$var parameter 4 "" i $end
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$scope module u_mac $end
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$var wire 32 #" acc_in [31:0] $end
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$var wire 8 $" w [7:0] $end
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$var wire 8 %" x [7:0] $end
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$var wire 32 &" product_ext [31:0] $end
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$var wire 16 '" product [15:0] $end
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$var wire 32 (" acc_out [31:0] $end
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$var parameter 32 )" ACC_WIDTH $end
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$var parameter 32 *" DATA_WIDTH $end
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$var parameter 64 +" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[5] $end
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$var parameter 4 ," i $end
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$scope module u_mac $end
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$var wire 32 -" acc_in [31:0] $end
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$var wire 8 ." w [7:0] $end
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$var wire 8 /" x [7:0] $end
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$var wire 32 0" product_ext [31:0] $end
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$var wire 16 1" product [15:0] $end
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$var wire 32 2" acc_out [31:0] $end
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$var parameter 32 3" ACC_WIDTH $end
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$var parameter 32 4" DATA_WIDTH $end
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$var parameter 64 5" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[6] $end
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$var parameter 4 6" i $end
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$scope module u_mac $end
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$var wire 32 7" acc_in [31:0] $end
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$var wire 8 8" w [7:0] $end
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$var wire 8 9" x [7:0] $end
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$var wire 32 :" product_ext [31:0] $end
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$var wire 16 ;" product [15:0] $end
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$var wire 32 <" acc_out [31:0] $end
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$var parameter 32 =" ACC_WIDTH $end
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$var parameter 32 >" DATA_WIDTH $end
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$var parameter 64 ?" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[7] $end
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$var parameter 4 @" i $end
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$scope module u_mac $end
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$var wire 32 A" acc_in [31:0] $end
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$var wire 8 B" w [7:0] $end
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$var wire 8 C" x [7:0] $end
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$var wire 32 D" product_ext [31:0] $end
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$var wire 16 E" product [15:0] $end
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$var wire 32 F" acc_out [31:0] $end
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$var parameter 32 G" ACC_WIDTH $end
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$var parameter 32 H" DATA_WIDTH $end
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$var parameter 64 I" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[0] $end
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$var parameter 2 J" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[1] $end
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$var parameter 2 K" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[2] $end
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$var parameter 3 L" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[3] $end
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$var parameter 3 M" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[4] $end
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$var parameter 4 N" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[5] $end
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$var parameter 4 O" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[6] $end
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$var parameter 4 P" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[7] $end
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$var parameter 4 Q" i $end
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$upscope $end
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$scope begin GEN_TREE_LEVEL[0] $end
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$var parameter 2 R" level $end
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$scope begin GEN_TREE_NODE[0] $end
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$var parameter 2 S" node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[1] $end
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$var parameter 2 T" node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[2] $end
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$var parameter 3 U" node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[3] $end
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$var parameter 3 V" node $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_LEVEL[1] $end
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$var parameter 2 W" level $end
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$scope begin GEN_TREE_NODE[0] $end
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$var parameter 2 X" node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[1] $end
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$var parameter 2 Y" node $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_LEVEL[2] $end
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$var parameter 3 Z" level $end
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$scope begin GEN_TREE_NODE[0] $end
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$var parameter 2 [" node $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope begin GEN_NEURON[1] $end
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$var parameter 2 \" n $end
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$scope module u_neuron $end
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$var wire 8 ]" bias [7:0] $end
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$var wire 1 * clk $end
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$var wire 1 + rst $end
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$var wire 1 , start $end
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$var wire 256 ^" w_bus [255:0] $end
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$var wire 256 _" x_bus [255:0] $end
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$var wire 64 `" x_group [63:0] $end
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$var wire 64 a" w_group [63:0] $end
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$var wire 32 b" final_acc [31:0] $end
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$var wire 32 c" bias_ext [31:0] $end
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$var wire 32 d" acc_next [31:0] $end
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$var parameter 32 e" ACC_WIDTH $end
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$var parameter 32 f" DATA_WIDTH $end
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$var parameter 32 g" GROUPS $end
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$var parameter 32 h" GROUP_INDEX_WIDTH $end
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$var parameter 32 i" N_INPUTS $end
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$var parameter 32 j" PARALLEL $end
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$var reg 32 k" acc [31:0] $end
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$var reg 1 l" busy $end
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$var reg 1 m" done $end
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$var reg 2 n" group_index [1:0] $end
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$var reg 8 o" y [7:0] $end
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$scope module u_mac8 $end
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$var wire 32 p" acc_in [31:0] $end
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$var wire 64 q" w_bus [63:0] $end
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$var wire 64 r" x_bus [63:0] $end
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$var wire 32 s" acc_out [31:0] $end
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$var parameter 32 t" ACC_WIDTH $end
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$var parameter 32 u" DATA_WIDTH $end
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$var parameter 32 v" PARALLEL $end
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$var parameter 32 w" TREE_LEVELS $end
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$scope begin GEN_MAC[0] $end
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$var parameter 2 x" i $end
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$scope module u_mac $end
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$var wire 32 y" acc_in [31:0] $end
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$var wire 8 z" w [7:0] $end
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$var wire 8 {" x [7:0] $end
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$var wire 32 |" product_ext [31:0] $end
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$var wire 16 }" product [15:0] $end
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$var wire 32 ~" acc_out [31:0] $end
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$var parameter 32 !# ACC_WIDTH $end
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$var parameter 32 "# DATA_WIDTH $end
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$var parameter 64 ## PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[1] $end
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$var parameter 2 $# i $end
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$scope module u_mac $end
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$var wire 32 %# acc_in [31:0] $end
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$var wire 8 &# w [7:0] $end
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$var wire 8 '# x [7:0] $end
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$var wire 32 (# product_ext [31:0] $end
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$var wire 16 )# product [15:0] $end
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$var wire 32 *# acc_out [31:0] $end
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$var parameter 32 +# ACC_WIDTH $end
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$var parameter 32 ,# DATA_WIDTH $end
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$var parameter 64 -# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[2] $end
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$var parameter 3 .# i $end
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$scope module u_mac $end
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$var wire 32 /# acc_in [31:0] $end
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$var wire 8 0# w [7:0] $end
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$var wire 8 1# x [7:0] $end
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$var wire 32 2# product_ext [31:0] $end
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$var wire 16 3# product [15:0] $end
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$var wire 32 4# acc_out [31:0] $end
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$var parameter 32 5# ACC_WIDTH $end
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$var parameter 32 6# DATA_WIDTH $end
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$var parameter 64 7# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[3] $end
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$var parameter 3 8# i $end
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$scope module u_mac $end
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$var wire 32 9# acc_in [31:0] $end
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$var wire 8 :# w [7:0] $end
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$var wire 8 ;# x [7:0] $end
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$var wire 32 <# product_ext [31:0] $end
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$var wire 16 =# product [15:0] $end
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$var wire 32 ># acc_out [31:0] $end
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$var parameter 32 ?# ACC_WIDTH $end
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$var parameter 32 @# DATA_WIDTH $end
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$var parameter 64 A# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[4] $end
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$var parameter 4 B# i $end
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$scope module u_mac $end
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$var wire 32 C# acc_in [31:0] $end
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$var wire 8 D# w [7:0] $end
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$var wire 8 E# x [7:0] $end
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$var wire 32 F# product_ext [31:0] $end
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$var wire 16 G# product [15:0] $end
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$var wire 32 H# acc_out [31:0] $end
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$var parameter 32 I# ACC_WIDTH $end
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$var parameter 32 J# DATA_WIDTH $end
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$var parameter 64 K# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[5] $end
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$var parameter 4 L# i $end
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$scope module u_mac $end
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$var wire 32 M# acc_in [31:0] $end
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$var wire 8 N# w [7:0] $end
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$var wire 8 O# x [7:0] $end
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$var wire 32 P# product_ext [31:0] $end
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$var wire 16 Q# product [15:0] $end
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$var wire 32 R# acc_out [31:0] $end
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$var parameter 32 S# ACC_WIDTH $end
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$var parameter 32 T# DATA_WIDTH $end
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$var parameter 64 U# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[6] $end
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$var parameter 4 V# i $end
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$scope module u_mac $end
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$var wire 32 W# acc_in [31:0] $end
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$var wire 8 X# w [7:0] $end
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$var wire 8 Y# x [7:0] $end
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$var wire 32 Z# product_ext [31:0] $end
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$var wire 16 [# product [15:0] $end
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$var wire 32 \# acc_out [31:0] $end
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$var parameter 32 ]# ACC_WIDTH $end
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$var parameter 32 ^# DATA_WIDTH $end
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$var parameter 64 _# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[7] $end
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$var parameter 4 `# i $end
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$scope module u_mac $end
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$var wire 32 a# acc_in [31:0] $end
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$var wire 8 b# w [7:0] $end
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$var wire 8 c# x [7:0] $end
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$var wire 32 d# product_ext [31:0] $end
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$var wire 16 e# product [15:0] $end
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$var wire 32 f# acc_out [31:0] $end
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$var parameter 32 g# ACC_WIDTH $end
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$var parameter 32 h# DATA_WIDTH $end
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$var parameter 64 i# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[0] $end
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$var parameter 2 j# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[1] $end
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$var parameter 2 k# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[2] $end
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$var parameter 3 l# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[3] $end
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$var parameter 3 m# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[4] $end
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$var parameter 4 n# i $end
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|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 o# i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 p# i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 q# i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 r# level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 s# node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 t# node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 u# node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 v# node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 w# level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 x# node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 y# node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 z# level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 {# node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[2] $end
|
|
$var parameter 3 |# n $end
|
|
$scope module u_neuron $end
|
|
$var wire 8 }# bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 256 ~# w_bus [255:0] $end
|
|
$var wire 256 !$ x_bus [255:0] $end
|
|
$var wire 64 "$ x_group [63:0] $end
|
|
$var wire 64 #$ w_group [63:0] $end
|
|
$var wire 32 $$ final_acc [31:0] $end
|
|
$var wire 32 %$ bias_ext [31:0] $end
|
|
$var wire 32 &$ acc_next [31:0] $end
|
|
$var parameter 32 '$ ACC_WIDTH $end
|
|
$var parameter 32 ($ DATA_WIDTH $end
|
|
$var parameter 32 )$ GROUPS $end
|
|
$var parameter 32 *$ GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 +$ N_INPUTS $end
|
|
$var parameter 32 ,$ PARALLEL $end
|
|
$var reg 32 -$ acc [31:0] $end
|
|
$var reg 1 .$ busy $end
|
|
$var reg 1 /$ done $end
|
|
$var reg 2 0$ group_index [1:0] $end
|
|
$var reg 8 1$ y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 2$ acc_in [31:0] $end
|
|
$var wire 64 3$ w_bus [63:0] $end
|
|
$var wire 64 4$ x_bus [63:0] $end
|
|
$var wire 32 5$ acc_out [31:0] $end
|
|
$var parameter 32 6$ ACC_WIDTH $end
|
|
$var parameter 32 7$ DATA_WIDTH $end
|
|
$var parameter 32 8$ PARALLEL $end
|
|
$var parameter 32 9$ TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 :$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 ;$ acc_in [31:0] $end
|
|
$var wire 8 <$ w [7:0] $end
|
|
$var wire 8 =$ x [7:0] $end
|
|
$var wire 32 >$ product_ext [31:0] $end
|
|
$var wire 16 ?$ product [15:0] $end
|
|
$var wire 32 @$ acc_out [31:0] $end
|
|
$var parameter 32 A$ ACC_WIDTH $end
|
|
$var parameter 32 B$ DATA_WIDTH $end
|
|
$var parameter 64 C$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 D$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 E$ acc_in [31:0] $end
|
|
$var wire 8 F$ w [7:0] $end
|
|
$var wire 8 G$ x [7:0] $end
|
|
$var wire 32 H$ product_ext [31:0] $end
|
|
$var wire 16 I$ product [15:0] $end
|
|
$var wire 32 J$ acc_out [31:0] $end
|
|
$var parameter 32 K$ ACC_WIDTH $end
|
|
$var parameter 32 L$ DATA_WIDTH $end
|
|
$var parameter 64 M$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 N$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 O$ acc_in [31:0] $end
|
|
$var wire 8 P$ w [7:0] $end
|
|
$var wire 8 Q$ x [7:0] $end
|
|
$var wire 32 R$ product_ext [31:0] $end
|
|
$var wire 16 S$ product [15:0] $end
|
|
$var wire 32 T$ acc_out [31:0] $end
|
|
$var parameter 32 U$ ACC_WIDTH $end
|
|
$var parameter 32 V$ DATA_WIDTH $end
|
|
$var parameter 64 W$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 X$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 Y$ acc_in [31:0] $end
|
|
$var wire 8 Z$ w [7:0] $end
|
|
$var wire 8 [$ x [7:0] $end
|
|
$var wire 32 \$ product_ext [31:0] $end
|
|
$var wire 16 ]$ product [15:0] $end
|
|
$var wire 32 ^$ acc_out [31:0] $end
|
|
$var parameter 32 _$ ACC_WIDTH $end
|
|
$var parameter 32 `$ DATA_WIDTH $end
|
|
$var parameter 64 a$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 b$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 c$ acc_in [31:0] $end
|
|
$var wire 8 d$ w [7:0] $end
|
|
$var wire 8 e$ x [7:0] $end
|
|
$var wire 32 f$ product_ext [31:0] $end
|
|
$var wire 16 g$ product [15:0] $end
|
|
$var wire 32 h$ acc_out [31:0] $end
|
|
$var parameter 32 i$ ACC_WIDTH $end
|
|
$var parameter 32 j$ DATA_WIDTH $end
|
|
$var parameter 64 k$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 l$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 m$ acc_in [31:0] $end
|
|
$var wire 8 n$ w [7:0] $end
|
|
$var wire 8 o$ x [7:0] $end
|
|
$var wire 32 p$ product_ext [31:0] $end
|
|
$var wire 16 q$ product [15:0] $end
|
|
$var wire 32 r$ acc_out [31:0] $end
|
|
$var parameter 32 s$ ACC_WIDTH $end
|
|
$var parameter 32 t$ DATA_WIDTH $end
|
|
$var parameter 64 u$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 v$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 w$ acc_in [31:0] $end
|
|
$var wire 8 x$ w [7:0] $end
|
|
$var wire 8 y$ x [7:0] $end
|
|
$var wire 32 z$ product_ext [31:0] $end
|
|
$var wire 16 {$ product [15:0] $end
|
|
$var wire 32 |$ acc_out [31:0] $end
|
|
$var parameter 32 }$ ACC_WIDTH $end
|
|
$var parameter 32 ~$ DATA_WIDTH $end
|
|
$var parameter 64 !% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 "% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 #% acc_in [31:0] $end
|
|
$var wire 8 $% w [7:0] $end
|
|
$var wire 8 %% x [7:0] $end
|
|
$var wire 32 &% product_ext [31:0] $end
|
|
$var wire 16 '% product [15:0] $end
|
|
$var wire 32 (% acc_out [31:0] $end
|
|
$var parameter 32 )% ACC_WIDTH $end
|
|
$var parameter 32 *% DATA_WIDTH $end
|
|
$var parameter 64 +% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 ,% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 -% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 .% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 /% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 0% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 1% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 2% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 3% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 4% level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 5% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 6% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 7% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 8% node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 9% level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 :% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 ;% node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 <% level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 =% node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[3] $end
|
|
$var parameter 3 >% n $end
|
|
$scope module u_neuron $end
|
|
$var wire 8 ?% bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 256 @% w_bus [255:0] $end
|
|
$var wire 256 A% x_bus [255:0] $end
|
|
$var wire 64 B% x_group [63:0] $end
|
|
$var wire 64 C% w_group [63:0] $end
|
|
$var wire 32 D% final_acc [31:0] $end
|
|
$var wire 32 E% bias_ext [31:0] $end
|
|
$var wire 32 F% acc_next [31:0] $end
|
|
$var parameter 32 G% ACC_WIDTH $end
|
|
$var parameter 32 H% DATA_WIDTH $end
|
|
$var parameter 32 I% GROUPS $end
|
|
$var parameter 32 J% GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 K% N_INPUTS $end
|
|
$var parameter 32 L% PARALLEL $end
|
|
$var reg 32 M% acc [31:0] $end
|
|
$var reg 1 N% busy $end
|
|
$var reg 1 O% done $end
|
|
$var reg 2 P% group_index [1:0] $end
|
|
$var reg 8 Q% y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 R% acc_in [31:0] $end
|
|
$var wire 64 S% w_bus [63:0] $end
|
|
$var wire 64 T% x_bus [63:0] $end
|
|
$var wire 32 U% acc_out [31:0] $end
|
|
$var parameter 32 V% ACC_WIDTH $end
|
|
$var parameter 32 W% DATA_WIDTH $end
|
|
$var parameter 32 X% PARALLEL $end
|
|
$var parameter 32 Y% TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 Z% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 [% acc_in [31:0] $end
|
|
$var wire 8 \% w [7:0] $end
|
|
$var wire 8 ]% x [7:0] $end
|
|
$var wire 32 ^% product_ext [31:0] $end
|
|
$var wire 16 _% product [15:0] $end
|
|
$var wire 32 `% acc_out [31:0] $end
|
|
$var parameter 32 a% ACC_WIDTH $end
|
|
$var parameter 32 b% DATA_WIDTH $end
|
|
$var parameter 64 c% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 d% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 e% acc_in [31:0] $end
|
|
$var wire 8 f% w [7:0] $end
|
|
$var wire 8 g% x [7:0] $end
|
|
$var wire 32 h% product_ext [31:0] $end
|
|
$var wire 16 i% product [15:0] $end
|
|
$var wire 32 j% acc_out [31:0] $end
|
|
$var parameter 32 k% ACC_WIDTH $end
|
|
$var parameter 32 l% DATA_WIDTH $end
|
|
$var parameter 64 m% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 n% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 o% acc_in [31:0] $end
|
|
$var wire 8 p% w [7:0] $end
|
|
$var wire 8 q% x [7:0] $end
|
|
$var wire 32 r% product_ext [31:0] $end
|
|
$var wire 16 s% product [15:0] $end
|
|
$var wire 32 t% acc_out [31:0] $end
|
|
$var parameter 32 u% ACC_WIDTH $end
|
|
$var parameter 32 v% DATA_WIDTH $end
|
|
$var parameter 64 w% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 x% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 y% acc_in [31:0] $end
|
|
$var wire 8 z% w [7:0] $end
|
|
$var wire 8 {% x [7:0] $end
|
|
$var wire 32 |% product_ext [31:0] $end
|
|
$var wire 16 }% product [15:0] $end
|
|
$var wire 32 ~% acc_out [31:0] $end
|
|
$var parameter 32 !& ACC_WIDTH $end
|
|
$var parameter 32 "& DATA_WIDTH $end
|
|
$var parameter 64 #& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 $& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 %& acc_in [31:0] $end
|
|
$var wire 8 && w [7:0] $end
|
|
$var wire 8 '& x [7:0] $end
|
|
$var wire 32 (& product_ext [31:0] $end
|
|
$var wire 16 )& product [15:0] $end
|
|
$var wire 32 *& acc_out [31:0] $end
|
|
$var parameter 32 +& ACC_WIDTH $end
|
|
$var parameter 32 ,& DATA_WIDTH $end
|
|
$var parameter 64 -& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 .& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 /& acc_in [31:0] $end
|
|
$var wire 8 0& w [7:0] $end
|
|
$var wire 8 1& x [7:0] $end
|
|
$var wire 32 2& product_ext [31:0] $end
|
|
$var wire 16 3& product [15:0] $end
|
|
$var wire 32 4& acc_out [31:0] $end
|
|
$var parameter 32 5& ACC_WIDTH $end
|
|
$var parameter 32 6& DATA_WIDTH $end
|
|
$var parameter 64 7& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 8& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 9& acc_in [31:0] $end
|
|
$var wire 8 :& w [7:0] $end
|
|
$var wire 8 ;& x [7:0] $end
|
|
$var wire 32 <& product_ext [31:0] $end
|
|
$var wire 16 =& product [15:0] $end
|
|
$var wire 32 >& acc_out [31:0] $end
|
|
$var parameter 32 ?& ACC_WIDTH $end
|
|
$var parameter 32 @& DATA_WIDTH $end
|
|
$var parameter 64 A& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 B& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 C& acc_in [31:0] $end
|
|
$var wire 8 D& w [7:0] $end
|
|
$var wire 8 E& x [7:0] $end
|
|
$var wire 32 F& product_ext [31:0] $end
|
|
$var wire 16 G& product [15:0] $end
|
|
$var wire 32 H& acc_out [31:0] $end
|
|
$var parameter 32 I& ACC_WIDTH $end
|
|
$var parameter 32 J& DATA_WIDTH $end
|
|
$var parameter 64 K& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 L& i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 M& i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 N& i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 O& i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 P& i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 Q& i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 R& i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 S& i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 T& level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 U& node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 V& node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 W& node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 X& node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 Y& level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 Z& node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 [& node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 \& level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 ]& node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[4] $end
|
|
$var parameter 4 ^& n $end
|
|
$scope module u_neuron $end
|
|
$var wire 8 _& bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 256 `& w_bus [255:0] $end
|
|
$var wire 256 a& x_bus [255:0] $end
|
|
$var wire 64 b& x_group [63:0] $end
|
|
$var wire 64 c& w_group [63:0] $end
|
|
$var wire 32 d& final_acc [31:0] $end
|
|
$var wire 32 e& bias_ext [31:0] $end
|
|
$var wire 32 f& acc_next [31:0] $end
|
|
$var parameter 32 g& ACC_WIDTH $end
|
|
$var parameter 32 h& DATA_WIDTH $end
|
|
$var parameter 32 i& GROUPS $end
|
|
$var parameter 32 j& GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 k& N_INPUTS $end
|
|
$var parameter 32 l& PARALLEL $end
|
|
$var reg 32 m& acc [31:0] $end
|
|
$var reg 1 n& busy $end
|
|
$var reg 1 o& done $end
|
|
$var reg 2 p& group_index [1:0] $end
|
|
$var reg 8 q& y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 r& acc_in [31:0] $end
|
|
$var wire 64 s& w_bus [63:0] $end
|
|
$var wire 64 t& x_bus [63:0] $end
|
|
$var wire 32 u& acc_out [31:0] $end
|
|
$var parameter 32 v& ACC_WIDTH $end
|
|
$var parameter 32 w& DATA_WIDTH $end
|
|
$var parameter 32 x& PARALLEL $end
|
|
$var parameter 32 y& TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 z& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 {& acc_in [31:0] $end
|
|
$var wire 8 |& w [7:0] $end
|
|
$var wire 8 }& x [7:0] $end
|
|
$var wire 32 ~& product_ext [31:0] $end
|
|
$var wire 16 !' product [15:0] $end
|
|
$var wire 32 "' acc_out [31:0] $end
|
|
$var parameter 32 #' ACC_WIDTH $end
|
|
$var parameter 32 $' DATA_WIDTH $end
|
|
$var parameter 64 %' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 &' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 '' acc_in [31:0] $end
|
|
$var wire 8 (' w [7:0] $end
|
|
$var wire 8 )' x [7:0] $end
|
|
$var wire 32 *' product_ext [31:0] $end
|
|
$var wire 16 +' product [15:0] $end
|
|
$var wire 32 ,' acc_out [31:0] $end
|
|
$var parameter 32 -' ACC_WIDTH $end
|
|
$var parameter 32 .' DATA_WIDTH $end
|
|
$var parameter 64 /' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 0' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 1' acc_in [31:0] $end
|
|
$var wire 8 2' w [7:0] $end
|
|
$var wire 8 3' x [7:0] $end
|
|
$var wire 32 4' product_ext [31:0] $end
|
|
$var wire 16 5' product [15:0] $end
|
|
$var wire 32 6' acc_out [31:0] $end
|
|
$var parameter 32 7' ACC_WIDTH $end
|
|
$var parameter 32 8' DATA_WIDTH $end
|
|
$var parameter 64 9' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 :' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 ;' acc_in [31:0] $end
|
|
$var wire 8 <' w [7:0] $end
|
|
$var wire 8 =' x [7:0] $end
|
|
$var wire 32 >' product_ext [31:0] $end
|
|
$var wire 16 ?' product [15:0] $end
|
|
$var wire 32 @' acc_out [31:0] $end
|
|
$var parameter 32 A' ACC_WIDTH $end
|
|
$var parameter 32 B' DATA_WIDTH $end
|
|
$var parameter 64 C' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 D' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 E' acc_in [31:0] $end
|
|
$var wire 8 F' w [7:0] $end
|
|
$var wire 8 G' x [7:0] $end
|
|
$var wire 32 H' product_ext [31:0] $end
|
|
$var wire 16 I' product [15:0] $end
|
|
$var wire 32 J' acc_out [31:0] $end
|
|
$var parameter 32 K' ACC_WIDTH $end
|
|
$var parameter 32 L' DATA_WIDTH $end
|
|
$var parameter 64 M' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 N' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 O' acc_in [31:0] $end
|
|
$var wire 8 P' w [7:0] $end
|
|
$var wire 8 Q' x [7:0] $end
|
|
$var wire 32 R' product_ext [31:0] $end
|
|
$var wire 16 S' product [15:0] $end
|
|
$var wire 32 T' acc_out [31:0] $end
|
|
$var parameter 32 U' ACC_WIDTH $end
|
|
$var parameter 32 V' DATA_WIDTH $end
|
|
$var parameter 64 W' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 X' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 Y' acc_in [31:0] $end
|
|
$var wire 8 Z' w [7:0] $end
|
|
$var wire 8 [' x [7:0] $end
|
|
$var wire 32 \' product_ext [31:0] $end
|
|
$var wire 16 ]' product [15:0] $end
|
|
$var wire 32 ^' acc_out [31:0] $end
|
|
$var parameter 32 _' ACC_WIDTH $end
|
|
$var parameter 32 `' DATA_WIDTH $end
|
|
$var parameter 64 a' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 b' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 c' acc_in [31:0] $end
|
|
$var wire 8 d' w [7:0] $end
|
|
$var wire 8 e' x [7:0] $end
|
|
$var wire 32 f' product_ext [31:0] $end
|
|
$var wire 16 g' product [15:0] $end
|
|
$var wire 32 h' acc_out [31:0] $end
|
|
$var parameter 32 i' ACC_WIDTH $end
|
|
$var parameter 32 j' DATA_WIDTH $end
|
|
$var parameter 64 k' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 l' i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 m' i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 n' i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 o' i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 p' i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 q' i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 r' i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 s' i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 t' level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 u' node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 v' node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 w' node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 x' node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 y' level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 z' node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 {' node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 |' level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 }' node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[5] $end
|
|
$var parameter 4 ~' n $end
|
|
$scope module u_neuron $end
|
|
$var wire 8 !( bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 256 "( w_bus [255:0] $end
|
|
$var wire 256 #( x_bus [255:0] $end
|
|
$var wire 64 $( x_group [63:0] $end
|
|
$var wire 64 %( w_group [63:0] $end
|
|
$var wire 32 &( final_acc [31:0] $end
|
|
$var wire 32 '( bias_ext [31:0] $end
|
|
$var wire 32 (( acc_next [31:0] $end
|
|
$var parameter 32 )( ACC_WIDTH $end
|
|
$var parameter 32 *( DATA_WIDTH $end
|
|
$var parameter 32 +( GROUPS $end
|
|
$var parameter 32 ,( GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 -( N_INPUTS $end
|
|
$var parameter 32 .( PARALLEL $end
|
|
$var reg 32 /( acc [31:0] $end
|
|
$var reg 1 0( busy $end
|
|
$var reg 1 1( done $end
|
|
$var reg 2 2( group_index [1:0] $end
|
|
$var reg 8 3( y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 4( acc_in [31:0] $end
|
|
$var wire 64 5( w_bus [63:0] $end
|
|
$var wire 64 6( x_bus [63:0] $end
|
|
$var wire 32 7( acc_out [31:0] $end
|
|
$var parameter 32 8( ACC_WIDTH $end
|
|
$var parameter 32 9( DATA_WIDTH $end
|
|
$var parameter 32 :( PARALLEL $end
|
|
$var parameter 32 ;( TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 <( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 =( acc_in [31:0] $end
|
|
$var wire 8 >( w [7:0] $end
|
|
$var wire 8 ?( x [7:0] $end
|
|
$var wire 32 @( product_ext [31:0] $end
|
|
$var wire 16 A( product [15:0] $end
|
|
$var wire 32 B( acc_out [31:0] $end
|
|
$var parameter 32 C( ACC_WIDTH $end
|
|
$var parameter 32 D( DATA_WIDTH $end
|
|
$var parameter 64 E( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 F( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 G( acc_in [31:0] $end
|
|
$var wire 8 H( w [7:0] $end
|
|
$var wire 8 I( x [7:0] $end
|
|
$var wire 32 J( product_ext [31:0] $end
|
|
$var wire 16 K( product [15:0] $end
|
|
$var wire 32 L( acc_out [31:0] $end
|
|
$var parameter 32 M( ACC_WIDTH $end
|
|
$var parameter 32 N( DATA_WIDTH $end
|
|
$var parameter 64 O( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 P( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 Q( acc_in [31:0] $end
|
|
$var wire 8 R( w [7:0] $end
|
|
$var wire 8 S( x [7:0] $end
|
|
$var wire 32 T( product_ext [31:0] $end
|
|
$var wire 16 U( product [15:0] $end
|
|
$var wire 32 V( acc_out [31:0] $end
|
|
$var parameter 32 W( ACC_WIDTH $end
|
|
$var parameter 32 X( DATA_WIDTH $end
|
|
$var parameter 64 Y( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 Z( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 [( acc_in [31:0] $end
|
|
$var wire 8 \( w [7:0] $end
|
|
$var wire 8 ]( x [7:0] $end
|
|
$var wire 32 ^( product_ext [31:0] $end
|
|
$var wire 16 _( product [15:0] $end
|
|
$var wire 32 `( acc_out [31:0] $end
|
|
$var parameter 32 a( ACC_WIDTH $end
|
|
$var parameter 32 b( DATA_WIDTH $end
|
|
$var parameter 64 c( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 d( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 e( acc_in [31:0] $end
|
|
$var wire 8 f( w [7:0] $end
|
|
$var wire 8 g( x [7:0] $end
|
|
$var wire 32 h( product_ext [31:0] $end
|
|
$var wire 16 i( product [15:0] $end
|
|
$var wire 32 j( acc_out [31:0] $end
|
|
$var parameter 32 k( ACC_WIDTH $end
|
|
$var parameter 32 l( DATA_WIDTH $end
|
|
$var parameter 64 m( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 n( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 o( acc_in [31:0] $end
|
|
$var wire 8 p( w [7:0] $end
|
|
$var wire 8 q( x [7:0] $end
|
|
$var wire 32 r( product_ext [31:0] $end
|
|
$var wire 16 s( product [15:0] $end
|
|
$var wire 32 t( acc_out [31:0] $end
|
|
$var parameter 32 u( ACC_WIDTH $end
|
|
$var parameter 32 v( DATA_WIDTH $end
|
|
$var parameter 64 w( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 x( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 y( acc_in [31:0] $end
|
|
$var wire 8 z( w [7:0] $end
|
|
$var wire 8 {( x [7:0] $end
|
|
$var wire 32 |( product_ext [31:0] $end
|
|
$var wire 16 }( product [15:0] $end
|
|
$var wire 32 ~( acc_out [31:0] $end
|
|
$var parameter 32 !) ACC_WIDTH $end
|
|
$var parameter 32 ") DATA_WIDTH $end
|
|
$var parameter 64 #) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 $) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 %) acc_in [31:0] $end
|
|
$var wire 8 &) w [7:0] $end
|
|
$var wire 8 ') x [7:0] $end
|
|
$var wire 32 () product_ext [31:0] $end
|
|
$var wire 16 )) product [15:0] $end
|
|
$var wire 32 *) acc_out [31:0] $end
|
|
$var parameter 32 +) ACC_WIDTH $end
|
|
$var parameter 32 ,) DATA_WIDTH $end
|
|
$var parameter 64 -) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 .) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 /) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 0) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 1) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 2) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 3) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 4) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 5) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 6) level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 7) node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 8) node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 9) node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 :) node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 ;) level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 <) node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 =) node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 >) level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 ?) node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[6] $end
|
|
$var parameter 4 @) n $end
|
|
$scope module u_neuron $end
|
|
$var wire 8 A) bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 256 B) w_bus [255:0] $end
|
|
$var wire 256 C) x_bus [255:0] $end
|
|
$var wire 64 D) x_group [63:0] $end
|
|
$var wire 64 E) w_group [63:0] $end
|
|
$var wire 32 F) final_acc [31:0] $end
|
|
$var wire 32 G) bias_ext [31:0] $end
|
|
$var wire 32 H) acc_next [31:0] $end
|
|
$var parameter 32 I) ACC_WIDTH $end
|
|
$var parameter 32 J) DATA_WIDTH $end
|
|
$var parameter 32 K) GROUPS $end
|
|
$var parameter 32 L) GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 M) N_INPUTS $end
|
|
$var parameter 32 N) PARALLEL $end
|
|
$var reg 32 O) acc [31:0] $end
|
|
$var reg 1 P) busy $end
|
|
$var reg 1 Q) done $end
|
|
$var reg 2 R) group_index [1:0] $end
|
|
$var reg 8 S) y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 T) acc_in [31:0] $end
|
|
$var wire 64 U) w_bus [63:0] $end
|
|
$var wire 64 V) x_bus [63:0] $end
|
|
$var wire 32 W) acc_out [31:0] $end
|
|
$var parameter 32 X) ACC_WIDTH $end
|
|
$var parameter 32 Y) DATA_WIDTH $end
|
|
$var parameter 32 Z) PARALLEL $end
|
|
$var parameter 32 [) TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 \) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 ]) acc_in [31:0] $end
|
|
$var wire 8 ^) w [7:0] $end
|
|
$var wire 8 _) x [7:0] $end
|
|
$var wire 32 `) product_ext [31:0] $end
|
|
$var wire 16 a) product [15:0] $end
|
|
$var wire 32 b) acc_out [31:0] $end
|
|
$var parameter 32 c) ACC_WIDTH $end
|
|
$var parameter 32 d) DATA_WIDTH $end
|
|
$var parameter 64 e) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 f) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 g) acc_in [31:0] $end
|
|
$var wire 8 h) w [7:0] $end
|
|
$var wire 8 i) x [7:0] $end
|
|
$var wire 32 j) product_ext [31:0] $end
|
|
$var wire 16 k) product [15:0] $end
|
|
$var wire 32 l) acc_out [31:0] $end
|
|
$var parameter 32 m) ACC_WIDTH $end
|
|
$var parameter 32 n) DATA_WIDTH $end
|
|
$var parameter 64 o) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 p) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 q) acc_in [31:0] $end
|
|
$var wire 8 r) w [7:0] $end
|
|
$var wire 8 s) x [7:0] $end
|
|
$var wire 32 t) product_ext [31:0] $end
|
|
$var wire 16 u) product [15:0] $end
|
|
$var wire 32 v) acc_out [31:0] $end
|
|
$var parameter 32 w) ACC_WIDTH $end
|
|
$var parameter 32 x) DATA_WIDTH $end
|
|
$var parameter 64 y) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 z) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 {) acc_in [31:0] $end
|
|
$var wire 8 |) w [7:0] $end
|
|
$var wire 8 }) x [7:0] $end
|
|
$var wire 32 ~) product_ext [31:0] $end
|
|
$var wire 16 !* product [15:0] $end
|
|
$var wire 32 "* acc_out [31:0] $end
|
|
$var parameter 32 #* ACC_WIDTH $end
|
|
$var parameter 32 $* DATA_WIDTH $end
|
|
$var parameter 64 %* PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 &* i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 '* acc_in [31:0] $end
|
|
$var wire 8 (* w [7:0] $end
|
|
$var wire 8 )* x [7:0] $end
|
|
$var wire 32 ** product_ext [31:0] $end
|
|
$var wire 16 +* product [15:0] $end
|
|
$var wire 32 ,* acc_out [31:0] $end
|
|
$var parameter 32 -* ACC_WIDTH $end
|
|
$var parameter 32 .* DATA_WIDTH $end
|
|
$var parameter 64 /* PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 0* i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 1* acc_in [31:0] $end
|
|
$var wire 8 2* w [7:0] $end
|
|
$var wire 8 3* x [7:0] $end
|
|
$var wire 32 4* product_ext [31:0] $end
|
|
$var wire 16 5* product [15:0] $end
|
|
$var wire 32 6* acc_out [31:0] $end
|
|
$var parameter 32 7* ACC_WIDTH $end
|
|
$var parameter 32 8* DATA_WIDTH $end
|
|
$var parameter 64 9* PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 :* i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 ;* acc_in [31:0] $end
|
|
$var wire 8 <* w [7:0] $end
|
|
$var wire 8 =* x [7:0] $end
|
|
$var wire 32 >* product_ext [31:0] $end
|
|
$var wire 16 ?* product [15:0] $end
|
|
$var wire 32 @* acc_out [31:0] $end
|
|
$var parameter 32 A* ACC_WIDTH $end
|
|
$var parameter 32 B* DATA_WIDTH $end
|
|
$var parameter 64 C* PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 D* i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 E* acc_in [31:0] $end
|
|
$var wire 8 F* w [7:0] $end
|
|
$var wire 8 G* x [7:0] $end
|
|
$var wire 32 H* product_ext [31:0] $end
|
|
$var wire 16 I* product [15:0] $end
|
|
$var wire 32 J* acc_out [31:0] $end
|
|
$var parameter 32 K* ACC_WIDTH $end
|
|
$var parameter 32 L* DATA_WIDTH $end
|
|
$var parameter 64 M* PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 N* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 O* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 P* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 Q* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 R* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 S* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 T* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 U* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 V* level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 W* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 X* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 Y* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 Z* node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 [* level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 \* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 ]* node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 ^* level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 _* node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[7] $end
|
|
$var parameter 4 `* n $end
|
|
$scope module u_neuron $end
|
|
$var wire 8 a* bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 256 b* w_bus [255:0] $end
|
|
$var wire 256 c* x_bus [255:0] $end
|
|
$var wire 64 d* x_group [63:0] $end
|
|
$var wire 64 e* w_group [63:0] $end
|
|
$var wire 32 f* final_acc [31:0] $end
|
|
$var wire 32 g* bias_ext [31:0] $end
|
|
$var wire 32 h* acc_next [31:0] $end
|
|
$var parameter 32 i* ACC_WIDTH $end
|
|
$var parameter 32 j* DATA_WIDTH $end
|
|
$var parameter 32 k* GROUPS $end
|
|
$var parameter 32 l* GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 m* N_INPUTS $end
|
|
$var parameter 32 n* PARALLEL $end
|
|
$var reg 32 o* acc [31:0] $end
|
|
$var reg 1 p* busy $end
|
|
$var reg 1 q* done $end
|
|
$var reg 2 r* group_index [1:0] $end
|
|
$var reg 8 s* y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 t* acc_in [31:0] $end
|
|
$var wire 64 u* w_bus [63:0] $end
|
|
$var wire 64 v* x_bus [63:0] $end
|
|
$var wire 32 w* acc_out [31:0] $end
|
|
$var parameter 32 x* ACC_WIDTH $end
|
|
$var parameter 32 y* DATA_WIDTH $end
|
|
$var parameter 32 z* PARALLEL $end
|
|
$var parameter 32 {* TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 |* i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 }* acc_in [31:0] $end
|
|
$var wire 8 ~* w [7:0] $end
|
|
$var wire 8 !+ x [7:0] $end
|
|
$var wire 32 "+ product_ext [31:0] $end
|
|
$var wire 16 #+ product [15:0] $end
|
|
$var wire 32 $+ acc_out [31:0] $end
|
|
$var parameter 32 %+ ACC_WIDTH $end
|
|
$var parameter 32 &+ DATA_WIDTH $end
|
|
$var parameter 64 '+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 (+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 )+ acc_in [31:0] $end
|
|
$var wire 8 *+ w [7:0] $end
|
|
$var wire 8 ++ x [7:0] $end
|
|
$var wire 32 ,+ product_ext [31:0] $end
|
|
$var wire 16 -+ product [15:0] $end
|
|
$var wire 32 .+ acc_out [31:0] $end
|
|
$var parameter 32 /+ ACC_WIDTH $end
|
|
$var parameter 32 0+ DATA_WIDTH $end
|
|
$var parameter 64 1+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 2+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 3+ acc_in [31:0] $end
|
|
$var wire 8 4+ w [7:0] $end
|
|
$var wire 8 5+ x [7:0] $end
|
|
$var wire 32 6+ product_ext [31:0] $end
|
|
$var wire 16 7+ product [15:0] $end
|
|
$var wire 32 8+ acc_out [31:0] $end
|
|
$var parameter 32 9+ ACC_WIDTH $end
|
|
$var parameter 32 :+ DATA_WIDTH $end
|
|
$var parameter 64 ;+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 <+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 =+ acc_in [31:0] $end
|
|
$var wire 8 >+ w [7:0] $end
|
|
$var wire 8 ?+ x [7:0] $end
|
|
$var wire 32 @+ product_ext [31:0] $end
|
|
$var wire 16 A+ product [15:0] $end
|
|
$var wire 32 B+ acc_out [31:0] $end
|
|
$var parameter 32 C+ ACC_WIDTH $end
|
|
$var parameter 32 D+ DATA_WIDTH $end
|
|
$var parameter 64 E+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 F+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 G+ acc_in [31:0] $end
|
|
$var wire 8 H+ w [7:0] $end
|
|
$var wire 8 I+ x [7:0] $end
|
|
$var wire 32 J+ product_ext [31:0] $end
|
|
$var wire 16 K+ product [15:0] $end
|
|
$var wire 32 L+ acc_out [31:0] $end
|
|
$var parameter 32 M+ ACC_WIDTH $end
|
|
$var parameter 32 N+ DATA_WIDTH $end
|
|
$var parameter 64 O+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 P+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 Q+ acc_in [31:0] $end
|
|
$var wire 8 R+ w [7:0] $end
|
|
$var wire 8 S+ x [7:0] $end
|
|
$var wire 32 T+ product_ext [31:0] $end
|
|
$var wire 16 U+ product [15:0] $end
|
|
$var wire 32 V+ acc_out [31:0] $end
|
|
$var parameter 32 W+ ACC_WIDTH $end
|
|
$var parameter 32 X+ DATA_WIDTH $end
|
|
$var parameter 64 Y+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 Z+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 [+ acc_in [31:0] $end
|
|
$var wire 8 \+ w [7:0] $end
|
|
$var wire 8 ]+ x [7:0] $end
|
|
$var wire 32 ^+ product_ext [31:0] $end
|
|
$var wire 16 _+ product [15:0] $end
|
|
$var wire 32 `+ acc_out [31:0] $end
|
|
$var parameter 32 a+ ACC_WIDTH $end
|
|
$var parameter 32 b+ DATA_WIDTH $end
|
|
$var parameter 64 c+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 d+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 e+ acc_in [31:0] $end
|
|
$var wire 8 f+ w [7:0] $end
|
|
$var wire 8 g+ x [7:0] $end
|
|
$var wire 32 h+ product_ext [31:0] $end
|
|
$var wire 16 i+ product [15:0] $end
|
|
$var wire 32 j+ acc_out [31:0] $end
|
|
$var parameter 32 k+ ACC_WIDTH $end
|
|
$var parameter 32 l+ DATA_WIDTH $end
|
|
$var parameter 64 m+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 n+ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 o+ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 p+ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 q+ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 r+ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 s+ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 t+ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 u+ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 v+ level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 w+ node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 x+ node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 y+ node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 z+ node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 {+ level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 |+ node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 }+ node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 ~+ level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 !, node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope task run_layer $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$enddefinitions $end
|
|
$comment Show the parameter values. $end
|
|
$dumpall
|
|
b0 !,
|
|
b10 ~+
|
|
b1 }+
|
|
b0 |+
|
|
b1 {+
|
|
b11 z+
|
|
b10 y+
|
|
b1 x+
|
|
b0 w+
|
|
b0 v+
|
|
b111 u+
|
|
b110 t+
|
|
b101 s+
|
|
b100 r+
|
|
b11 q+
|
|
b10 p+
|
|
b1 o+
|
|
b0 n+
|
|
b10000 m+
|
|
b1000 l+
|
|
b100000 k+
|
|
b111 d+
|
|
b10000 c+
|
|
b1000 b+
|
|
b100000 a+
|
|
b110 Z+
|
|
b10000 Y+
|
|
b1000 X+
|
|
b100000 W+
|
|
b101 P+
|
|
b10000 O+
|
|
b1000 N+
|
|
b100000 M+
|
|
b100 F+
|
|
b10000 E+
|
|
b1000 D+
|
|
b100000 C+
|
|
b11 <+
|
|
b10000 ;+
|
|
b1000 :+
|
|
b100000 9+
|
|
b10 2+
|
|
b10000 1+
|
|
b1000 0+
|
|
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1q*
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0p*
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b10101 s*
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b11010 f*
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b10101 h*
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b10101 w*
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b10101 o*
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b10101 t*
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1*
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#70000
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0*
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#75000
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0"
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b0 5
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0q*
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0Q)
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01(
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0o&
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0O%
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0/$
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0m"
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0M
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1*
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