michele
cfd5e98a0e
tools/fpga_benchmark.py: parametric Yosys + nextpnr-ecp5 benchmark harness for the LFE5U-45F-8BG381 (speed grade -8, 80 MHz target), sweeping PARALLEL over the neuron layer and parsing Fmax/LUT4/DFF/DSP utilization out of the nextpnr report into JSON/CSV. synth/ecp5/p2, p4, p8: real synthesis+PnR results backing the same-price-tier FPGA comparison (P2: 87.88 MHz PASS, P4: 75.01 MHz FAIL, P8: 147.62 MHz PASS -- non-monotonic, dominated by placement noise since the whole design uses <2% of the device's LUT4 fabric at every setting, and P8 notably maps to 0 DSP blocks vs 8/16 for P2/P4). synth/ecp5/top.v: benchmark harness top-level, reworked to generate deterministic non-constant X/weights/bias via `keep`-attributed generate blocks so Yosys can't constant-fold the datapath away. Also adds .gitignore for Python's __pycache__/*.pyc.
21 lines
568 B
Plaintext
21 lines
568 B
Plaintext
read_verilog -sv \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v
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hierarchy -top top
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proc
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flatten
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opt
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memory
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opt
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techmap
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opt
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abc -g simple
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clean
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synth_ecp5 -top top -json /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.json
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