micheleandClaude Sonnet 5
9e1f16db47
sdram_arbiter_hier.v: fixes EXP-0093's own real, traced P&R timing failure (flat 21-way req_wdata mux, route-delay-dominated). Reuses sdram_arbiter_n.v unmodified, twice: 4 leaf instances (NUM_REQ=5, one per group) + 1 top instance (NUM_REQ=5: 4 groups + host, host bypassed/unpipelined), one real pipeline register stage between levels. Isolated verification (tb_sdram_arbiter_hier.v): 23/23 PASS. Two real bugs found and fixed via signal tracing: a testbench helper not waiting for grant before firing req, and a genuine RTL lost-pulse bug at the leaf-to-top boundary (a transient one-shot request could be dropped if the top level was busy with a different group) -- fixed with a sticky per-group pending_req_r latch. Wired into n16_system_ddr3_top.v (drop-in). Real, full P&R re-run: WNS improved -0.913ns -> -0.646ns, TNS -690ns -> -97.5ns, failing endpoints 3021 -> 771 -- substantial, measured improvement, confirming the arbiter was correctly root-caused (bottleneck moved elsewhere: neural_processor_packed.v's own already-thin-margin MAC datapath, eroded by N=16's higher overall congestion). Functional xsim still 32/32 PASS. Timing not yet fully closed -- real next steps documented, not yet attempted without further direction. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
286 lines
16 KiB
Verilog
286 lines
16 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// V3 -- real, hierarchical 2-level arbiter for n16_system_ddr3_top.v
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// (EXP-0094), built to fix EXP-0093's own real, measured P&R timing
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// failure (WNS=-0.913ns on the real 155.039MHz clk_pll_i domain).
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//
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// REAL ROOT CAUSE THIS FIXES (traced via EXP-0093's own worst violated
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// path, not guessed): sdram_arbiter_n.v's own flat req_wdata/req_addr/
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// etc mux grew from a 3-way select at N=2 to a real 20/21-way select at
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// N=16 over a 256-bit-wide bus -- EXP-0093's own real post-route report
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// showed the delay dominated by ROUTE (73%), not logic (27%): this is a
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// real PHYSICAL problem (20 separately-placed PE/weight-fetch sources
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// all converging on one central mux at mig_native_adapter.v), not just
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// a logic-depth one.
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//
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// REAL FIX: reuse `sdram_arbiter_n.v` UNMODIFIED, twice, hierarchically
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// -- NOT a new arbitration algorithm, the SAME already-proven
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// combinational-first-grant/locked semantics, just applied at two
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// levels instead of one:
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// - LEAF level (4x, one per systolic_group.v): a real
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// `sdram_arbiter_n` instance with NUM_REQ=5 (1 weight-fetch + 4 PE
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// activation/writeback requesters of THAT group), physically local
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// to its own group's own real PEs -- short wires, small mux.
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// - TOP level (1x): a real `sdram_arbiter_n` instance with
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// NUM_REQ=5 (4 groups' own pipelined output + 1 host_mem_bridge.v,
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// unpipelined -- see below), deciding which GROUP gets the real
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// shared ctrl_* port this cycle.
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// - ONE real pipeline register stage, BOTH directions, between the
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// two levels (leaf's own ctrl_req/wr/addr/wdata/wmask -> top's own
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// req_*, AND top's own req_ready/req_busy/req_rdata -> leaf's own
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// ctrl_ready/ctrl_busy/ctrl_rdata) -- this is the real fix for the
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// route-delay-dominated critical path: it lets the placer/router
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// spread the two mux stages across two separate clock periods'
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// worth of physical budget instead of forcing all 20 sources to
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// settle into one central mux within a single cycle.
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//
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// REAL CORRECTNESS ARGUMENT (not asserted without derivation): EVERY
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// requester in this project (`act_tile_fetch.v`, `layer_prefetch_
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// ctrl.v`, `host_mem_bridge.v`) already keeps its own `mem_active`
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// asserted for the FULL duration of its own outstanding transaction,
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// only dropping it once it has genuinely seen its own completion --
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// this is the real invariant `sdram_arbiter_n.v`'s own `locked` state
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// already relies on for transactions that already span many real DDR3-
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// latency cycles today. The 2 extra real cycles of round-trip latency
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// this hierarchy adds (1 cycle each direction, GROUP-sourced traffic
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// only) are indistinguishable, from any requester's own point of view,
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// from "DDR3 was slightly slower this time" -- no new race is
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// introduced, because the LEAF's own `locked` state depends only on
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// its own local requesters' real `mem_active` signals, never on
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// response timing from the top level.
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//
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// REAL, DELIBERATE ASYMMETRY: `host_mem_bridge.v`'s own single real
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// requester slot BYPASSES the leaf/pipeline stage entirely, wired
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// directly into the top-level arbiter's own 5th slot -- it was never
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// the reported critical path (only one physical source, not 20), and
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// this keeps its own real round-trip latency completely unchanged from
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// today's flat design (no reason to add latency where there is no real
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// fan-in problem to fix).
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//
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// PRESERVES EXP-0066's real "own grant same cycle as own active"
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// requirement EXACTLY for all 21 real requesters: weight-fetch/PE
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// requesters see the LEAF's own combinational grant (unchanged
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// `sdram_arbiter_n.v` internals, just NUM_REQ=5 instead of 21); host
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// sees the TOP's own combinational grant directly. Only the underlying
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// ctrl_req/wdata/etc reaching mig_native_adapter.v is pipelined -- the
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// grant signal a requester actually polls is untouched.
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//
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// EXTERNAL PORT LIST: byte-for-byte identical shape to
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// `sdram_arbiter_n.v` (same NUM_REQ-wide req_active/req_grant/etc
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// arrays, same single ctrl_* port) -- a real drop-in replacement at
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// the `n16_system_ddr3_top.v` instantiation site, no change needed to
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// the surrounding req_active/req_grant/etc bus-slicing code there.
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// Real, fixed slot-index convention matched to n16_system_ddr3_top.v's
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// own real `GEN_GROUP` layout: slot g (g=0..N_GROUPS-1) = group g's
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// own weight-fetch; slot N_GROUPS+g*PES_PER_GROUP+p (p=0..PES_PER_
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// GROUP-1) = group g's own PE p; slot NUM_REQ-1 = host_mem_bridge.v.
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// ============================================================
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module sdram_arbiter_hier #(
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parameter N_GROUPS = 4,
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parameter PES_PER_GROUP = 4,
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parameter ADDR_WIDTH = 25,
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parameter BURST_LEN = 8,
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parameter NUM_REQ = N_GROUPS*(1+PES_PER_GROUP) + 1 // 21, this project's real N=16 topology
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)(
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input wire clk,
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input wire rst,
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input wire [NUM_REQ-1:0] req_active,
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output wire [NUM_REQ-1:0] req_grant,
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input wire [NUM_REQ-1:0] req_req,
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input wire [NUM_REQ-1:0] req_wr,
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input wire [NUM_REQ*ADDR_WIDTH-1:0] req_addr,
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input wire [NUM_REQ*32*BURST_LEN-1:0] req_wdata,
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input wire [NUM_REQ*4*BURST_LEN-1:0] req_wmask,
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output wire [NUM_REQ*32*BURST_LEN-1:0] req_rdata,
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output wire [NUM_REQ-1:0] req_ready,
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output wire [NUM_REQ-1:0] req_busy,
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output wire ctrl_req,
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output wire ctrl_wr,
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output wire [ADDR_WIDTH-1:0] ctrl_addr,
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output wire [32*BURST_LEN-1:0] ctrl_wdata,
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output wire [4*BURST_LEN-1:0] ctrl_wmask,
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input wire [32*BURST_LEN-1:0] ctrl_rdata,
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input wire ctrl_ready,
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input wire ctrl_busy
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);
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localparam GROUP_SIZE = 1 + PES_PER_GROUP; // 5: weight-fetch (local idx 0) + PES_PER_GROUP PEs (local idx 1..4)
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// ---- per-group leaf outputs (outgoing, pre-pipeline) ----
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wire [N_GROUPS-1:0] leaf_active_any;
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wire [N_GROUPS-1:0] leaf_ctrl_req, leaf_ctrl_wr;
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wire [N_GROUPS*ADDR_WIDTH-1:0] leaf_ctrl_addr;
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wire [N_GROUPS*32*BURST_LEN-1:0] leaf_ctrl_wdata;
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wire [N_GROUPS*4*BURST_LEN-1:0] leaf_ctrl_wmask;
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// ---- per-group leaf inputs (return path, post-pipeline) ----
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reg [N_GROUPS-1:0] leaf_ctrl_ready_reg, leaf_ctrl_busy_reg;
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reg [N_GROUPS*32*BURST_LEN-1:0] leaf_ctrl_rdata_reg;
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genvar lg;
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generate
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for (lg = 0; lg < N_GROUPS; lg = lg + 1) begin : GEN_LEAF
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// real, fixed slot map (matches n16_system_ddr3_top.v's own
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// GEN_GROUP layout exactly): local idx 0 = weight-fetch
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// (external slot lg, same relative priority it already has
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// today -- lower index than its own group's PEs), local idx
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// 1..PES_PER_GROUP = PEs 0..PES_PER_GROUP-1 (external slots
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// N_GROUPS+lg*PES_PER_GROUP .. +PES_PER_GROUP-1).
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wire [GROUP_SIZE-1:0] g_req_active = {req_active[N_GROUPS+lg*PES_PER_GROUP +: PES_PER_GROUP], req_active[lg]};
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wire [GROUP_SIZE-1:0] g_req_req = {req_req[N_GROUPS+lg*PES_PER_GROUP +: PES_PER_GROUP], req_req[lg]};
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wire [GROUP_SIZE-1:0] g_req_wr = {req_wr[N_GROUPS+lg*PES_PER_GROUP +: PES_PER_GROUP], req_wr[lg]};
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wire [GROUP_SIZE*ADDR_WIDTH-1:0] g_req_addr =
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{req_addr[(N_GROUPS+lg*PES_PER_GROUP)*ADDR_WIDTH +: PES_PER_GROUP*ADDR_WIDTH], req_addr[lg*ADDR_WIDTH +: ADDR_WIDTH]};
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wire [GROUP_SIZE*32*BURST_LEN-1:0] g_req_wdata =
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{req_wdata[(N_GROUPS+lg*PES_PER_GROUP)*32*BURST_LEN +: PES_PER_GROUP*32*BURST_LEN], req_wdata[lg*32*BURST_LEN +: 32*BURST_LEN]};
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wire [GROUP_SIZE*4*BURST_LEN-1:0] g_req_wmask =
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{req_wmask[(N_GROUPS+lg*PES_PER_GROUP)*4*BURST_LEN +: PES_PER_GROUP*4*BURST_LEN], req_wmask[lg*4*BURST_LEN +: 4*BURST_LEN]};
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wire [GROUP_SIZE-1:0] g_req_grant;
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wire [GROUP_SIZE*32*BURST_LEN-1:0] g_req_rdata;
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wire [GROUP_SIZE-1:0] g_req_ready, g_req_busy;
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sdram_arbiter_n #(.NUM_REQ(GROUP_SIZE), .ADDR_WIDTH(ADDR_WIDTH), .BURST_LEN(BURST_LEN)) u_leaf (
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.clk(clk), .rst(rst),
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.req_active(g_req_active), .req_grant(g_req_grant),
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.req_req(g_req_req), .req_wr(g_req_wr), .req_addr(g_req_addr),
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.req_wdata(g_req_wdata), .req_wmask(g_req_wmask),
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.req_rdata(g_req_rdata), .req_ready(g_req_ready), .req_busy(g_req_busy),
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.ctrl_req(leaf_ctrl_req[lg]), .ctrl_wr(leaf_ctrl_wr[lg]),
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.ctrl_addr(leaf_ctrl_addr[lg*ADDR_WIDTH +: ADDR_WIDTH]),
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.ctrl_wdata(leaf_ctrl_wdata[lg*32*BURST_LEN +: 32*BURST_LEN]),
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.ctrl_wmask(leaf_ctrl_wmask[lg*4*BURST_LEN +: 4*BURST_LEN]),
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.ctrl_rdata(leaf_ctrl_rdata_reg[lg*32*BURST_LEN +: 32*BURST_LEN]),
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.ctrl_ready(leaf_ctrl_ready_reg[lg]), .ctrl_busy(leaf_ctrl_busy_reg[lg])
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);
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assign leaf_active_any[lg] = |g_req_active;
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// un-concatenate the leaf's own real per-slot responses back
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// to their real external (global) slot positions -- these are
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// the LEAF's own combinational grant/ready/busy/rdata, so the
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// real EXP-0066 "own grant same cycle as own active"
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// requirement is preserved EXACTLY for every weight-fetch/PE
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// requester (see this file's own header).
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assign req_grant[lg] = g_req_grant[0];
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assign req_grant[N_GROUPS+lg*PES_PER_GROUP +: PES_PER_GROUP] = g_req_grant[GROUP_SIZE-1:1];
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assign req_ready[lg] = g_req_ready[0];
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assign req_ready[N_GROUPS+lg*PES_PER_GROUP +: PES_PER_GROUP] = g_req_ready[GROUP_SIZE-1:1];
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assign req_busy[lg] = g_req_busy[0];
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assign req_busy[N_GROUPS+lg*PES_PER_GROUP +: PES_PER_GROUP] = g_req_busy[GROUP_SIZE-1:1];
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assign req_rdata[lg*32*BURST_LEN +: 32*BURST_LEN] = g_req_rdata[0 +: 32*BURST_LEN];
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assign req_rdata[(N_GROUPS+lg*PES_PER_GROUP)*32*BURST_LEN +: PES_PER_GROUP*32*BURST_LEN] =
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g_req_rdata[32*BURST_LEN +: PES_PER_GROUP*32*BURST_LEN];
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end
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endgenerate
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// ---- real pipeline register, outgoing direction (leaf -> top) ----
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// REAL FIX (found via signal tracing, EXP-0094): `leaf_ctrl_req` is
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// a TRANSIENT one-shot pulse -- it mirrors the real underlying
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// requester's own one-shot ctrl_req (e.g. act_tile_fetch.v's own
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// S_MEMWAIT: `ctrl_req <= 1'b1` for exactly one real cycle). A bare
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// "register leaf_ctrl_req every cycle" pipeline (the first, broken
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// version of this file) loses that pulse whenever the TOP level is
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// still busy with a DIFFERENT group at the exact cycle it fires --
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// by the time TOP gets around to this group, the transient pulse
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// has already reverted to 0. Real, generalizable lost-pulse bug,
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// same EXP-0066 class, now hit at the leaf-to-top boundary because
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// (unlike the flat single-level arbiter, where the winning
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// requester's own grant and the physical controller's own
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// readiness to capture it are ALWAYS the same decision) a leaf's
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// own LOCAL grant (which a real requester correctly waits for
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// before firing req, confirmed via act_tile_fetch.v) does NOT
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// guarantee the TOP level is free to act on it the same cycle.
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// FIX: latch `pending_req_r` STICKY per group, from the first real
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// cycle `leaf_ctrl_req` pulses until the top level has genuinely
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// dispatched it (see the `pending_req_r` update below, placed after
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// `u_top` so it can reference `top_req_grant`/`top_req_req`) -- addr/
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// wr/wdata/wmask do NOT need the same treatment: the leaf stays
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// locked onto the SAME real requester for its entire transaction
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// (real requesters hold `mem_active` until truly done), so those
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// fields are already stable for as long as `pending_req_r` matters.
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reg [N_GROUPS-1:0] top_req_active_r, top_req_req_r, top_req_wr_r;
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reg [N_GROUPS*ADDR_WIDTH-1:0] top_req_addr_r;
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reg [N_GROUPS*32*BURST_LEN-1:0] top_req_wdata_r;
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reg [N_GROUPS*4*BURST_LEN-1:0] top_req_wmask_r;
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reg [N_GROUPS-1:0] pending_req_r;
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always @(posedge clk) begin
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if (rst) begin
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top_req_active_r <= {N_GROUPS{1'b0}};
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top_req_req_r <= {N_GROUPS{1'b0}};
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top_req_wr_r <= {N_GROUPS{1'b0}};
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top_req_addr_r <= {(N_GROUPS*ADDR_WIDTH){1'b0}};
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top_req_wdata_r <= {(N_GROUPS*32*BURST_LEN){1'b0}};
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top_req_wmask_r <= {(N_GROUPS*4*BURST_LEN){1'b0}};
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end else begin
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top_req_active_r <= leaf_active_any;
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top_req_req_r <= pending_req_r | leaf_ctrl_req;
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top_req_wr_r <= leaf_ctrl_wr;
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top_req_addr_r <= leaf_ctrl_addr;
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top_req_wdata_r <= leaf_ctrl_wdata;
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top_req_wmask_r <= leaf_ctrl_wmask;
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end
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end
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// ---- top-level arbiter: N_GROUPS (pipelined) + 1 host (direct,
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// unpipelined -- see this file's own header for why) ----
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localparam TOP_NUM_REQ = N_GROUPS + 1;
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wire [TOP_NUM_REQ-1:0] top_req_active = {req_active[NUM_REQ-1], top_req_active_r};
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wire [TOP_NUM_REQ-1:0] top_req_req = {req_req[NUM_REQ-1], top_req_req_r};
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wire [TOP_NUM_REQ-1:0] top_req_wr = {req_wr[NUM_REQ-1], top_req_wr_r};
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wire [TOP_NUM_REQ*ADDR_WIDTH-1:0] top_req_addr = {req_addr[(NUM_REQ-1)*ADDR_WIDTH +: ADDR_WIDTH], top_req_addr_r};
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wire [TOP_NUM_REQ*32*BURST_LEN-1:0] top_req_wdata = {req_wdata[(NUM_REQ-1)*32*BURST_LEN +: 32*BURST_LEN], top_req_wdata_r};
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wire [TOP_NUM_REQ*4*BURST_LEN-1:0] top_req_wmask = {req_wmask[(NUM_REQ-1)*4*BURST_LEN +: 4*BURST_LEN], top_req_wmask_r};
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wire [TOP_NUM_REQ-1:0] top_req_grant;
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wire [TOP_NUM_REQ*32*BURST_LEN-1:0] top_req_rdata;
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wire [TOP_NUM_REQ-1:0] top_req_ready, top_req_busy;
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sdram_arbiter_n #(.NUM_REQ(TOP_NUM_REQ), .ADDR_WIDTH(ADDR_WIDTH), .BURST_LEN(BURST_LEN)) u_top (
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.clk(clk), .rst(rst),
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.req_active(top_req_active), .req_grant(top_req_grant),
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.req_req(top_req_req), .req_wr(top_req_wr), .req_addr(top_req_addr),
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.req_wdata(top_req_wdata), .req_wmask(top_req_wmask),
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.req_rdata(top_req_rdata), .req_ready(top_req_ready), .req_busy(top_req_busy),
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.ctrl_req(ctrl_req), .ctrl_wr(ctrl_wr), .ctrl_addr(ctrl_addr),
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.ctrl_wdata(ctrl_wdata), .ctrl_wmask(ctrl_wmask),
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.ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy)
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);
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// pending_req_r update (see its own declaration above for the real
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// rationale): set the cycle a group's own leaf_ctrl_req first
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// pulses; clear the cycle the top level actually dispatches it
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// (its own grant AND req both true for that group simultaneously --
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// this can only happen several cycles after pending_req_r was set,
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// via the outgoing pipeline register, so there is no same-cycle
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// set/clear race for a single real request).
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wire [N_GROUPS-1:0] pending_clear = top_req_grant[N_GROUPS-1:0] & top_req_req[N_GROUPS-1:0];
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always @(posedge clk) begin
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if (rst) pending_req_r <= {N_GROUPS{1'b0}};
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else pending_req_r <= (pending_req_r | leaf_ctrl_req) & ~pending_clear;
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end
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// host's own external slot: direct, unpipelined (see header)
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assign req_grant[NUM_REQ-1] = top_req_grant[N_GROUPS];
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assign req_ready[NUM_REQ-1] = top_req_ready[N_GROUPS];
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assign req_busy[NUM_REQ-1] = top_req_busy[N_GROUPS];
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assign req_rdata[(NUM_REQ-1)*32*BURST_LEN +: 32*BURST_LEN] = top_req_rdata[N_GROUPS*32*BURST_LEN +: 32*BURST_LEN];
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// ---- real pipeline register, return direction (top -> leaf) ----
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always @(posedge clk) begin
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if (rst) begin
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leaf_ctrl_ready_reg <= {N_GROUPS{1'b0}};
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leaf_ctrl_busy_reg <= {N_GROUPS{1'b1}}; // safe default: "still busy" during reset/pipeline-fill
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leaf_ctrl_rdata_reg <= {(N_GROUPS*32*BURST_LEN){1'b0}};
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end else begin
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leaf_ctrl_ready_reg <= top_req_ready[N_GROUPS-1:0];
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leaf_ctrl_busy_reg <= top_req_busy[N_GROUPS-1:0];
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leaf_ctrl_rdata_reg <= top_req_rdata[N_GROUPS*32*BURST_LEN-1:0];
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end
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end
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endmodule
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