micheleandClaude Sonnet 5
9ca180a787
New hardware/v3/sim/tb_np_packed_layer_reuse.v: real SDR SDRAM -> layer_prefetch_ctrl.v -> layer_weight_buffer.v -> weight_tile_gather.v -> neural_processor_packed.v, ALL real synthesizable RTL (unlike EXP-0058, which still had a testbench-only gather step). First run: 15/16 PASS, 1 FAIL. Root-caused (not re-run away): a testbench handshake bug, not a DUT bug -- operand_valid was held one extra clock edge after each accepted tile, double-consuming stale data every tile on every pair. 15 of 16 "passed" only because this test's saturating outputs happened to clamp to the same value whether or not the accumulator was inflated -- disclosed as a real methodology risk, not swept under the rug. Fixed by dropping operand_valid the same delta the handshake is observed. Re-verified after the fix: 16/16 PASS, 0 errors, bit-exact against an independent golden model, through the complete real RTL path. Full writeup in hardware/v2/logs/experiments.log EXP-0062. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC