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FPGA-Neural/sim/memory_interface.vcd
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micheleandClaude Sonnet 5 07a48e401f fix: close 7 zero-value/mid-run guard gaps found in re-certification campaign 
Fixes all 7 bugs found in the FPGA-Neural re-certification campaign
(docs/validation/bugs.md, CERTIFICATION.md), per campaign policy that
fixes land as a commit separate from the analysis work (commits
313a199..77e74db):

- BUG-005 (CRITICAL): layer_sequencer.v -- RUN_NETWORK(num_layers=0)
  ran through 256 fabricated layers reading arbitrary PSRAM data as
  descriptors. Now an immediate no-op.
- BUG-007 (CRITICAL): spi_engine.v -- SET_NET_TYPE received mid-run
  remapped the arbiter mux and hung the in-progress engine. Now
  rejected while graph_busy/seq_busy, verified not to partially apply.
- BUG-002 (MEDIA): neuron_parallel.v -- N_INPUTS=0 bypassed the
  elaboration-time guard, leaving x_bus/w_bus undriven. Guard extended
  to reject N_INPUTS==0.
- BUG-003 (MEDIA): neuron_parallel.v -- n_inputs_real=0 at runtime had
  inconsistent behavior across repeated runs. Now an explicit early-out
  via the existing "finishing" completion path.
- BUG-004 (BASSA): neuron_memory.v -- n_neurons_real=0 silently ignored
  the limit. Fixed at all three entry points into the vulnerable
  termination checks (STATE_READ_X, STATE_READ_W, and the X->W
  dispatch).
- BUG-006 (BASSA): graph_engine.v -- num_neurons_graph=0 relied on an
  incidental guard rather than a real one. Now an explicit no-op.
- BUG-001 (INFO): removed sim/top.v, confirmed dead code from the
  pre-INT8 Q8.8 era.

Every bug-reproduction testbench is rewritten from observe-only to
hard-assert the fixed behavior (sim/*_bug00[2-7]*_tb.v), verified
individually and via a full regression (44 testbenches, 43 PASS, 0
FAIL/ERROR, 1 benchmark by design). Re-verified on the real toolchain
(Yosys synth_ecp5 + nextpnr-ecp5): 0 constraint errors, Fmax 68.65 MHz
(was 67.91 MHz, within known placement noise), critical path
structurally unchanged (neuron_parallel/mac8 accumulator carry chain).

Updates docs/validation/bugs.md and CERTIFICATION.md to reflect the
resolved state, and docs/FPGA-NeuralNetwork-Engine.md + the LaTeX
datasheet (IT/EN) with inline notes on each fixed edge case, closing
the datasheet/RTL gap flagged in C.13 of the original certification.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-04 20:29:05 +02:00

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$date
Fri Sep 4 20:17:10 2026
$end
$version
Icarus Verilog
$end
$timescale
1ps
$end
$scope module memory_interface_tb $end
$var wire 1 ! ready $end
$var wire 16 " rdata [15:0] $end
$var wire 1 # mem_wr $end
$var wire 16 $ mem_wdata [15:0] $end
$var wire 1 % mem_req $end
$var wire 1 & mem_ready $end
$var wire 16 ' mem_rdata [15:0] $end
$var wire 23 ( mem_addr [22:0] $end
$var parameter 32 ) ADDR_WIDTH $end
$var parameter 32 * DATA_WIDTH $end
$var reg 23 + addr [22:0] $end
$var reg 1 , clk $end
$var reg 1 - req $end
$var reg 1 . rst $end
$var reg 16 / wdata [15:0] $end
$var reg 1 0 wr $end
$scope module dut $end
$var wire 23 1 addr [22:0] $end
$var wire 1 , clk $end
$var wire 1 2 lb_n $end
$var wire 1 - req $end
$var wire 1 . rst $end
$var wire 1 3 ub_n $end
$var wire 16 4 wdata [15:0] $end
$var wire 1 0 wr $end
$var wire 1 & mem_ready $end
$var wire 16 5 mem_rdata [15:0] $end
$var parameter 32 6 ADDR_WIDTH $end
$var parameter 32 7 DATA_WIDTH $end
$var parameter 2 8 STATE_IDLE $end
$var parameter 2 9 STATE_WAIT $end
$var reg 23 : mem_addr [22:0] $end
$var reg 1 ; mem_lb_n $end
$var reg 1 % mem_req $end
$var reg 1 < mem_ub_n $end
$var reg 16 = mem_wdata [15:0] $end
$var reg 1 # mem_wr $end
$var reg 16 > rdata [15:0] $end
$var reg 1 ! ready $end
$var reg 2 ? state [1:0] $end
$upscope $end
$scope module memory $end
$var wire 23 @ addr [22:0] $end
$var wire 1 , clk $end
$var wire 1 % req $end
$var wire 1 . rst $end
$var wire 16 A wdata [15:0] $end
$var wire 1 # wr $end
$var parameter 32 B ADDR_WIDTH $end
$var parameter 32 C DATA_WIDTH $end
$var parameter 32 D DEPTH $end
$var parameter 32 E READ_LATENCY $end
$var reg 1 F busy $end
$var reg 23 G pending_addr [22:0] $end
$var reg 16 H pending_wdata [15:0] $end
$var reg 1 I pending_wr $end
$var reg 16 J rdata [15:0] $end
$var reg 1 & ready $end
$var integer 32 K delay_count [31:0] $end
$var integer 32 L i [31:0] $end
$upscope $end
$scope task read_mem $end
$var reg 23 M address [22:0] $end
$var reg 16 N expected [15:0] $end
$var reg 16 O received [15:0] $end
$upscope $end
$scope task write_mem $end
$var reg 23 P address [22:0] $end
$var reg 16 Q data [15:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b10 E
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$end
#0
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