FPGA-Neural

T

micheleandClaude Sonnet 5 996dda3415 feat: real functional xsim verification of N=16 hybrid systolic system (EXP-0092)

tb_n16_system_ddr3.v, adapted from tb_n2_system_ddr3.v's own real DDR3-
model methodology (real mig_7series_0_mig, real 2-chip ddr3_model.sv,
real Vivado xsim). Submits 32 positions across all 4 groups of
n16_system_ddr3_top.v's own real neural_director_grouped.v + 4x
systolic_group.v + 20-way arbiter. 32/32 PASS, 0 errors.

This confirms EXP-0091's synthesis-only result (0 errors, 128
DSP48E1/53.33%) reflected real functional correctness, not just
connectivity -- the grouped Director's octet dispatch, the new
arbiter's slot map, and the shared-weight-broadcast barrier all work
correctly wired together at full N=16 scale.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-21 00:31:02 +02:00

benchmark_results

feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results

2026-09-02 19:48:03 +02:00

docs

feat: real functional xsim verification of N=16 hybrid systolic system (EXP-0092)

2026-09-21 00:31:02 +02:00

hardware

feat: real functional xsim verification of N=16 hybrid systolic system (EXP-0092)

2026-09-21 00:31:02 +02:00

sim

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze